Commit Graph

205 Commits

Author SHA1 Message Date
Linus Torvalds cbda94e039 ARM: SoC: driver changes
These changes are mostly for ARM specific device drivers that either
 don't have an upstream maintainer, or that had the maintainer ask
 us to pick up the changes to avoid conflicts. A large chunk of this
 are clock drivers (bcm281xx, exynos, versatile, shmobile), aside from
 that, reset controllers for STi as well as a large rework of the
 Marvell Orion/EBU watchdog driver are notable.
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Merge tag 'drivers-3.15' of git://git.kernel.org/pub/scm/linux/kernel/git/arm/arm-soc

Pull ARM SoC driver changes from Arnd Bergmann:
 "These changes are mostly for ARM specific device drivers that either
  don't have an upstream maintainer, or that had the maintainer ask us
  to pick up the changes to avoid conflicts.

  A large chunk of this are clock drivers (bcm281xx, exynos, versatile,
  shmobile), aside from that, reset controllers for STi as well as a
  large rework of the Marvell Orion/EBU watchdog driver are notable"

* tag 'drivers-3.15' of git://git.kernel.org/pub/scm/linux/kernel/git/arm/arm-soc: (99 commits)
  Revert "dts: socfpga: Add DTS entry for adding the stmmac glue layer for stmmac."
  Revert "net: stmmac: Add SOCFPGA glue driver"
  ARM: shmobile: r8a7791: Fix SCIFA3-5 clocks
  ARM: STi: Add reset controller support to mach-sti Kconfig
  drivers: reset: stih416: add softreset controller
  drivers: reset: stih415: add softreset controller
  drivers: reset: Reset controller driver for STiH416
  drivers: reset: Reset controller driver for STiH415
  drivers: reset: STi SoC system configuration reset controller support
  dts: socfpga: Add sysmgr node so the gmac can use to reference
  dts: socfpga: Add support for SD/MMC on the SOCFPGA platform
  reset: Add optional resets and stubs
  ARM: shmobile: r7s72100: fix bus clock calculation
  Power: Reset: Generalize qnap-poweroff to work on Synology devices.
  dts: socfpga: Update clock entry to support multiple parents
  ARM: socfpga: Update socfpga_defconfig
  dts: socfpga: Add DTS entry for adding the stmmac glue layer for stmmac.
  net: stmmac: Add SOCFPGA glue driver
  watchdog: orion_wdt: Use %pa to print 'phys_addr_t'
  drivers: cci: Export CCI PMU revision
  ...
2014-04-05 15:37:40 -07:00
Linus Torvalds ff050ad12c ARM: SoC specific changes
Lots of changes specific to one of the SoC families. Some that
 stick out are:
 
 * mach-qcom gains new features, most importantly SMP support for
   the newer chips (Stephen Boyd, Rohit Vaswani)
 * mvebu gains support for three new SoCs: Armada 375, 380 and 385
   (Thomas Petazzoni and Free-electrons team)
 * SMP support for Rockchips (Heiko Stübner)
 * Lots of i.MX changes (Shawn Guo)
 * Added support for BCM5301x SoC (Hauke Mehrtens)
 * Multiplatform support for Marvell Kirkwood and Dove
   (Andrew Lunn and Sebastian Hesselbarth doing the final part
   of a long journey)
 * Unify davinci platforms and remove obsolete ones (Sekhar Nori,
   Arnd Bergmann)
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Merge tag 'soc-3.15' of git://git.kernel.org/pub/scm/linux/kernel/git/arm/arm-soc

Pull ARM SoC specific changes from Arnd Bergmann:
 "Lots of changes specific to one of the SoC families.  Some that stick
  out are:

   - mach-qcom gains new features, most importantly SMP support for the
     newer chips (Stephen Boyd, Rohit Vaswani)
   - mvebu gains support for three new SoCs: Armada 375, 380 and 385
     (Thomas Petazzoni and Free-electrons team)
   - SMP support for Rockchips (Heiko Stübner)
   - Lots of i.MX changes (Shawn Guo)
   - Added support for BCM5301x SoC (Hauke Mehrtens)
   - Multiplatform support for Marvell Kirkwood and Dove (Andrew Lunn
     and Sebastian Hesselbarth doing the final part of a long journey)
   - Unify davinci platforms and remove obsolete ones (Sekhar Nori, Arnd
     Bergmann)"

* tag 'soc-3.15' of git://git.kernel.org/pub/scm/linux/kernel/git/arm/arm-soc: (126 commits)
  ARM: sunxi: Select HAVE_ARM_ARCH_TIMER
  ARM: cache-tauros2: remove ARMv6 code
  ARM: mvebu: don't select CONFIG_NEON
  ARM: davinci: fix DT booting with default defconfig
  ARM: configs: bcm_defconfig: enable bcm590xx regulator support
  ARM: davinci: remove tnetv107x support
  MAINTAINERS: Update ARM STi maintainers
  ARM: restrict BCM_KONA_UART to ARCH_BCM_MOBILE
  ARM: bcm21664: Add board support.
  ARM: sunxi: Add the new watchog compatibles to the reboot code
  ARM: enable ARM_HAS_SG_CHAIN for multiplatform
  ARM: davinci: remove da8xx_omapl_defconfig
  ARM: davinci: da8xx: fix multiple watchdog device registration
  ARM: davinci: add da8xx specific configs to davinci_all_defconfig
  ARM: davinci: enable da8xx build concurrently with older devices
  ARM: BCM5301X: workaround suppress fault
  ARM: BCM5301X: add early debugging support
  ARM: BCM5301X: initial support for the BCM5301X/BCM470X SoCs with ARM CPU
  ARM: mach-bcm: Remove GENERIC_TIME
  ARM: shmobile: APMU: Fix warnings due to improper printk formats
  ...
2014-04-05 14:19:54 -07:00
Linus Torvalds dfc25e4503 ARM: SoC: cleanups for 3.15
These cleanup patches are mainly move stuff around and should all
 be harmless. They are mainly split out so that other branches can
 be based on top to avoid conflicts.
 
 Notable changes are:
 
 * We finally remove all mach/timex.h, after CLOCK_TICK_RATE is no
   longer used. (Uwe Kleine-König)
 * The Qualcomm MSM platform is split out into legacy mach-msm and
   new-style mach-qcom, to allow easier maintainance of the new
   hardware support without regressions. (Kumar Gala)
 * A rework of some of the Kconfig logic to simplify multiplatform
   support (Rob Herring)
 * Samsung Exynos gets closer to supporting multiplatform (Sachin
   Kamat and others)
 * mach-bcm3528 gets merged into mach-bcm (Stephen Warren)
 * at91 gains some common clock framework support (Alexandre Belloni,
   Jean-Jacques Hiblot and other French people).
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Merge tag 'cleanup-3.15' of git://git.kernel.org/pub/scm/linux/kernel/git/arm/arm-soc

Pull ARM SoC cleanups from Arnd Bergmann:
 "These cleanup patches are mainly move stuff around and should all be
  harmless.  They are mainly split out so that other branches can be
  based on top to avoid conflicts.

  Notable changes are:

   - We finally remove all mach/timex.h, after CLOCK_TICK_RATE is no
     longer used (Uwe Kleine-König)
   - The Qualcomm MSM platform is split out into legacy mach-msm and
     new-style mach-qcom, to allow easier maintainance of the new
     hardware support without regressions (Kumar Gala)
   - A rework of some of the Kconfig logic to simplify multiplatform
     support (Rob Herring)
   - Samsung Exynos gets closer to supporting multiplatform (Sachin
     Kamat and others)
   - mach-bcm3528 gets merged into mach-bcm (Stephen Warren)
   - at91 gains some common clock framework support (Alexandre Belloni,
     Jean-Jacques Hiblot and other French people)"

* tag 'cleanup-3.15' of git://git.kernel.org/pub/scm/linux/kernel/git/arm/arm-soc: (89 commits)
  ARM: hisi: select HAVE_ARM_SCU only for SMP
  ARM: efm32: allow uncompress debug output
  ARM: prima2: build reset code standalone
  ARM: at91: add PWM clock
  ARM: at91: move sam9261 SoC to common clk
  ARM: at91: prepare common clk transition for sam9261 SoC
  ARM: at91: updated the at91_dt_defconfig with support for the ADS7846
  ARM: at91: dt: sam9261: Device Tree support for the at91sam9261ek
  ARM: at91: dt: defconfig: Added the sam9261 to the list of DT-enabled SOCs
  ARM: at91: dt: Add at91sam9261 dt SoC support
  ARM: at91: switch sam9rl to common clock framework
  ARM: at91/dt: define main clk frequency of at91sam9rlek
  ARM: at91/dt: define at91sam9rl clocks
  ARM: at91: prepare common clk transition for sam9rl SoCs
  ARM: at91: prepare sam9 dt boards transition to common clk
  ARM: at91: dt: sam9rl: Device Tree for the at91sam9rlek
  ARM: at91/defconfig: Add the sam9rl to the list of DT-enabled SOCs
  ARM: at91: Add at91sam9rl DT SoC support
  ARM: at91: prepare at91sam9rl DT transition
  ARM: at91/defconfig: refresh at91sam9260_9g20_defconfig
  ...
2014-04-05 13:51:19 -07:00
Linus Torvalds 9f800363bb ARM: SoC non-critical bug fixes for 3.15
Lots of isolated bug fixes that were not found to be important
 enough to be submitted before the merge window or backported
 into stable kernels.
 The vast majority of these came out of Arnd's randconfig testing
 and just prevents running into build-time bugs in configurations
 that we do not care about in practice.
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Merge tag 'fixes-non-critical-3.15' of git://git.kernel.org/pub/scm/linux/kernel/git/arm/arm-soc

Pull ARM SoC non-critical bug fixes from Arnd Bergmann:
 "Lots of isolated bug fixes that were not found to be important enough
  to be submitted before the merge window or backported into stable
  kernels.

  The vast majority of these came out of Arnd's randconfig testing and
  just prevents running into build-time bugs in configurations that we
  do not care about in practice"

* tag 'fixes-non-critical-3.15' of git://git.kernel.org/pub/scm/linux/kernel/git/arm/arm-soc: (75 commits)
  ARM: at91: fix a typo
  ARM: moxart: fix CPU selection
  ARM: tegra: fix board DT pinmux setup
  ARM: nspire: Fix compiler warning
  IXP4xx: Fix DMA masks.
  Revert "ARM: ixp4xx: Make dma_set_coherent_mask common, correct implementation"
  IXP4xx: Fix Goramo Multilink GPIO conversion.
  Revert "ARM: ixp4xx: fix gpio rework"
  ARM: tegra: make debug_ll code build for ARMv6
  ARM: sunxi: fix build for THUMB2_KERNEL
  ARM: exynos: add missing include of linux/module.h
  ARM: exynos: fix l2x0 saved regs handling
  ARM: samsung: select CRC32 for SAMSUNG_PM_CHECK
  ARM: samsung: select ATAGS where necessary
  ARM: samsung: fix SAMSUNG_PM_DEBUG Kconfig logic
  ARM: samsung: allow serial driver to be disabled
  ARM: s5pv210: enable IDE support in MACH_TORBRECK
  ARM: s5p64x0: fix building with only one soc type
  ARM: s3c64xx: select power domains only when used
  ARM: s3c64xx: MACH_SMDK6400 needs HSMMC1
  ...
2014-04-05 13:44:27 -07:00
Hans de Goede 1b422ecd27 irqchip: sun7i/sun6i: Disable NMI before registering the handler
It is advisable to disable the NMI before registering the IRQ handler as
registering the IRQ handler unmasks the IRQ on the GIC, so if U-Boot has
left the NMI enabled and the NMI pin is active we will immediately get
an interrupt before any driver has claimed the downstream interrupt of
the NMI.

Signed-off-by: Hans de Goede <hdegoede@redhat.com>
Signed-off-by: Carlo Caione <carlo@caione.org>
Cc: maxime.ripard@free-electrons.com
Cc: linux-arm-kernel@lists.infradead.org
Cc: linux-sunxi@googlegroups.com
Link: http://lkml.kernel.org/r/1395939759-11135-3-git-send-email-carlo@caione.org
Signed-off-by: Thomas Gleixner <tglx@linutronix.de>
2014-03-31 11:12:57 +02:00
Carlo Caione 6058bb3628 ARM: sun7i/sun6i: irqchip: Add irqchip driver for NMI controller
Allwinner A20/A31 SoCs have special registers to control / (un)mask /
acknowledge NMI. This NMI controller is separated and independent from GIC.
This patch adds a new irqchip to manage NMI.

Signed-off-by: Carlo Caione <carlo@caione.org>
Acked-by: Maxime Ripard <maxime.ripard@free-electrons.com>
Cc: linux-arm-kernel@lists.infradead.org
Cc: linux-sunxi@googlegroups.com
Cc: mark.rutland@arm.com
Cc: hdegoede@redhat.com
Link: http://lkml.kernel.org/r/1395256879-8475-2-git-send-email-carlo@caione.org
Signed-off-by: Thomas Gleixner <tglx@linutronix.de>
2014-03-26 01:00:50 +01:00
Hans de Goede cc3b68fea2 irqchip: sun4i: Simplify sun4i_irq_ack
Now that we only ack irq 0 the code can be simplified a lot.

Also switch from read / modify / write to a simple write clear:
1) This is what the android code does (it has a hack for acking irq 0
   in its unmask code doing this)

2) read / modify / write simply does not make sense for an irq status
   register like this, if the other bits are writeable (and the data sheet says
   they are not) they should be write 1 to clear, since otherwise a read /
   modify / write can race with a device raising an interrupt and then clear
   the pending bit unintentionally

Signed-off-by: Hans de Goede <hdegoede@redhat.com>
Acked-by: Maxime Ripard <maxime.ripard@free-electrons.com>
Cc: linux-arm-kernel@lists.infradead.org
Cc: linux-sunxi@googlegroups.com
Link: http://lkml.kernel.org/r/1394895894-8891-3-git-send-email-hdegoede@redhat.com
Signed-off-by: Thomas Gleixner <tglx@linutronix.de>
2014-03-19 12:34:29 +01:00
Hans de Goede 915b78ce8e irqchip: sun4i: Use handle_fasteoi_irq for all interrupts
Since the sun4i irq chip does not require any action and clears the interrupt
when the level goes back to inactive, we don't need to mask / unmask for
non oneshot IRQs, to achieve this we make sun4i_irq_ack a nop for all irqs
except irq 0 and use handle_fasteoi_irq for all interrupts.

Now there might be a case when the device reactivates the interrupt
before the RETI. But that does not matter as we run the primary
interrupt handlers with interrupts disabled.

This also allows us to get rid of needing to use 2 irq_chip structs, this
means that the IRQCHIP_EOI_THREADED | IRQCHIP_EOI_IF_HANDLED will now influence
all interrupts rather then just irq 0, but that does not matter as the eoi
is now a nop anyways for all interrupts but irq 0.

Signed-off-by: Hans de Goede <hdegoede@redhat.com>
Acked-by: Maxime Ripard <maxime.ripard@free-electrons.com>
Cc: linux-arm-kernel@lists.infradead.org
Cc: linux-sunxi@googlegroups.com
Link: http://lkml.kernel.org/r/1394895894-8891-2-git-send-email-hdegoede@redhat.com
Signed-off-by: Thomas Gleixner <tglx@linutronix.de>
2014-03-19 12:34:29 +01:00
Arnd Bergmann f18651eb2c Fixes for omaps that would be good to get in before v3.15-rc1.
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Merge tag 'omap-for-v3.15/fixes-for-merge-window' of git://git.kernel.org/pub/scm/linux/kernel/git/tmlind/linux-omap into next/fixes-non-critical

Merge "omap fixes for v3.15 merge window" from Tony Lindgren:

Fixes for omaps that would be good to get in before v3.15-rc1.

* tag 'omap-for-v3.15/fixes-for-merge-window' of git://git.kernel.org/pub/scm/linux/kernel/git/tmlind/linux-omap:
  ARM: OMAP4: hwmod data: correct the idlemodes for spinlock
  ARM: dts: am33xx: correcting dt node unit address for usb
  ARM: dts: omap4/5: Use l3_ick for the gpmc node
  CLK: TI: OMAP4/5/DRA7: Remove gpmc_fck from dummy clocks
  ARM: OMAP4: Fix definition of IS_PM44XX_ERRATUM
  ARM: OMAP2+: INTC: Acknowledge stuck active interrupts

Signed-off-by: Arnd Bergmann <arnd@arndb.de>
2014-03-17 15:31:30 +01:00
Hans de Goede e9df9e2216 irqchip: sun4i: Don't ack IRQs > 0, fix acking of IRQ 0
All IRQs except for IRQ 0 seem to not need acking, so drop acking for them.

The ENMI needs to have the ack done *after* clearing the interrupt source,
otherwise we will get a spurious interrupt for each real interrupt.

So use the new IRQCHIP_EOI_THREADED flag for this in combination with
handle_fasteoi_irq. This uses a separate irq_chip struct for IRQ 0,
since we only want this behavior for IRQ 0.

Signed-off-by: Hans de Goede <hdegoede@redhat.com>
Cc: linux-arm-kernel@lists.infradead.org
Cc: linux-sunxi@googlegroups.com
Cc: Maxime Ripard <maxime.ripard@free-electrons.com>
Link: http://lkml.kernel.org/r/1394733834-26839-5-git-send-email-hdegoede@redhat.com
Signed-off-by: Thomas Gleixner <tglx@linutronix.de>
2014-03-14 13:43:33 +01:00
Hans de Goede 649ff46e5e irqchip: sun4i: Fix a comment about mask register initialization
The comment was claiming that we were masking all irqs, while the code actually
*un*masks all of them.

Signed-off-by: Hans de Goede <hdegoede@redhat.com>
Acked-by: Maxime Ripard <maxime.ripard@free-electrons.com>
Cc: linux-arm-kernel@lists.infradead.org
Cc: linux-sunxi@googlegroups.com
Link: http://lkml.kernel.org/r/1394733834-26839-4-git-send-email-hdegoede@redhat.com
Signed-off-by: Thomas Gleixner <tglx@linutronix.de>
2014-03-14 13:43:33 +01:00
Hans de Goede 56af0416b0 irqchip: sun4i: Fix irq 0 not working
SUN4I_IRQ_VECTOR_REG containing 0 can mean one of 3 things:

1) no more irqs pending
2) irq 0 pending
3) spurious irq

So if we immediately get a reading of 0, check the irq-pending reg
to differentiate between 2 and 3. We only do this once to avoid
the extra check in the common case of 1) hapening after having
read the vector-reg once.

Signed-off-by: Hans de Goede <hdegoede@redhat.com>
Acked-by: Maxime Ripard <maxime.ripard@free-electrons.com>
Cc: linux-arm-kernel@lists.infradead.org
Cc: linux-sunxi@googlegroups.com
Link: http://lkml.kernel.org/r/1394733834-26839-3-git-send-email-hdegoede@redhat.com
Signed-off-by: Thomas Gleixner <tglx@linutronix.de>
2014-03-14 13:43:33 +01:00
Maxime Ripard a7e8b4b519 irqchip: sunxi: Change compatibles
The Allwinner A10 compatibles were following a slightly different compatible
patterns than the rest of the SoCs for historical reasons. Change the compatibles
to match the other pattern in the irq controller driver for consistency.

Signed-off-by: Maxime Ripard <maxime.ripard@free-electrons.com>
Cc: linux-arm-kernel@lists.infradead.org
Signed-off-by: Thomas Gleixner <tglx@linutronix.de>
2014-03-14 13:43:32 +01:00
Thomas Gleixner ffb12cf002 Merge branch 'irq/for-gpio' into irq/core
Merge the request/release callbacks which are in a separate branch for
consumption by the gpio folks.

Signed-off-by: Thomas Gleixner <tglx@linutronix.de>
2014-03-12 16:01:07 +01:00
Stephen Boyd 1a75b8e645 irqchip: Remove unused include
The "irqchip.h" include here is not needed as the only thing in
irqchip.h is IRQCHIP_DECLARE which this file doesn't use. Drop
it.

Reported-by: Jiri Kosina <jkosina@suse.cz>
Signed-off-by: Stephen Boyd <sboyd@codeaurora.org>
Link: http://lkml.kernel.org/r/531F7765.40207@codeaurora.org
Signed-off-by: Thomas Gleixner <tglx@linutronix.de>
2014-03-12 13:12:04 +01:00
Stephen Boyd 8783dd3a37 irqchip: Remove asmlinkage from static functions
LTO patches add __visible to the asmlinkage define, causing
compilation warnings like:

  drivers/irqchip/irq-gic.c:283:1: warning: 'externally_visible'
  attribute have effect only on public objects [-Wattributes]

Drop asmlinkage here to avoid such warnings.

Reported-by: Olof's autobuilder <build@lixom.net>
Signed-off-by: Stephen Boyd <sboyd@codeaurora.org>
Cc: linux-arm-kernel@lists.infradead.org
Cc: khilman@linaro.org
Cc: Russell King <linux@arm.linux.org.uk>
Cc: Josh Cartwright <joshc@codeaurora.org>
Cc: Andi Kleen <ak@linux.intel.com>
Link: http://lkml.kernel.org/r/1393980030-17770-1-git-send-email-sboyd@codeaurora.org
Signed-off-by: Thomas Gleixner <tglx@linutronix.de>
2014-03-12 13:00:41 +01:00
Olof Johansson 1760e4f855 i.MX SoC changes for 3.15:
- Support suspend from ocram (DDR IO floating) for imx6 platforms
  - Add cpuidle support for imx6sl
  - Sparse warning fixes for imx6sl and vf610 clock code
  - Remove PWM platform code
  - Support ptp and rmii clock from pad
  - Support WEIM CS GPR configuration
  - Random cleanups and defconfig updates
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Merge tag 'imx-soc-3.15' of git://git.linaro.org/people/shawnguo/linux-2.6 into next/soc

i.MX SoC changes for 3.15 from Shawn Guo:
 - Support suspend from ocram (DDR IO floating) for imx6 platforms
 - Add cpuidle support for imx6sl
 - Sparse warning fixes for imx6sl and vf610 clock code
 - Remove PWM platform code
 - Support ptp and rmii clock from pad
 - Support WEIM CS GPR configuration
 - Random cleanups and defconfig updates

* tag 'imx-soc-3.15' of git://git.linaro.org/people/shawnguo/linux-2.6: (373 commits)
  ARM: imx6: drop .text.head section annotation from headsmp.S
  ARM: imx6: build suspend-imx6.o with CONFIG_SOC_IMX6
  ARM: imx6: rename pm-imx6q.c to pm-imx6.c
  ARM: imx6: introduce CONFIG_SOC_IMX6 for i.MX6 common stuff
  ARM: imx6: do not call imx6q_suspend_init() with !CONFIG_SUSPEND
  ARM: imx6: call suspend_set_ops() from suspend routine
  ARM: imx6: build headsmp.o only on CONFIG_SMP
  ARM: imx6: move v7_cpu_resume() into suspend-imx6.S
  ARM i.MX6q: Mark VPU and IPU AXI transfers as cacheable, increase IPU priority
  ARM: imx6q: Add GPR6 and GPR7 register definitions for iomuxc gpr
  bus: imx-weim: support CS GPR configuration
  ARM: mach-imx: Kconfig: Remove IMX_HAVE_PLATFORM_IMX2_WDT from SOC_IMX53
  ARM: imx_v6_v7_defconfig: Select CONFIG_DEBUG_FS
  ARM: mach-imx: Select CONFIG_SRAM at ARCH_MXC level
  ARM: imx: add speed grading check for i.mx6 soc
  ARM: imx: avoid calling clk APIs in idle thread which may cause schedule
  ARM: imx6q: support ptp and rmii clock from pad
  ARM: imx6q: remove unneeded clk lookups
  ARM: imx_v6_v7_defconfig: Select CONFIG_MMC_UNSAFE_RESUME
  ARM: imx_v4_v5_defconfig: Select CONFIG_MMC_UNSAFE_RESUME
  ...
2014-03-09 12:03:18 -07:00
Olof Johansson dba5bedb96 Merge tag 'irq-mmp' of https://git.kernel.org/pub/scm/linux/kernel/git/hzhuang1/linux into next/cleanup
Merge a mach header include removal from Haojian Zhuang.

* tag 'irq-mmp' of https://git.kernel.org/pub/scm/linux/kernel/git/hzhuang1/linux:
  irqchip: mmp: avoid use head file in a specific arch

Signed-off-by: Olof Johansson <olof@lixom.net>
2014-03-09 11:46:36 -07:00
Olof Johansson 687fb3c8a0 Samsung drivers update for v3.15
- remove inclusion <asm/mach/time.h> from exynos_mct.c
 - remove inclusion <asm/mach/irq.h> from exynos-combiner.c
   and use calling handle_bad_irq() instead of do_bad_IRQ()
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Merge tag 'samsung-drivers' of http://git.kernel.org/pub/scm/linux/kernel/git/kgene/linux-samsung into next/cleanup

Samsung drivers update for v3.15 from Kukjin Kim:
- remove inclusion <asm/mach/time.h> from exynos_mct.c
- remove inclusion <asm/mach/irq.h> from exynos-combiner.c
  and use calling handle_bad_irq() instead of do_bad_IRQ()

* tag 'samsung-drivers' of http://git.kernel.org/pub/scm/linux/kernel/git/kgene/linux-samsung:
  irqchip: exynos-combiner: call handle_bad_irq directly
  clocksource: exynos_mct: remove unwanted header file inclusion

Signed-off-by: Olof Johansson <olof@lixom.net>
2014-03-09 11:26:31 -07:00
Olof Johansson 63261d76c8 Add support for GIC crossbar that routes interrupts on newer omaps.
Looks like people wanted these merged via the omap tree as it's
 the only user for the GIC crossbar.
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Merge tag 'omap-for-v3.15/crossbar-signed' of git://git.kernel.org/pub/scm/linux/kernel/git/tmlind/linux-omap into next/drivers

Merge OMAP crossbar support from Tony Lindgren:

Add support for GIC crossbar that routes interrupts on newer omaps.

Looks like people wanted these merged via the omap tree as it's
the only user for the GIC crossbar.

* tag 'omap-for-v3.15/crossbar-signed' of git://git.kernel.org/pub/scm/linux/kernel/git/tmlind/linux-omap:
  ARM: DRA: Enable Crossbar IP support for DRA7XX
  ARM: OMAP4+: Correct Wakeup-gen code to use physical irq number
  DRIVERS: IRQCHIP: CROSSBAR: Add support for Crossbar IP
  DRIVERS: IRQCHIP: IRQ-GIC: Add support for routable irqs

Signed-off-by: Olof Johansson <olof@lixom.net>
2014-03-08 23:32:26 -08:00
Stephen Boyd 6859358e4b irqchip: gic: Silence sparse warnings
drivers/irqchip/irq-gic.c:53:23: warning: duplicate [noderef]
drivers/irqchip/irq-gic.c:651:6: warning: symbol 'gic_raise_softirq' was not declared. Should it be static?
drivers/irqchip/irq-gic.c:872:29: warning: symbol 'gic_irq_domain_ops' was not declared. Should it be static?
drivers/irqchip/irq-gic.c:977:12: warning: symbol 'gic_of_init' was not declared. Should it be static?

Signed-off-by: Stephen Boyd <sboyd@codeaurora.org>
Cc: linux-arm-kernel@lists.infradead.org
Link: http://lkml.kernel.org/r/1393981321-25721-1-git-send-email-sboyd@codeaurora.org
Signed-off-by: Thomas Gleixner <tglx@linutronix.de>
2014-03-06 11:40:47 +01:00
Stephen Boyd 559ba4b153 irqchip: Silence sparse warning
drivers/irqchip/irqchip.c:27:13: warning: symbol 'irqchip_init'
was not declared. Should it be static?

Signed-off-by: Stephen Boyd <sboyd@codeaurora.org>
Cc: trivial@kernel.org
Link: http://lkml.kernel.org/r/1393981281-25553-1-git-send-email-sboyd@codeaurora.org
Signed-off-by: Thomas Gleixner <tglx@linutronix.de>
2014-03-06 11:40:47 +01:00
Thomas Gleixner 5c331c8626 irqchip: xtensa: Select only an online cpu
The user space interface does not filter out offline cpus. It merily
verifies that the mask contains at least one online cpu. So the
selector in the irq chip implementation needs to make sure to pick
only an online cpu because otherwise:

     Offline Core 1
     Set affinity to 0xe
     Selector will pick first set bit, i.e. core 1

Signed-off-by: Thomas Gleixner <tglx@linutronix.de>
Cc: Chris Zankel <chris@zankel.net>
Cc: xtensa <linux-xtensa@linux-xtensa.org>
2014-03-04 17:37:55 +01:00
Jason Cooper eb9cf4e8ec Revert irqchip: irq-dove: Add PMU interrupt controller
This reverts commit 40b367d95f.

Russell King has raised the idea of creating a proper PMU driver for
this SoC that would incorporate the functionality currently in this
driver. It would also cover the use case for the graphics subsystem on
this SoC.

To prevent having to maintain the devicetree ABI for this limited
interrupt-handler driver, we revert the driver before it hits a mainline
tagged release (eg v3.15).

Signed-off-by: Jason Cooper <jason@lakedaemon.net>
Cc: linux-arm-kernel@lists.infradead.org
Cc: Andrew Lunn <andrew@lunn.ch>
Cc: Sebastian Hesselbarth <sebastian.hesselbarth@googlemail.com>
Cc: Gregory CLEMENT <gregory.clement@free-electrons.com>
Cc: Russell King - ARM Linux <linux@arm.linux.org.uk>
Link: http://lkml.kernel.org/r/1393911160-7688-1-git-send-email-jason@lakedaemon.net
Signed-off-by: Thomas Gleixner <tglx@linutronix.de>
2014-03-04 11:10:17 +01:00
Neil Zhang 13dde81828 irqchip: mmp: avoid use head file in a specific arch
For example, arm64 doesn't have mach/irq.h.

Signed-off-by: Neil Zhang <zhangwm@marvell.com>
Acked-by: Haojian Zhuang <haojian.zhuang@gmail.com>
Acked-by: Thomas Gleixner <tglx@linutronix.de>
Signed-off-by: Haojian Zhuang <haojian.zhuang@gmail.com>
2014-03-04 08:56:47 +08:00
Alexander Shiyan afc98d9088 ARM: clps711x: Add CLPS711X irqchip driver
This adds the irqchip driver for Cirrus Logic CLPS711X series SoCs.

Signed-off-by: Alexander Shiyan <shc_work@mail.ru>
Signed-off-by: Arnd Bergmann <arnd@arndb.de>
2014-02-28 17:27:30 +01:00
James Hogan f229006ec6 irq-metag*: stop set_affinity vectoring to offline cpus
Fix irq_set_affinity callbacks in the Meta IRQ chip drivers to AND
cpu_online_mask into the cpumask when picking a CPU to vector the
interrupt to.

As Thomas pointed out, the /proc/irq/$N/smp_affinity interface doesn't
filter out offline CPUs, so without this patch if you offline CPU0 and
set an IRQ affinity to 0x3 it vectors the interrupt onto CPU0 even
though it is offline.

Reported-by: Thomas Gleixner <tglx@linutronix.de>
Signed-off-by: James Hogan <james.hogan@imgtec.com>
Cc: Thomas Gleixner <tglx@linutronix.de>
Cc: linux-metag@vger.kernel.org
Cc: stable@vger.kernel.org
2014-02-25 22:35:06 +00:00
Will Deacon 8adbf57fc4 irqchip: gic: use dmb ishst instead of dsb when raising a softirq
When sending an SGI to another CPU, we require a barrier to ensure that
any pending stores to normal memory are made visible to the recipient
before the interrupt arrives.

Rather than use a vanilla dsb() (which will soon cause an assembly error
on arm64) before the writel_relaxed, we can instead use dsb(ishst),
since we just need to ensure that any pending normal writes are visible
within the inner-shareable domain before we poke the GIC.

With this observation, we can then further weaken the barrier to a
dmb(ishst), since other CPUs in the inner-shareable domain must observe
the write to the distributor before the SGI is generated.

Cc: Thomas Gleixner <tglx@linutronix.de>
Acked-by: Marc Zyngier <marc.zyngier@arm.com>
Acked-by: Catalin Marinas <catalin.marinas@arm.com>
Signed-off-by: Will Deacon <will.deacon@arm.com>
Signed-off-by: Arnd Bergmann <arnd@arndb.de>
2014-02-25 19:36:03 +01:00
Arnd Bergmann a3f4fdf219 irqchip: VIC: export vic_init_cascaded
vic_init_cascaded is called by integrator impd1 code that can
be a loadable module, so the function has to be exported.

Signed-off-by: Arnd Bergmann <arnd@arndb.de>
Acked-by: Linus Walleij <linus.walleij@linaro.org>
2014-02-25 18:01:43 +01:00
Arnd Bergmann 96f9d40db8 irqchip mvebu fixes for v3.14
- orion:
     - fixes for clearing bridge cause register, and clearing stale interrupts
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Merge tag 'irqchip-mvebu-fixes-3.14' of git://git.infradead.org/linux-mvebu into next/drivers

irqchip mvebu fixes for v3.14

 - orion:
    - fixes for clearing bridge cause register, and clearing stale interrupts

* tag 'irqchip-mvebu-fixes-3.14' of git://git.infradead.org/linux-mvebu:
  irqchip: orion: Fix getting generic chip pointer.
  irqchip: orion: clear stale interrupts in irq_startup
  irqchip: orion: use handle_edge_irq on bridge irqs
  irqchip: orion: clear bridge cause register on init

This is a dependency for the mvebu watchdog changes.

Signed-off-by: Arnd Bergmann <arnd@arndb.de>
2014-02-25 17:49:35 +01:00
Thomas Gleixner d0e3a9719f irqchip mvebu changes for v3.15
- armada-370-xp
     - add MSI helper
     - MPIC chained handler
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Merge tag 'irqchip-mvebu-3.15' of git://git.infradead.org/linux-mvebu into irq/core

irqchip mvebu changes for v3.15

 - armada-370-xp
    - add MSI helper
    - MPIC chained handler

Signed-off-by: Thomas Gleixner <tglx@linutronix.de>
2014-02-22 10:57:06 +01:00
Ezequiel Garcia bc69b8adfe irqchip: armada-370-xp: Setup a chained handler for the MPIC
The new Armada 375 and Armada 38x Marvell SoCs are based on Cortex-A9
CPU cores and use the ARM GIC as their main interrupt controller.
However, for various purposes (wake-up from suspend, MSI interrupts),
they have kept a separate MPIC interrupt controller, acting as a slave
to the GIC. This MPIC was already used as the primary controller on
previous Marvell SoCs, so this commit extends the existing driver to
allow the MPIC to be used as a GIC slave.

Reviewed-by: Gregory CLEMENT <gregory.clement@free-electrons.com>
Signed-off-by: Ezequiel Garcia <ezequiel.garcia@free-electrons.com>
Signed-off-by: Jason Cooper <jason@lakedaemon.net>
2014-02-22 06:12:29 +00:00
Ezequiel Garcia 9b8cf779f9 irqchip: armada-370-xp: Add helper for the MSI IRQ handling
Introduce a helper function to handle the MSI interrupts. This makes
the code more readable. In addition, this will allow to introduce a
chained IRQ handler mechanism, which is needed in situations where the
MPIC is used as a slave to another interrupt controller.

Reviewed-by: Gregory CLEMENT <gregory.clement@free-electrons.com>
Signed-off-by: Ezequiel Garcia <ezequiel.garcia@free-electrons.com>
Signed-off-by: Jason Cooper <jason@lakedaemon.net>
2014-02-22 06:12:13 +00:00
Jason Cooper 3efca1d156 mvebu irqchip fixes for v3.13
- armada-370-xp
     - fix races is MSI and IPI
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Merge tag 'tags/mvebu-irqchip-fixes-3.13' into mvebu/irqchip

mvebu irqchip fixes for v3.13

 - armada-370-xp
    - fix races is MSI and IPI
2014-02-22 06:11:45 +00:00
Thomas Gleixner ec79b577f0 irqchip mvebu fixes for v3.14
- orion:
     - fixes for clearing bridge cause register, and clearing stale interrupts
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Merge tag 'irqchip-mvebu-fixes-3.14' of git://git.infradead.org/linux-mvebu into irq/urgent

irqchip mvebu fixes for v3.14

 - orion:
    - fixes for clearing bridge cause register, and clearing stale interrupts

Signed-off-by: Thomas Gleixner <tglx@linutronix.de>
2014-02-21 23:57:33 +01:00
Andrew Lunn d86e9af633 irqchip: orion: Fix getting generic chip pointer.
Enabling SPARSE_IRQ shows up a bug in the irq-orion bridge interrupt
handler. The bridge interrupt is implemented using a single generic
chip. Thus the parameter passed to irq_get_domain_generic_chip()
should always be zero.

Signed-off-by: Andrew Lunn <andrew@lunn.ch>
Acked-by: Sebastian Hesselbarth <sebastian.hesselbarth@gmail.com>
Fixes: 9dbd90f17e ("irqchip: Add support for Marvell Orion SoCs")
Cc: <stable@vger.kernel.org> # v3.11+
Signed-off-by: Jason Cooper <jason@lakedaemon.net>
2014-02-21 21:46:56 +00:00
Thomas Gleixner ddf2965d77 mvebu irqchip changes for v3.14
- add Dove PMU interrupt controller
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Merge tag 'mvebu-irqchip-3.14' of git://git.infradead.org/linux-mvebu into irq/core

mvebu irqchip changes for v3.14

 - add Dove PMU interrupt controller

Duh. I completely forgot about that one...

Signed-off-by: Thomas Gleixner <tglx@linutronix.de>
2014-02-18 21:27:56 +01:00
Pankaj Dubey a83784859c irqchip: exynos-combiner: call handle_bad_irq directly
This patch is inspired from following commit aec00956
(irqchip: gic: Call handle_bad_irq() directly)

Also this will help in removing unwanted inclusion
of header file "asm/mach/irq.h"

Signed-off-by: Pankaj Dubey <pankaj.dubey@samsung.com>
Reviewed-by: Tomasz Figa <t.figa@samsung.com>
Signed-off-by: Kukjin Kim <kgene.kim@samsung.com>
2014-02-14 07:27:40 +09:00
Linus Walleij e641b987c2 irqchip: support cascaded VICs
This adds support for a VIC to be cascaded off another IRQ.
On the Integrator/AP logical module IM-PD1 there is a VIC
cascaded off the central FPGA IRQ controller so this is
needed for that to work out.

In order for the plug-in board to be able to register all
the devices with their IRQs relative to the offset of the
base obtained for the cascaded VIC, the base IRQ number
is passed back to the caller.

Cc: Thomas Gleixner <tglx@linutronix.de>
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
2014-02-13 11:21:21 +01:00
Linus Walleij 3b4df9dbd9 irqchip: vic: update the base IRQ member correctly
When passing 0 as the irq base the VIC driver will dynamically
allocate a number of consecutive interrupt descriptors at some
available number range. Make sure this number is recorded in
the state container rather than the passed-in zero argument
in this case.

Cc: Thomas Gleixner <tglx@linutronix.de>
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
2014-02-13 11:21:13 +01:00
Sebastian Hesselbarth e0318ec3bf irqchip: orion: clear stale interrupts in irq_startup
Bridge IRQ_CAUSE bits are asserted regardless of the corresponding bit in
IRQ_MASK register. To avoid interrupt events on stale irqs, we have to clear
them before unmask. This installs an .irq_startup callback to ensure stale
irqs are cleared before initial unmask.

Signed-off-by: Sebastian Hesselbarth <sebastian.hesselbarth@gmail.com>
Tested-by: Ezequiel Garcia <ezequiel.garcia@free-electrons.com>
Cc: <stable@vger.kernel.org>: f56c0738b5c2: "irqchip: orion: clear bridge cause register on init"
Cc: <stable@vger.kernel.org>: 38bd80b84fca: "irqchip: orion: use handle_edge_irq on bridge irqs"
Cc: <stable@vger.kernel.org> # v3.10+
Signed-off-by: Jason Cooper <jason@lakedaemon.net>
2014-02-06 18:03:32 +00:00
Sebastian Hesselbarth 5f40067fc8 irqchip: orion: use handle_edge_irq on bridge irqs
Bridge irqs are edge-triggered, i.e. they get asserted on low-to-high
transitions and not on the level of the downstream interrupt line.
This replaces handle_level_irq by the more appropriate handle_edge_irq.

Signed-off-by: Sebastian Hesselbarth <sebastian.hesselbarth@gmail.com>
Tested-by: Ezequiel Garcia <ezequiel.garcia@free-electrons.com>
Cc: <stable@vger.kernel.org>: f56c0738b5c2: "irqchip: orion: clear bridge cause register on init"
Cc: <stable@vger.kernel.org> # v3.10+
Signed-off-by: Jason Cooper <jason@lakedaemon.net>
2014-02-06 18:03:22 +00:00
Sebastian Hesselbarth 7b119fd1bd irqchip: orion: clear bridge cause register on init
It is good practice to mask and clear pending irqs on init. We already
mask all irqs, so also clear the bridge irq cause register.

Signed-off-by: Sebastian Hesselbarth <sebastian.hesselbarth@gmail.com>
Tested-by: Ezequiel Garcia <ezequiel.garcia@free-electrons.com>
Cc: <stable@vger.kernel.org> # v3.10+
Signed-off-by: Jason Cooper <jason@lakedaemon.net>
2014-02-06 18:03:08 +00:00
Linus Torvalds ef42c58a5b Merge branch 'irq-core-for-linus' of git://git.kernel.org/pub/scm/linux/kernel/git/tip/tip
Pull irq updates from Thomas Gleixner:
 "This lot provides:

   * Bugfixes for armada irq controller
   * Updates to renesas irq chip
   * Support for the TI-NSPIRE irq controller

  Not strictly a bug fix only pull request, but important updates for
  some of the arm Socs which I completely forgot to send last week.

  Seems like my obliviousness is getting worse, I just can't remember
  when it started"

* 'irq-core-for-linus' of git://git.kernel.org/pub/scm/linux/kernel/git/tip/tip:
  irqchip: Add support for TI-NSPIRE irqchip
  irqchip: renesas-irqc: Enable mask on suspend
  irqchip: renesas-irqc: Use lazy disable
  irqchip: armada-370-xp: fix MSI race condition
  irqchip: armada-370-xp: fix IPI race condition
2014-02-05 16:02:53 -08:00
Sricharan R 96ca848ef7 DRIVERS: IRQCHIP: CROSSBAR: Add support for Crossbar IP
Some socs have a large number of interrupts requests to service
the needs of its many peripherals and subsystems. All of the
interrupt lines from the subsystems are not needed at the same
time, so they have to be muxed to the irq-controller appropriately.
In such places a interrupt controllers are preceded by an CROSSBAR
that provides flexibility in muxing the device requests to the controller
inputs.

This driver takes care a allocating a free irq and then configuring the
crossbar IP as a part of the mpu's irqchip callbacks. crossbar_init should
be called right before the irqchip_init, so that it is setup to handle the
irqchip callbacks.

Cc: Thomas Gleixner <tglx@linutronix.de>
Cc: Linus Walleij <linus.walleij@linaro.org>
Cc: Santosh Shilimkar <santosh.shilimkar@ti.com>
Cc: Russell King <linux@arm.linux.org.uk>
Cc: Tony Lindgren <tony@atomide.com>
Cc: Rajendra Nayak <rnayak@ti.com>
Cc: Marc Zyngier <marc.zyngier@arm.com>
Cc: Grant Likely <grant.likely@linaro.org>
Cc: Rob Herring <rob.herring@calxeda.com>
Signed-off-by: Sricharan R <r.sricharan@ti.com>
Acked-by: Kumar Gala <galak@codeaurora.org> (for DT binding portion)
Acked-by: Santosh Shilimkar <santosh.shilimkar@ti.com>
Acked-by: Linus Walleij <linus.walleij@linaro.org>
Acked-by: Thomas Gleixner <tglx@linutronix.de>
2014-02-05 20:08:34 +05:30
Sricharan R 006e983bbc DRIVERS: IRQCHIP: IRQ-GIC: Add support for routable irqs
In some socs the gic can be preceded by a crossbar IP which
routes the peripheral interrupts to the gic inputs. The peripheral
interrupts are associated with a fixed crossbar input line and the
crossbar routes that to one of the free gic input line.

The DT entries for peripherals provides the fixed crossbar input line
as its interrupt number and the mapping code should associate this with
a free gic input line. This patch adds the support inside the gic irqchip
to handle such routable irqs. The routable irqs are registered in a linear
domain. The registered routable domain's callback should be implemented
to get a free irq and to configure the IP to route it.

Cc: Thomas Gleixner <tglx@linutronix.de>
Cc: Linus Walleij <linus.walleij@linaro.org>
Cc: Santosh Shilimkar <santosh.shilimkar@ti.com>
Cc: Russell King <linux@arm.linux.org.uk>
Cc: Tony Lindgren <tony@atomide.com>
Cc: Rajendra Nayak <rnayak@ti.com>
Cc: Marc Zyngier <marc.zyngier@arm.com>
Cc: Grant Likely <grant.likely@linaro.org>
Cc: Rob Herring <rob.herring@calxeda.com>
Signed-off-by: Sricharan R <r.sricharan@ti.com>
Reviewed-by: Thomas Gleixner <tglx@linutronix.de>
Acked-by: Santosh Shilimkar <santosh.shilimkar@ti.com>
Acked-by: Linus Walleij <linus.walleij@linaro.org>
2014-02-05 20:08:00 +05:30
Olof Johansson 167eeb4700 mvebu fixes for v3.13 (incremental #2)
- allow building and booting DT and non-DT plat-orion SoCs
  - catch proper return value for kirkwood_pm_init()
  - properly check return of of_iomap to solve boot hangs (mirabox, others)
  - remove a compile warning on Armada 370 with non-SMP.
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Merge tag 'mvebu-fixes-3.13-2' of git://git.infradead.org/linux-mvebu into fixes

mvebu fixes for v3.13 (incremental #2)

 - allow building and booting DT and non-DT plat-orion SoCs
 - catch proper return value for kirkwood_pm_init()
 - properly check return of of_iomap to solve boot hangs (mirabox, others)
 - remove a compile warning on Armada 370 with non-SMP.

* tag 'mvebu-fixes-3.13-2' of git://git.infradead.org/linux-mvebu:
  ARM: mvebu: fix compilation warning on Armada 370 (i.e. non-SMP)
  ARM: mvebu: Fix kernel hang in mvebu_soc_id_init() when of_iomap failed
  ARM: kirkwood: kirkwood_pm_init() should return void
  ARM: orion: provide C-style interrupt handler for MULTI_IRQ_HANDLER

Signed-off-by: Olof Johansson <olof@lixom.net>
2014-01-31 14:59:28 -08:00
Linus Torvalds 9b83d851a2 Xtensa patchset for 3.14-rc1
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Merge tag 'xtensa-next-20140123' of git://github.com/czankel/xtensa-linux

Pull Xtensa patches from Chris Zankel:
 "The major changes are adding support for SMP for Xtensa, fixing and
  cleaning up the ISS (simulator) network driver, and better support for
  device trees"

* tag 'xtensa-next-20140123' of git://github.com/czankel/xtensa-linux: (40 commits)
  xtensa: implement ndelay
  xtensa: clean up udelay
  xtensa: enable HAVE_PERF_EVENTS
  xtensa: remap io area defined in device tree
  xtensa: support default device tree buses
  xtensa: initialize device tree clock sources
  xtensa: xtfpga: fix definitions of platform devices
  xtensa: standardize devicetree cpu compatible strings
  xtensa: avoid duplicate of IO range definitions
  xtensa: fix ATOMCTL register documentation
  xtensa: Enable irqs after cpu is set online
  xtensa: ISS: raise network polling rate to 10 times/sec
  xtensa: remove unused XTENSA_ISS_NETWORK Kconfig parameter
  xtensa: ISS: avoid simple_strtoul usage
  xtensa: Switch to sched_clock_register()
  xtensa: implement CPU hotplug
  xtensa: add SMP support
  xtensa: add MX irqchip
  xtensa: clear timer IRQ unconditionally in its handler
  xtensa: clean up do_interrupt/do_IRQ
  ...
2014-01-25 10:49:30 -08:00
Linus Torvalds 0ba3307a8e ARM: driver updates for 3.14
Updates of SoC-near drivers and other driver updates that makes more sense to
 take through our tree.
 
 The largest part of this is a conversion of device registration for some
 renesas shmobile/sh devices over to use resources. This has required
 coordination with the corresponding arch/sh changes, and we've agreed
 to merge the arch/sh changes through our tree.
 
 Added in this branch is support for Trusted Foundations secure firmware,
 which is what is used on many of the commercial Nvidia Tegra products
 that are in the market, including the Nvidia Shield. The code is local
 to arch/arm at this time since it's uncertain whether it will be shared
 with arm64 longer-term, if needed we will refactor later.
 
 A couple of new RTC drivers used on ARM boards, merged through our tree
 on request by the RTC maintainer.
 
 ... plus a bunch of smaller updates across the board, gpio conversions
 for davinci, etc.
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Merge tag 'drivers-for-linus' of git://git.kernel.org/pub/scm/linux/kernel/git/arm/arm-soc

Pull ARM driver updates from Olof Johansson:
 "Updates of SoC-near drivers and other driver updates that makes more
  sense to take through our tree.

  The largest part of this is a conversion of device registration for
  some renesas shmobile/sh devices over to use resources.  This has
  required coordination with the corresponding arch/sh changes, and
  we've agreed to merge the arch/sh changes through our tree.

  Added in this branch is support for Trusted Foundations secure
  firmware, which is what is used on many of the commercial Nvidia Tegra
  products that are in the market, including the Nvidia Shield.  The
  code is local to arch/arm at this time since it's uncertain whether it
  will be shared with arm64 longer-term, if needed we will refactor
  later.

  A couple of new RTC drivers used on ARM boards, merged through our
  tree on request by the RTC maintainer.

  ... plus a bunch of smaller updates across the board, gpio conversions
  for davinci, etc"

* tag 'drivers-for-linus' of git://git.kernel.org/pub/scm/linux/kernel/git/arm/arm-soc: (45 commits)
  watchdog: davinci: rename platform driver to davinci-wdt
  tty: serial: Limit msm_serial_hs driver to platforms that use it
  mmc: msm_sdcc: Limit driver to platforms that use it
  usb: phy: msm: Move mach dependent code to platform data
  clk: versatile: fixup IM-PD1 clock implementation
  clk: versatile: pass a name to ICST clock provider
  ARM: integrator: pass parent IRQ to the SIC
  irqchip: versatile FPGA: support cascaded interrupts from DT
  gpio: davinci: don't create irq_domain in case of unbanked irqs
  gpio: davinci: use chained_irq_enter/chained_irq_exit API
  gpio: davinci: add OF support
  gpio: davinci: remove unused variable intc_irq_num
  gpio: davinci: convert to use irqdomain support.
  gpio: introduce GPIO_DAVINCI kconfig option
  gpio: davinci: get rid of DAVINCI_N_GPIO
  gpio: davinci: use {readl|writel}_relaxed() instead of __raw_*
  serial: sh-sci: Add OF support
  serial: sh-sci: Add device tree bindings documentation
  serial: sh-sci: Remove platform data mapbase and irqs fields
  serial: sh-sci: Remove platform data scbrr_algo_id field
  ...
2014-01-23 18:49:36 -08:00
Linus Torvalds dfd10e7ae6 ARM: SoC platform changes for 3.14
New core SoC-specific changes.
 
 New platforms:
 * Introduction of a vendor, Hisilicon, and one of their SoCs with some
   random numerical product name.
 * Introduction of EFM32, embedded platform from Silicon Labs (ARMv7m, i.e. !MMU).
 * Marvell Berlin series of SoCs, which include the one in Chromecast.
 * MOXA platform support, ARM9-based platform used mostly in industrial products
 * Support for Freescale's i.MX50 SoC.
 
 Other work:
 * Renesas work for new platforms and drivers, and conversion over to
   more multiplatform-friendly device registration schemes.
 * SMP support for Allwinner sunxi platforms.
 * ... plus a bunch of other stuff across various platforms.
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Merge tag 'soc-for-linus' of git://git.kernel.org/pub/scm/linux/kernel/git/arm/arm-soc

Pull ARM SoC platform changes from Olof Johansson:
 "New core SoC-specific changes.

  New platforms:
   * Introduction of a vendor, Hisilicon, and one of their SoCs with
     some random numerical product name.
   * Introduction of EFM32, embedded platform from Silicon Labs (ARMv7m,
     i.e. !MMU).
   * Marvell Berlin series of SoCs, which include the one in Chromecast.
   * MOXA platform support, ARM9-based platform used mostly in
     industrial products
   * Support for Freescale's i.MX50 SoC.

  Other work:
   * Renesas work for new platforms and drivers, and conversion over to
     more multiplatform-friendly device registration schemes.
   * SMP support for Allwinner sunxi platforms.
   * ... plus a bunch of other stuff across various platforms"

* tag 'soc-for-linus' of git://git.kernel.org/pub/scm/linux/kernel/git/arm/arm-soc: (201 commits)
  ARM: tegra: fix tegra_powergate_sequence_power_up() inline
  ARM: msm_defconfig: Update for multi-platform
  ARM: msm: Move MSM's DT based hardware to multi-platform support
  ARM: msm: Only build timer.c if required
  ARM: msm: Only build clock.c on proc_comm based platforms
  ARM: ux500: Enable system suspend with WFI support
  ARM: ux500: turn on PRINTK_TIME in u8500_defconfig
  ARM: shmobile: r8a7790: Fix I2C controller names
  ARM: msm: Simplify ARCH_MSM_DT config
  ARM: msm: Add support for MSM8974 SoC
  ARM: sunxi: select ARM_PSCI
  MAINTAINERS: Update Allwinner sunXi maintainer files
  ARM: sunxi: Select RESET_CONTROLLER
  ARM: imx: improve the comment of CCM lpm SW workaround
  ARM: imx: improve status check of clock gate
  ARM: imx: add necessary interface for pfd
  ARM: imx_v6_v7_defconfig: Select CONFIG_REGULATOR_PFUZE100
  ARM: imx_v6_v7_defconfig: Select MX35 and MX50 device tree support
  ARM: imx: Add cpu frequency scaling support
  ARM i.MX35: Add devicetree support.
  ...
2014-01-23 18:40:49 -08:00