4f4f85fa0b
The memory controller clock runs either at half or the same frequency as the EMC clock. Reviewed-By: Tomeu Vizoso <tomeu.vizoso@collabora.com> Acked-by: Mike Turquette <mturquette@linaro.org> Signed-off-by: Thierry Reding <treding@nvidia.com> |
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.. | ||
clk-audio-sync.c | ||
clk-divider.c | ||
clk-id.h | ||
clk-periph-gate.c | ||
clk-periph.c | ||
clk-pll-out.c | ||
clk-pll.c | ||
clk-super.c | ||
clk-tegra20.c | ||
clk-tegra30.c | ||
clk-tegra114.c | ||
clk-tegra124.c | ||
clk-tegra-audio.c | ||
clk-tegra-fixed.c | ||
clk-tegra-periph.c | ||
clk-tegra-pmc.c | ||
clk-tegra-super-gen4.c | ||
clk.c | ||
clk.h | ||
Makefile |