148675a7b2
The bank offset was being incorrectly calculated on ICH9 parts with a bank size of 8K (instead of the more common 4K bank) which would cause any NVM writes to be done on the wrong address after switching from bank 1 to bank 0. Additionally, assume we are meant to use bank 0 if a valid bank is not detected, and remove the unnecessary acquisition of the SW/FW/HW semaphore when writing to the shadow ram version of the NVM image. Signed-off-by: Bruce Allan <bruce.w.allan@intel.com> Signed-off-by: Jeff Kirsher <jeffrey.t.kirsher@intel.com> Signed-off-by: David S. Miller <davem@davemloft.net> |
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| .. | ||
| 82571.c | ||
| Makefile | ||
| defines.h | ||
| e1000.h | ||
| es2lan.c | ||
| ethtool.c | ||
| hw.h | ||
| ich8lan.c | ||
| lib.c | ||
| netdev.c | ||
| param.c | ||
| phy.c | ||