5e505bb9e7
From Stephen Warren: ARM: tegra: core SoC code enhancements Various small clock initialization table and driver changes to support WiFi modules, SPI controllers, and host1x (graphics/display hardware). Various AHB/APB-related clocks were added to the Tegra30 clock driver. The level 2 cache initialization is now driven by data from device tree, and the cache configuration tweaked. AUXDATA is added to support SPI controllers and host1x. Code to decode Tegra's "speedo" process identification fuses is added. This pull request is based on tegra-for-3.8-cleanup. * tag 'tegra-for-3.8-soc' of git://git.kernel.org/pub/scm/linux/kernel/git/swarren/linux-tegra: (26 commits) ARM: tegra: Add Tegra30 host1x clock support ARM: tegra: Add AUXDATA for Tegra30 host1x ARM: tegra: Add Tegra20 host1x clock support ARM: tegra: Add AUXDATA for Tegra20 host1x ARM: tegra: Tegra30 speedo-based process identification ARM: tegra: Add speedo-based process identification ARM: tegra: flexible spare fuse read function ARM: tegra: Implement 6395/1 for Tegra ARM: tegra: Add OF_DEV_AUXDATA for sflash driver in board dt ARM: tegra: enable data prefetch on L2 ARM: tegra: Add OF_DEV_AUXDATA for SLINK driver in board dt ARM: tegra: common: using OF api for L2 cache init ARM: tegra: dt: add L2 cache controller ARM: tegra30: clocks: add AHB and APB clocks ARM: tegra: set up wlan clocks for tegra dt ARM: tegra: move irammap.h to mach-tegra ARM: tegra: move iomap.h to mach-tegra ARM: tegra: remove <mach/dma.h> ARM: tegra: move tegra-ahb.h out of arch/arm/mach-tegra/ ARM: tegra: remove unnecessary includes of <mach/*.h> ... |
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| .. | ||
| aoa | ||
| arm | ||
| atmel | ||
| core | ||
| drivers | ||
| firewire | ||
| i2c | ||
| isa | ||
| mips | ||
| oss | ||
| parisc | ||
| pci | ||
| pcmcia | ||
| ppc | ||
| sh | ||
| soc | ||
| sparc | ||
| spi | ||
| synth | ||
| usb | ||
| Kconfig | ||
| Makefile | ||
| ac97_bus.c | ||
| last.c | ||
| sound_core.c | ||
| sound_firmware.c | ||