2016-01-29 23:50:40 +01:00
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/*
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* bcm2708 aka bcm2835/2836 aka Raspberry Pi/Pi2 SoC platform defines
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*
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* These definitions are derived from those in Raspbian Linux at
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* arch/arm/mach-{bcm2708,bcm2709}/include/mach/platform.h
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* where they carry the following notice:
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*
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* Copyright (C) 2010 Broadcom
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License as published by
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* the Free Software Foundation; either version 2 of the License, or
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* (at your option) any later version.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*
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* You should have received a copy of the GNU General Public License
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* along with this program; if not, write to the Free Software
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* Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
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*/
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2019-06-04 20:16:18 +02:00
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#ifndef HW_ARM_RASPI_PLATFORM_H
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#define HW_ARM_RASPI_PLATFORM_H
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2016-01-29 23:50:40 +01:00
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#define MCORE_OFFSET 0x0000 /* Fake frame buffer device
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* (the multicore sync block) */
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#define IC0_OFFSET 0x2000
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#define ST_OFFSET 0x3000 /* System Timer */
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#define MPHI_OFFSET 0x6000 /* Message-based Parallel Host Intf. */
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#define DMA_OFFSET 0x7000 /* DMA controller, channels 0-14 */
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#define ARM_OFFSET 0xB000 /* BCM2708 ARM control block */
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#define ARMCTRL_OFFSET (ARM_OFFSET + 0x000)
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#define ARMCTRL_IC_OFFSET (ARM_OFFSET + 0x200) /* Interrupt controller */
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#define ARMCTRL_TIMER0_1_OFFSET (ARM_OFFSET + 0x400) /* Timer 0 and 1 */
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#define ARMCTRL_0_SBM_OFFSET (ARM_OFFSET + 0x800) /* User 0 (ARM) Semaphores
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* Doorbells & Mailboxes */
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#define PM_OFFSET 0x100000 /* Power Management, Reset controller
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* and Watchdog registers */
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#define PCM_CLOCK_OFFSET 0x101098
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#define RNG_OFFSET 0x104000
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#define GPIO_OFFSET 0x200000
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#define UART0_OFFSET 0x201000
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#define MMCI0_OFFSET 0x202000
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#define I2S_OFFSET 0x203000
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#define SPI0_OFFSET 0x204000
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#define BSC0_OFFSET 0x205000 /* BSC0 I2C/TWI */
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#define UART1_OFFSET 0x215000
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#define EMMC_OFFSET 0x300000
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#define SMI_OFFSET 0x600000
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#define BSC1_OFFSET 0x804000 /* BSC1 I2C/TWI */
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#define USB_OFFSET 0x980000 /* DTC_OTG USB controller */
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#define DMA15_OFFSET 0xE05000 /* DMA controller, channel 15 */
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/* GPU interrupts */
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#define INTERRUPT_TIMER0 0
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#define INTERRUPT_TIMER1 1
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#define INTERRUPT_TIMER2 2
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#define INTERRUPT_TIMER3 3
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#define INTERRUPT_CODEC0 4
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#define INTERRUPT_CODEC1 5
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#define INTERRUPT_CODEC2 6
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#define INTERRUPT_JPEG 7
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#define INTERRUPT_ISP 8
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#define INTERRUPT_USB 9
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#define INTERRUPT_3D 10
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#define INTERRUPT_TRANSPOSER 11
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#define INTERRUPT_MULTICORESYNC0 12
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#define INTERRUPT_MULTICORESYNC1 13
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#define INTERRUPT_MULTICORESYNC2 14
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#define INTERRUPT_MULTICORESYNC3 15
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#define INTERRUPT_DMA0 16
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#define INTERRUPT_DMA1 17
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#define INTERRUPT_DMA2 18
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#define INTERRUPT_DMA3 19
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#define INTERRUPT_DMA4 20
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#define INTERRUPT_DMA5 21
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#define INTERRUPT_DMA6 22
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#define INTERRUPT_DMA7 23
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#define INTERRUPT_DMA8 24
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#define INTERRUPT_DMA9 25
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#define INTERRUPT_DMA10 26
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#define INTERRUPT_DMA11 27
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#define INTERRUPT_DMA12 28
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#define INTERRUPT_AUX 29
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#define INTERRUPT_ARM 30
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#define INTERRUPT_VPUDMA 31
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#define INTERRUPT_HOSTPORT 32
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#define INTERRUPT_VIDEOSCALER 33
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#define INTERRUPT_CCP2TX 34
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#define INTERRUPT_SDC 35
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#define INTERRUPT_DSI0 36
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#define INTERRUPT_AVE 37
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#define INTERRUPT_CAM0 38
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#define INTERRUPT_CAM1 39
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#define INTERRUPT_HDMI0 40
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#define INTERRUPT_HDMI1 41
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#define INTERRUPT_PIXELVALVE1 42
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#define INTERRUPT_I2CSPISLV 43
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#define INTERRUPT_DSI1 44
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#define INTERRUPT_PWA0 45
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#define INTERRUPT_PWA1 46
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#define INTERRUPT_CPR 47
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#define INTERRUPT_SMI 48
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#define INTERRUPT_GPIO0 49
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#define INTERRUPT_GPIO1 50
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#define INTERRUPT_GPIO2 51
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#define INTERRUPT_GPIO3 52
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#define INTERRUPT_I2C 53
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#define INTERRUPT_SPI 54
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#define INTERRUPT_I2SPCM 55
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#define INTERRUPT_SDIO 56
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#define INTERRUPT_UART 57
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#define INTERRUPT_SLIMBUS 58
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#define INTERRUPT_VEC 59
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#define INTERRUPT_CPG 60
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#define INTERRUPT_RNG 61
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#define INTERRUPT_ARASANSDIO 62
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#define INTERRUPT_AVSPMON 63
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/* ARM CPU IRQs use a private number space */
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#define INTERRUPT_ARM_TIMER 0
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#define INTERRUPT_ARM_MAILBOX 1
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#define INTERRUPT_ARM_DOORBELL_0 2
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#define INTERRUPT_ARM_DOORBELL_1 3
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#define INTERRUPT_VPU0_HALTED 4
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#define INTERRUPT_VPU1_HALTED 5
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#define INTERRUPT_ILLEGAL_TYPE0 6
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#define INTERRUPT_ILLEGAL_TYPE1 7
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2019-06-04 20:16:18 +02:00
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#endif
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