2019-06-19 22:10:41 +02:00
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# -*- Mode: Python -*-
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2020-07-29 20:50:24 +02:00
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# vim: filetype=python
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2019-06-19 22:10:41 +02:00
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#
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# This work is licensed under the terms of the GNU GPL, version 2 or later.
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# See the COPYING file in the top-level directory.
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##
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# = Machines
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##
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2020-10-20 12:47:58 +02:00
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{ 'include': 'common.json' }
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2023-10-16 20:39:06 +02:00
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{ 'include': 'machine-common.json' }
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2020-10-20 12:47:58 +02:00
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2019-07-09 17:20:53 +02:00
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##
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# @SysEmuTarget:
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#
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# The comprehensive enumeration of QEMU system emulation ("softmmu")
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2023-04-28 12:54:29 +02:00
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# targets. Run "./configure --help" in the project root directory,
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# and look for the \*-softmmu targets near the "--target-list" option.
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# The individual target constants are not documented here, for the
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# time being.
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2019-07-09 17:20:53 +02:00
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#
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2019-01-21 14:18:59 +01:00
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# @rx: since 5.0
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2023-04-28 12:54:29 +02:00
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#
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2020-01-24 01:51:21 +01:00
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# @avr: since 5.1
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2019-01-21 14:18:59 +01:00
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#
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2023-04-28 12:54:29 +02:00
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# Notes: The resulting QMP strings can be appended to the
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# "qemu-system-" prefix to produce the corresponding QEMU
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# executable name. This is true even for "qemu-system-x86_64".
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2019-07-09 17:20:53 +02:00
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#
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# Since: 3.0
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##
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{ 'enum' : 'SysEmuTarget',
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2021-05-03 10:40:33 +02:00
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'data' : [ 'aarch64', 'alpha', 'arm', 'avr', 'cris', 'hppa', 'i386',
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2022-06-06 14:43:20 +02:00
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'loongarch64', 'm68k', 'microblaze', 'microblazeel', 'mips', 'mips64',
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2021-04-30 18:03:55 +02:00
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'mips64el', 'mipsel', 'nios2', 'or1k', 'ppc',
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2019-01-21 14:18:59 +01:00
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'ppc64', 'riscv32', 'riscv64', 'rx', 's390x', 'sh4',
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2021-05-03 10:40:34 +02:00
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'sh4eb', 'sparc', 'sparc64', 'tricore',
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2019-07-09 17:20:53 +02:00
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'x86_64', 'xtensa', 'xtensaeb' ] }
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2019-06-19 22:10:41 +02:00
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##
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# @CpuS390State:
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#
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2023-04-28 12:54:29 +02:00
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# An enumeration of cpu states that can be assumed by a virtual S390
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# CPU
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2019-06-19 22:10:41 +02:00
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#
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# Since: 2.12
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##
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{ 'enum': 'CpuS390State',
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'prefix': 'S390_CPU_STATE',
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'data': [ 'uninitialized', 'stopped', 'check-stop', 'operating', 'load' ] }
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##
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# @CpuInfoS390:
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#
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# Additional information about a virtual S390 CPU
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#
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# @cpu-state: the virtual CPU's state
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#
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2023-10-16 20:39:14 +02:00
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# @dedicated: the virtual CPU's dedication (since 8.2)
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#
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# @entitlement: the virtual CPU's entitlement (since 8.2)
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#
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2019-06-19 22:10:41 +02:00
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# Since: 2.12
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##
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2023-10-16 20:39:14 +02:00
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{ 'struct': 'CpuInfoS390',
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'data': { 'cpu-state': 'CpuS390State',
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'*dedicated': 'bool',
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'*entitlement': 'CpuS390Entitlement' } }
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2019-06-19 22:10:41 +02:00
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##
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# @CpuInfoFast:
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#
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# Information about a virtual CPU
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#
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# @cpu-index: index of the virtual CPU
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#
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# @qom-path: path to the CPU object in the QOM tree
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#
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# @thread-id: ID of the underlying host thread
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#
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# @props: properties associated with a virtual CPU, e.g. the socket id
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2019-06-19 22:10:41 +02:00
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#
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# @target: the QEMU system emulation target, which determines which
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2023-04-28 12:54:29 +02:00
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# additional fields will be listed (since 3.0)
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2019-06-19 22:10:41 +02:00
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#
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# Since: 2.12
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##
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{ 'union' : 'CpuInfoFast',
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'base' : { 'cpu-index' : 'int',
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'qom-path' : 'str',
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'thread-id' : 'int',
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'*props' : 'CpuInstanceProperties',
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'target' : 'SysEmuTarget' },
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'discriminator' : 'target',
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'data' : { 's390x' : 'CpuInfoS390' } }
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##
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# @query-cpus-fast:
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#
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2021-02-22 13:54:55 +01:00
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# Returns information about all virtual CPUs.
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2019-06-19 22:10:41 +02:00
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#
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# Returns: list of @CpuInfoFast
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#
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# Since: 2.12
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#
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# Example:
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#
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# -> { "execute": "query-cpus-fast" }
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# <- { "return": [
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# {
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# "thread-id": 25627,
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# "props": {
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# "core-id": 0,
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# "thread-id": 0,
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# "socket-id": 0
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# },
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# "qom-path": "/machine/unattached/device[0]",
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# "target":"x86_64",
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# "cpu-index": 0
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# },
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# {
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# "thread-id": 25628,
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# "props": {
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# "core-id": 0,
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# "thread-id": 0,
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# "socket-id": 1
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# },
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# "qom-path": "/machine/unattached/device[2]",
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# "target":"x86_64",
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# "cpu-index": 1
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# }
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# ]
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# }
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##
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{ 'command': 'query-cpus-fast', 'returns': [ 'CpuInfoFast' ] }
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##
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# @MachineInfo:
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#
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# Information describing a machine.
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#
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# @name: the name of the machine
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#
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# @alias: an alias for the machine name
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#
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# @is-default: whether the machine is default
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#
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# @cpu-max: maximum number of CPUs supported by the machine type
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# (since 1.5)
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2019-06-19 22:10:41 +02:00
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#
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2020-11-18 07:41:58 +01:00
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# @hotpluggable-cpus: cpu hotplug via -device is supported (since 2.7)
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2019-06-19 22:10:41 +02:00
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#
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2019-06-10 15:10:07 +02:00
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# @numa-mem-supported: true if '-numa node,mem' option is supported by
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2023-04-28 12:54:29 +02:00
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# the machine type and false otherwise (since 4.1)
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2019-06-10 15:10:07 +02:00
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#
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2023-04-28 12:54:29 +02:00
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# @deprecated: if true, the machine type is deprecated and may be
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# removed in future versions of QEMU according to the QEMU
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# deprecation policy (since 4.1)
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2019-06-09 01:34:47 +02:00
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#
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2023-04-28 12:54:29 +02:00
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# @default-cpu-type: default CPU model typename if none is requested
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# via the -cpu argument. (since 4.2)
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2019-08-22 12:04:12 +02:00
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#
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2023-04-28 12:54:29 +02:00
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# @default-ram-id: the default ID of initial RAM memory backend (since
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# 5.2)
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2020-05-26 10:25:35 +02:00
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#
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2023-02-28 09:12:34 +01:00
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# @acpi: machine type supports ACPI (since 8.0)
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#
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2020-11-18 07:41:58 +01:00
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# Since: 1.2
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2019-06-19 22:10:41 +02:00
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##
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{ 'struct': 'MachineInfo',
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'data': { 'name': 'str', '*alias': 'str',
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'*is-default': 'bool', 'cpu-max': 'int',
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2019-06-09 01:34:47 +02:00
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'hotpluggable-cpus': 'bool', 'numa-mem-supported': 'bool',
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2020-05-26 10:25:35 +02:00
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'deprecated': 'bool', '*default-cpu-type': 'str',
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2023-02-28 09:12:34 +01:00
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'*default-ram-id': 'str', 'acpi': 'bool' } }
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2019-06-19 22:10:41 +02:00
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##
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# @query-machines:
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#
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# Return a list of supported machines
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#
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# Returns: a list of MachineInfo
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#
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2020-11-18 07:41:58 +01:00
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# Since: 1.2
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2019-06-19 22:10:41 +02:00
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##
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{ 'command': 'query-machines', 'returns': ['MachineInfo'] }
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##
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# @CurrentMachineParams:
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#
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# Information describing the running machine parameters.
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#
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# @wakeup-suspend-support: true if the machine supports wake up from
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# suspend
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2019-06-19 22:10:41 +02:00
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#
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# Since: 4.0
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##
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{ 'struct': 'CurrentMachineParams',
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'data': { 'wakeup-suspend-support': 'bool'} }
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##
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# @query-current-machine:
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#
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# Return information on the current virtual machine.
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#
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# Returns: CurrentMachineParams
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#
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# Since: 4.0
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##
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{ 'command': 'query-current-machine', 'returns': 'CurrentMachineParams' }
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2019-07-09 17:20:53 +02:00
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##
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# @TargetInfo:
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#
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# Information describing the QEMU target.
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#
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# @arch: the target architecture
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#
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2020-11-18 07:41:58 +01:00
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# Since: 1.2
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2019-07-09 17:20:53 +02:00
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##
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{ 'struct': 'TargetInfo',
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'data': { 'arch': 'SysEmuTarget' } }
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##
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# @query-target:
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#
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# Return information about the target for this QEMU
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#
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# Returns: TargetInfo
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#
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2020-11-18 07:41:58 +01:00
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# Since: 1.2
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2019-07-09 17:20:53 +02:00
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##
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{ 'command': 'query-target', 'returns': 'TargetInfo' }
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2020-09-13 21:53:45 +02:00
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##
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# @UuidInfo:
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#
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# Guest UUID information (Universally Unique Identifier).
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#
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# @UUID: the UUID of the guest
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#
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2020-11-18 07:41:58 +01:00
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# Since: 0.14
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2020-09-13 21:53:45 +02:00
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#
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# Notes: If no UUID was specified for the guest, a null UUID is
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# returned.
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2020-09-13 21:53:45 +02:00
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##
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{ 'struct': 'UuidInfo', 'data': {'UUID': 'str'} }
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##
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# @query-uuid:
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#
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# Query the guest UUID information.
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#
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# Returns: The @UuidInfo for the guest
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#
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2020-11-18 07:41:58 +01:00
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# Since: 0.14
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2020-09-13 21:53:45 +02:00
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#
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# Example:
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#
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# -> { "execute": "query-uuid" }
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# <- { "return": { "UUID": "550e8400-e29b-41d4-a716-446655440000" } }
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##
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{ 'command': 'query-uuid', 'returns': 'UuidInfo', 'allow-preconfig': true }
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2020-09-13 21:53:44 +02:00
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##
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# @GuidInfo:
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#
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# GUID information.
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#
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# @guid: the globally unique identifier
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#
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# Since: 2.9
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##
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{ 'struct': 'GuidInfo', 'data': {'guid': 'str'} }
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##
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# @query-vm-generation-id:
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#
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# Show Virtual Machine Generation ID
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#
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# Since: 2.9
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##
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{ 'command': 'query-vm-generation-id', 'returns': 'GuidInfo' }
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2020-10-12 14:15:33 +02:00
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##
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# @system_reset:
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#
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# Performs a hard reset of a guest.
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#
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2020-11-18 07:41:58 +01:00
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# Since: 0.14
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2020-10-12 14:15:33 +02:00
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#
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# Example:
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#
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# -> { "execute": "system_reset" }
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# <- { "return": {} }
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##
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{ 'command': 'system_reset' }
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##
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# @system_powerdown:
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#
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# Requests that a guest perform a powerdown operation.
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#
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2020-11-18 07:41:58 +01:00
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# Since: 0.14
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2020-10-12 14:15:33 +02:00
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#
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# Notes: A guest may or may not respond to this command. This command
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2023-04-28 12:54:29 +02:00
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# returning does not indicate that a guest has accepted the
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# request or that it has shut down. Many guests will respond to
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# this command by prompting the user in some way.
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2022-05-03 09:37:32 +02:00
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#
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2020-10-12 14:15:33 +02:00
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# Example:
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#
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# -> { "execute": "system_powerdown" }
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# <- { "return": {} }
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##
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{ 'command': 'system_powerdown' }
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##
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# @system_wakeup:
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#
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2023-04-28 12:54:29 +02:00
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# Wake up guest from suspend. If the guest has wake-up from suspend
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2020-10-12 14:15:33 +02:00
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# support enabled (wakeup-suspend-support flag from
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# query-current-machine), wake-up guest from suspend if the guest is
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2023-04-28 12:54:29 +02:00
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# in SUSPENDED state. Return an error otherwise.
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2020-10-12 14:15:33 +02:00
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#
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2022-05-03 09:37:35 +02:00
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# Since: 1.1
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2020-10-12 14:15:33 +02:00
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#
|
2022-05-03 09:37:35 +02:00
|
|
|
# Returns: nothing.
|
2020-10-12 14:15:33 +02:00
|
|
|
#
|
|
|
|
# Note: prior to 4.0, this command does nothing in case the guest
|
2023-04-28 12:54:29 +02:00
|
|
|
# isn't suspended.
|
2020-10-12 14:15:33 +02:00
|
|
|
#
|
|
|
|
# Example:
|
|
|
|
#
|
|
|
|
# -> { "execute": "system_wakeup" }
|
|
|
|
# <- { "return": {} }
|
|
|
|
##
|
|
|
|
{ 'command': 'system_wakeup' }
|
|
|
|
|
2020-09-13 21:53:41 +02:00
|
|
|
##
|
|
|
|
# @LostTickPolicy:
|
|
|
|
#
|
2023-04-28 12:54:29 +02:00
|
|
|
# Policy for handling lost ticks in timer devices. Ticks end up
|
|
|
|
# getting lost when, for example, the guest is paused.
|
|
|
|
#
|
|
|
|
# @discard: throw away the missed ticks and continue with future
|
|
|
|
# injection normally. The guest OS will see the timer jump ahead
|
|
|
|
# by a potentially quite significant amount all at once, as if the
|
|
|
|
# intervening chunk of time had simply not existed; needless to
|
|
|
|
# say, such a sudden jump can easily confuse a guest OS which is
|
|
|
|
# not specifically prepared to deal with it. Assuming the guest
|
|
|
|
# OS can deal correctly with the time jump, the time in the guest
|
|
|
|
# and in the host should now match.
|
|
|
|
#
|
|
|
|
# @delay: continue to deliver ticks at the normal rate. The guest OS
|
|
|
|
# will not notice anything is amiss, as from its point of view
|
|
|
|
# time will have continued to flow normally. The time in the
|
|
|
|
# guest should now be behind the time in the host by exactly the
|
|
|
|
# amount of time during which ticks have been missed.
|
|
|
|
#
|
|
|
|
# @slew: deliver ticks at a higher rate to catch up with the missed
|
|
|
|
# ticks. The guest OS will not notice anything is amiss, as from
|
|
|
|
# its point of view time will have continued to flow normally.
|
|
|
|
# Once the timer has managed to catch up with all the missing
|
|
|
|
# ticks, the time in the guest and in the host should match.
|
2020-09-13 21:53:41 +02:00
|
|
|
#
|
|
|
|
# Since: 2.0
|
|
|
|
##
|
|
|
|
{ 'enum': 'LostTickPolicy',
|
|
|
|
'data': ['discard', 'delay', 'slew' ] }
|
|
|
|
|
2020-10-12 14:15:32 +02:00
|
|
|
##
|
|
|
|
# @inject-nmi:
|
|
|
|
#
|
2023-04-28 12:54:29 +02:00
|
|
|
# Injects a Non-Maskable Interrupt into the default CPU (x86/s390) or
|
|
|
|
# all CPUs (ppc64). The command fails when the guest doesn't support
|
|
|
|
# injecting.
|
2020-10-12 14:15:32 +02:00
|
|
|
#
|
2022-05-03 09:37:35 +02:00
|
|
|
# Returns: If successful, nothing
|
2020-10-12 14:15:32 +02:00
|
|
|
#
|
2022-05-03 09:37:35 +02:00
|
|
|
# Since: 0.14
|
2020-10-12 14:15:32 +02:00
|
|
|
#
|
2023-04-28 12:54:29 +02:00
|
|
|
# Note: prior to 2.1, this command was only supported for x86 and s390
|
|
|
|
# VMs
|
2020-10-12 14:15:32 +02:00
|
|
|
#
|
|
|
|
# Example:
|
|
|
|
#
|
|
|
|
# -> { "execute": "inject-nmi" }
|
|
|
|
# <- { "return": {} }
|
|
|
|
##
|
|
|
|
{ 'command': 'inject-nmi' }
|
|
|
|
|
2020-10-12 14:15:35 +02:00
|
|
|
##
|
|
|
|
# @KvmInfo:
|
|
|
|
#
|
|
|
|
# Information about support for KVM acceleration
|
|
|
|
#
|
|
|
|
# @enabled: true if KVM acceleration is active
|
|
|
|
#
|
|
|
|
# @present: true if KVM acceleration is built into this executable
|
|
|
|
#
|
2020-11-18 07:41:58 +01:00
|
|
|
# Since: 0.14
|
2020-10-12 14:15:35 +02:00
|
|
|
##
|
|
|
|
{ 'struct': 'KvmInfo', 'data': {'enabled': 'bool', 'present': 'bool'} }
|
|
|
|
|
|
|
|
##
|
|
|
|
# @query-kvm:
|
|
|
|
#
|
|
|
|
# Returns information about KVM acceleration
|
|
|
|
#
|
|
|
|
# Returns: @KvmInfo
|
|
|
|
#
|
2020-11-18 07:41:58 +01:00
|
|
|
# Since: 0.14
|
2020-10-12 14:15:35 +02:00
|
|
|
#
|
|
|
|
# Example:
|
|
|
|
#
|
|
|
|
# -> { "execute": "query-kvm" }
|
|
|
|
# <- { "return": { "enabled": true, "present": true } }
|
|
|
|
##
|
|
|
|
{ 'command': 'query-kvm', 'returns': 'KvmInfo' }
|
|
|
|
|
2019-06-19 22:10:41 +02:00
|
|
|
##
|
|
|
|
# @NumaOptionsType:
|
|
|
|
#
|
|
|
|
# @node: NUMA nodes configuration
|
|
|
|
#
|
|
|
|
# @dist: NUMA distance configuration (since 2.10)
|
|
|
|
#
|
|
|
|
# @cpu: property based CPU(s) to node mapping (Since: 2.10)
|
|
|
|
#
|
2019-12-13 02:19:23 +01:00
|
|
|
# @hmat-lb: memory latency and bandwidth information (Since: 5.0)
|
|
|
|
#
|
2019-12-13 02:19:24 +01:00
|
|
|
# @hmat-cache: memory side cache information (Since: 5.0)
|
|
|
|
#
|
2019-06-19 22:10:41 +02:00
|
|
|
# Since: 2.1
|
|
|
|
##
|
|
|
|
{ 'enum': 'NumaOptionsType',
|
2019-12-13 02:19:24 +01:00
|
|
|
'data': [ 'node', 'dist', 'cpu', 'hmat-lb', 'hmat-cache' ] }
|
2019-06-19 22:10:41 +02:00
|
|
|
|
|
|
|
##
|
|
|
|
# @NumaOptions:
|
|
|
|
#
|
2023-04-28 12:54:29 +02:00
|
|
|
# A discriminated record of NUMA options. (for OptsVisitor)
|
2019-06-19 22:10:41 +02:00
|
|
|
#
|
|
|
|
# Since: 2.1
|
|
|
|
##
|
|
|
|
{ 'union': 'NumaOptions',
|
|
|
|
'base': { 'type': 'NumaOptionsType' },
|
|
|
|
'discriminator': 'type',
|
|
|
|
'data': {
|
|
|
|
'node': 'NumaNodeOptions',
|
|
|
|
'dist': 'NumaDistOptions',
|
2019-12-13 02:19:23 +01:00
|
|
|
'cpu': 'NumaCpuOptions',
|
2019-12-13 02:19:24 +01:00
|
|
|
'hmat-lb': 'NumaHmatLBOptions',
|
|
|
|
'hmat-cache': 'NumaHmatCacheOptions' }}
|
2019-06-19 22:10:41 +02:00
|
|
|
|
|
|
|
##
|
|
|
|
# @NumaNodeOptions:
|
|
|
|
#
|
2023-04-28 12:54:29 +02:00
|
|
|
# Create a guest NUMA node. (for OptsVisitor)
|
2019-06-19 22:10:41 +02:00
|
|
|
#
|
|
|
|
# @nodeid: NUMA node ID (increase by 1 from 0 if omitted)
|
|
|
|
#
|
2023-04-28 12:54:29 +02:00
|
|
|
# @cpus: VCPUs belonging to this node (assign VCPUS round-robin if
|
|
|
|
# omitted)
|
2019-06-19 22:10:41 +02:00
|
|
|
#
|
|
|
|
# @mem: memory size of this node; mutually exclusive with @memdev.
|
2023-04-28 12:54:29 +02:00
|
|
|
# Equally divide total memory among nodes if both @mem and @memdev
|
|
|
|
# are omitted.
|
2019-06-19 22:10:41 +02:00
|
|
|
#
|
2023-04-28 12:54:29 +02:00
|
|
|
# @memdev: memory backend object. If specified for one node, it must
|
|
|
|
# be specified for all nodes.
|
2019-06-19 22:10:41 +02:00
|
|
|
#
|
2023-04-28 12:54:29 +02:00
|
|
|
# @initiator: defined in ACPI 6.3 Chapter 5.2.27.3 Table 5-145, points
|
|
|
|
# to the nodeid which has the memory controller responsible for
|
|
|
|
# this NUMA node. This field provides additional information as
|
|
|
|
# to the initiator node that is closest (as in directly attached)
|
|
|
|
# to this node, and therefore has the best performance (since 5.0)
|
2019-12-13 02:19:22 +01:00
|
|
|
#
|
2019-06-19 22:10:41 +02:00
|
|
|
# Since: 2.1
|
|
|
|
##
|
|
|
|
{ 'struct': 'NumaNodeOptions',
|
|
|
|
'data': {
|
|
|
|
'*nodeid': 'uint16',
|
|
|
|
'*cpus': ['uint16'],
|
|
|
|
'*mem': 'size',
|
2019-12-13 02:19:22 +01:00
|
|
|
'*memdev': 'str',
|
|
|
|
'*initiator': 'uint16' }}
|
2019-06-19 22:10:41 +02:00
|
|
|
|
|
|
|
##
|
|
|
|
# @NumaDistOptions:
|
|
|
|
#
|
|
|
|
# Set the distance between 2 NUMA nodes.
|
|
|
|
#
|
|
|
|
# @src: source NUMA node.
|
|
|
|
#
|
|
|
|
# @dst: destination NUMA node.
|
|
|
|
#
|
2023-04-28 12:54:29 +02:00
|
|
|
# @val: NUMA distance from source node to destination node. When a
|
|
|
|
# node is unreachable from another node, set the distance between
|
|
|
|
# them to 255.
|
2019-06-19 22:10:41 +02:00
|
|
|
#
|
|
|
|
# Since: 2.10
|
|
|
|
##
|
|
|
|
{ 'struct': 'NumaDistOptions',
|
|
|
|
'data': {
|
|
|
|
'src': 'uint16',
|
|
|
|
'dst': 'uint16',
|
|
|
|
'val': 'uint8' }}
|
|
|
|
|
hw/cxl/host: Add support for CXL Fixed Memory Windows.
The concept of these is introduced in [1] in terms of the
description the CEDT ACPI table. The principal is more general.
Unlike once traffic hits the CXL root bridges, the host system
memory address routing is implementation defined and effectively
static once observable by standard / generic system software.
Each CXL Fixed Memory Windows (CFMW) is a region of PA space
which has fixed system dependent routing configured so that
accesses can be routed to the CXL devices below a set of target
root bridges. The accesses may be interleaved across multiple
root bridges.
For QEMU we could have fully specified these regions in terms
of a base PA + size, but as the absolute address does not matter
it is simpler to let individual platforms place the memory regions.
ExampleS:
-cxl-fixed-memory-window targets.0=cxl.0,size=128G
-cxl-fixed-memory-window targets.0=cxl.1,size=128G
-cxl-fixed-memory-window targets.0=cxl0,targets.1=cxl.1,size=256G,interleave-granularity=2k
Specifies
* 2x 128G regions not interleaved across root bridges, one for each of
the root bridges with ids cxl.0 and cxl.1
* 256G region interleaved across root bridges with ids cxl.0 and cxl.1
with a 2k interleave granularity.
When system software enumerates the devices below a given root bridge
it can then decide which CFMW to use. If non interleave is desired
(or possible) it can use the appropriate CFMW for the root bridge in
question. If there are suitable devices to interleave across the
two root bridges then it may use the 3rd CFMS.
A number of other designs were considered but the following constraints
made it hard to adapt existing QEMU approaches to this particular problem.
1) The size must be known before a specific architecture / board brings
up it's PA memory map. We need to set up an appropriate region.
2) Using links to the host bridges provides a clean command line interface
but these links cannot be established until command line devices have
been added.
Hence the two step process used here of first establishing the size,
interleave-ways and granularity + caching the ids of the host bridges
and then, once available finding the actual host bridges so they can
be used later to support interleave decoding.
[1] CXL 2.0 ECN: CEDT CFMWS & QTG DSM (computeexpresslink.org / specifications)
Signed-off-by: Jonathan Cameron <jonathan.cameron@huawei.com>
Acked-by: Markus Armbruster <armbru@redhat.com> # QAPI Schema
Message-Id: <20220429144110.25167-28-Jonathan.Cameron@huawei.com>
Reviewed-by: Michael S. Tsirkin <mst@redhat.com>
Signed-off-by: Michael S. Tsirkin <mst@redhat.com>
2022-04-29 16:40:52 +02:00
|
|
|
##
|
|
|
|
# @CXLFixedMemoryWindowOptions:
|
|
|
|
#
|
|
|
|
# Create a CXL Fixed Memory Window
|
|
|
|
#
|
2023-04-28 12:54:29 +02:00
|
|
|
# @size: Size of the Fixed Memory Window in bytes. Must be a multiple
|
|
|
|
# of 256MiB.
|
|
|
|
#
|
hw/cxl/host: Add support for CXL Fixed Memory Windows.
The concept of these is introduced in [1] in terms of the
description the CEDT ACPI table. The principal is more general.
Unlike once traffic hits the CXL root bridges, the host system
memory address routing is implementation defined and effectively
static once observable by standard / generic system software.
Each CXL Fixed Memory Windows (CFMW) is a region of PA space
which has fixed system dependent routing configured so that
accesses can be routed to the CXL devices below a set of target
root bridges. The accesses may be interleaved across multiple
root bridges.
For QEMU we could have fully specified these regions in terms
of a base PA + size, but as the absolute address does not matter
it is simpler to let individual platforms place the memory regions.
ExampleS:
-cxl-fixed-memory-window targets.0=cxl.0,size=128G
-cxl-fixed-memory-window targets.0=cxl.1,size=128G
-cxl-fixed-memory-window targets.0=cxl0,targets.1=cxl.1,size=256G,interleave-granularity=2k
Specifies
* 2x 128G regions not interleaved across root bridges, one for each of
the root bridges with ids cxl.0 and cxl.1
* 256G region interleaved across root bridges with ids cxl.0 and cxl.1
with a 2k interleave granularity.
When system software enumerates the devices below a given root bridge
it can then decide which CFMW to use. If non interleave is desired
(or possible) it can use the appropriate CFMW for the root bridge in
question. If there are suitable devices to interleave across the
two root bridges then it may use the 3rd CFMS.
A number of other designs were considered but the following constraints
made it hard to adapt existing QEMU approaches to this particular problem.
1) The size must be known before a specific architecture / board brings
up it's PA memory map. We need to set up an appropriate region.
2) Using links to the host bridges provides a clean command line interface
but these links cannot be established until command line devices have
been added.
Hence the two step process used here of first establishing the size,
interleave-ways and granularity + caching the ids of the host bridges
and then, once available finding the actual host bridges so they can
be used later to support interleave decoding.
[1] CXL 2.0 ECN: CEDT CFMWS & QTG DSM (computeexpresslink.org / specifications)
Signed-off-by: Jonathan Cameron <jonathan.cameron@huawei.com>
Acked-by: Markus Armbruster <armbru@redhat.com> # QAPI Schema
Message-Id: <20220429144110.25167-28-Jonathan.Cameron@huawei.com>
Reviewed-by: Michael S. Tsirkin <mst@redhat.com>
Signed-off-by: Michael S. Tsirkin <mst@redhat.com>
2022-04-29 16:40:52 +02:00
|
|
|
# @interleave-granularity: Number of contiguous bytes for which
|
2023-04-28 12:54:29 +02:00
|
|
|
# accesses will go to a given interleave target. Accepted values
|
|
|
|
# [256, 512, 1k, 2k, 4k, 8k, 16k]
|
|
|
|
#
|
|
|
|
# @targets: Target root bridge IDs from -device ...,id=<ID> for each
|
|
|
|
# root bridge.
|
hw/cxl/host: Add support for CXL Fixed Memory Windows.
The concept of these is introduced in [1] in terms of the
description the CEDT ACPI table. The principal is more general.
Unlike once traffic hits the CXL root bridges, the host system
memory address routing is implementation defined and effectively
static once observable by standard / generic system software.
Each CXL Fixed Memory Windows (CFMW) is a region of PA space
which has fixed system dependent routing configured so that
accesses can be routed to the CXL devices below a set of target
root bridges. The accesses may be interleaved across multiple
root bridges.
For QEMU we could have fully specified these regions in terms
of a base PA + size, but as the absolute address does not matter
it is simpler to let individual platforms place the memory regions.
ExampleS:
-cxl-fixed-memory-window targets.0=cxl.0,size=128G
-cxl-fixed-memory-window targets.0=cxl.1,size=128G
-cxl-fixed-memory-window targets.0=cxl0,targets.1=cxl.1,size=256G,interleave-granularity=2k
Specifies
* 2x 128G regions not interleaved across root bridges, one for each of
the root bridges with ids cxl.0 and cxl.1
* 256G region interleaved across root bridges with ids cxl.0 and cxl.1
with a 2k interleave granularity.
When system software enumerates the devices below a given root bridge
it can then decide which CFMW to use. If non interleave is desired
(or possible) it can use the appropriate CFMW for the root bridge in
question. If there are suitable devices to interleave across the
two root bridges then it may use the 3rd CFMS.
A number of other designs were considered but the following constraints
made it hard to adapt existing QEMU approaches to this particular problem.
1) The size must be known before a specific architecture / board brings
up it's PA memory map. We need to set up an appropriate region.
2) Using links to the host bridges provides a clean command line interface
but these links cannot be established until command line devices have
been added.
Hence the two step process used here of first establishing the size,
interleave-ways and granularity + caching the ids of the host bridges
and then, once available finding the actual host bridges so they can
be used later to support interleave decoding.
[1] CXL 2.0 ECN: CEDT CFMWS & QTG DSM (computeexpresslink.org / specifications)
Signed-off-by: Jonathan Cameron <jonathan.cameron@huawei.com>
Acked-by: Markus Armbruster <armbru@redhat.com> # QAPI Schema
Message-Id: <20220429144110.25167-28-Jonathan.Cameron@huawei.com>
Reviewed-by: Michael S. Tsirkin <mst@redhat.com>
Signed-off-by: Michael S. Tsirkin <mst@redhat.com>
2022-04-29 16:40:52 +02:00
|
|
|
#
|
2023-04-25 08:42:21 +02:00
|
|
|
# Since: 7.1
|
hw/cxl/host: Add support for CXL Fixed Memory Windows.
The concept of these is introduced in [1] in terms of the
description the CEDT ACPI table. The principal is more general.
Unlike once traffic hits the CXL root bridges, the host system
memory address routing is implementation defined and effectively
static once observable by standard / generic system software.
Each CXL Fixed Memory Windows (CFMW) is a region of PA space
which has fixed system dependent routing configured so that
accesses can be routed to the CXL devices below a set of target
root bridges. The accesses may be interleaved across multiple
root bridges.
For QEMU we could have fully specified these regions in terms
of a base PA + size, but as the absolute address does not matter
it is simpler to let individual platforms place the memory regions.
ExampleS:
-cxl-fixed-memory-window targets.0=cxl.0,size=128G
-cxl-fixed-memory-window targets.0=cxl.1,size=128G
-cxl-fixed-memory-window targets.0=cxl0,targets.1=cxl.1,size=256G,interleave-granularity=2k
Specifies
* 2x 128G regions not interleaved across root bridges, one for each of
the root bridges with ids cxl.0 and cxl.1
* 256G region interleaved across root bridges with ids cxl.0 and cxl.1
with a 2k interleave granularity.
When system software enumerates the devices below a given root bridge
it can then decide which CFMW to use. If non interleave is desired
(or possible) it can use the appropriate CFMW for the root bridge in
question. If there are suitable devices to interleave across the
two root bridges then it may use the 3rd CFMS.
A number of other designs were considered but the following constraints
made it hard to adapt existing QEMU approaches to this particular problem.
1) The size must be known before a specific architecture / board brings
up it's PA memory map. We need to set up an appropriate region.
2) Using links to the host bridges provides a clean command line interface
but these links cannot be established until command line devices have
been added.
Hence the two step process used here of first establishing the size,
interleave-ways and granularity + caching the ids of the host bridges
and then, once available finding the actual host bridges so they can
be used later to support interleave decoding.
[1] CXL 2.0 ECN: CEDT CFMWS & QTG DSM (computeexpresslink.org / specifications)
Signed-off-by: Jonathan Cameron <jonathan.cameron@huawei.com>
Acked-by: Markus Armbruster <armbru@redhat.com> # QAPI Schema
Message-Id: <20220429144110.25167-28-Jonathan.Cameron@huawei.com>
Reviewed-by: Michael S. Tsirkin <mst@redhat.com>
Signed-off-by: Michael S. Tsirkin <mst@redhat.com>
2022-04-29 16:40:52 +02:00
|
|
|
##
|
|
|
|
{ 'struct': 'CXLFixedMemoryWindowOptions',
|
|
|
|
'data': {
|
|
|
|
'size': 'size',
|
|
|
|
'*interleave-granularity': 'size',
|
|
|
|
'targets': ['str'] }}
|
|
|
|
|
2022-06-08 16:54:33 +02:00
|
|
|
##
|
|
|
|
# @CXLFMWProperties:
|
|
|
|
#
|
|
|
|
# List of CXL Fixed Memory Windows.
|
|
|
|
#
|
|
|
|
# @cxl-fmw: List of CXLFixedMemoryWindowOptions
|
|
|
|
#
|
2023-04-25 08:42:21 +02:00
|
|
|
# Since: 7.1
|
2022-06-08 16:54:33 +02:00
|
|
|
##
|
|
|
|
{ 'struct' : 'CXLFMWProperties',
|
|
|
|
'data': { 'cxl-fmw': ['CXLFixedMemoryWindowOptions'] }
|
|
|
|
}
|
|
|
|
|
2019-06-19 22:10:41 +02:00
|
|
|
##
|
|
|
|
# @X86CPURegister32:
|
|
|
|
#
|
|
|
|
# A X86 32-bit register
|
|
|
|
#
|
|
|
|
# Since: 1.5
|
|
|
|
##
|
|
|
|
{ 'enum': 'X86CPURegister32',
|
|
|
|
'data': [ 'EAX', 'EBX', 'ECX', 'EDX', 'ESP', 'EBP', 'ESI', 'EDI' ] }
|
|
|
|
|
|
|
|
##
|
|
|
|
# @X86CPUFeatureWordInfo:
|
|
|
|
#
|
|
|
|
# Information about a X86 CPU feature word
|
|
|
|
#
|
2023-04-28 12:54:29 +02:00
|
|
|
# @cpuid-input-eax: Input EAX value for CPUID instruction for that
|
|
|
|
# feature word
|
2019-06-19 22:10:41 +02:00
|
|
|
#
|
|
|
|
# @cpuid-input-ecx: Input ECX value for CPUID instruction for that
|
2023-04-28 12:54:29 +02:00
|
|
|
# feature word
|
2019-06-19 22:10:41 +02:00
|
|
|
#
|
|
|
|
# @cpuid-register: Output register containing the feature bits
|
|
|
|
#
|
|
|
|
# @features: value of output register, containing the feature bits
|
|
|
|
#
|
|
|
|
# Since: 1.5
|
|
|
|
##
|
|
|
|
{ 'struct': 'X86CPUFeatureWordInfo',
|
|
|
|
'data': { 'cpuid-input-eax': 'int',
|
|
|
|
'*cpuid-input-ecx': 'int',
|
|
|
|
'cpuid-register': 'X86CPURegister32',
|
|
|
|
'features': 'int' } }
|
|
|
|
|
|
|
|
##
|
|
|
|
# @DummyForceArrays:
|
|
|
|
#
|
2023-04-28 12:54:29 +02:00
|
|
|
# Not used by QMP; hack to let us use X86CPUFeatureWordInfoList
|
|
|
|
# internally
|
2019-06-19 22:10:41 +02:00
|
|
|
#
|
|
|
|
# Since: 2.5
|
|
|
|
##
|
|
|
|
{ 'struct': 'DummyForceArrays',
|
|
|
|
'data': { 'unused': ['X86CPUFeatureWordInfo'] } }
|
|
|
|
|
|
|
|
##
|
|
|
|
# @NumaCpuOptions:
|
|
|
|
#
|
2023-04-28 12:54:29 +02:00
|
|
|
# Option "-numa cpu" overrides default cpu to node mapping. It
|
|
|
|
# accepts the same set of cpu properties as returned by
|
2019-06-19 22:10:41 +02:00
|
|
|
# query-hotpluggable-cpus[].props, where node-id could be used to
|
|
|
|
# override default node mapping.
|
|
|
|
#
|
|
|
|
# Since: 2.10
|
|
|
|
##
|
|
|
|
{ 'struct': 'NumaCpuOptions',
|
|
|
|
'base': 'CpuInstanceProperties',
|
|
|
|
'data' : {} }
|
|
|
|
|
2019-12-13 02:19:23 +01:00
|
|
|
##
|
|
|
|
# @HmatLBMemoryHierarchy:
|
|
|
|
#
|
|
|
|
# The memory hierarchy in the System Locality Latency and Bandwidth
|
|
|
|
# Information Structure of HMAT (Heterogeneous Memory Attribute Table)
|
|
|
|
#
|
|
|
|
# For more information about @HmatLBMemoryHierarchy, see chapter
|
|
|
|
# 5.2.27.4: Table 5-146: Field "Flags" of ACPI 6.3 spec.
|
|
|
|
#
|
|
|
|
# @memory: the structure represents the memory performance
|
|
|
|
#
|
|
|
|
# @first-level: first level of memory side cache
|
|
|
|
#
|
|
|
|
# @second-level: second level of memory side cache
|
|
|
|
#
|
|
|
|
# @third-level: third level of memory side cache
|
|
|
|
#
|
|
|
|
# Since: 5.0
|
|
|
|
##
|
|
|
|
{ 'enum': 'HmatLBMemoryHierarchy',
|
|
|
|
'data': [ 'memory', 'first-level', 'second-level', 'third-level' ] }
|
|
|
|
|
|
|
|
##
|
|
|
|
# @HmatLBDataType:
|
|
|
|
#
|
2023-04-28 12:54:29 +02:00
|
|
|
# Data type in the System Locality Latency and Bandwidth Information
|
|
|
|
# Structure of HMAT (Heterogeneous Memory Attribute Table)
|
2019-12-13 02:19:23 +01:00
|
|
|
#
|
2023-04-28 12:54:29 +02:00
|
|
|
# For more information about @HmatLBDataType, see chapter 5.2.27.4:
|
|
|
|
# Table 5-146: Field "Data Type" of ACPI 6.3 spec.
|
2019-12-13 02:19:23 +01:00
|
|
|
#
|
|
|
|
# @access-latency: access latency (nanoseconds)
|
|
|
|
#
|
|
|
|
# @read-latency: read latency (nanoseconds)
|
|
|
|
#
|
|
|
|
# @write-latency: write latency (nanoseconds)
|
|
|
|
#
|
|
|
|
# @access-bandwidth: access bandwidth (Bytes per second)
|
|
|
|
#
|
|
|
|
# @read-bandwidth: read bandwidth (Bytes per second)
|
|
|
|
#
|
|
|
|
# @write-bandwidth: write bandwidth (Bytes per second)
|
|
|
|
#
|
|
|
|
# Since: 5.0
|
|
|
|
##
|
|
|
|
{ 'enum': 'HmatLBDataType',
|
|
|
|
'data': [ 'access-latency', 'read-latency', 'write-latency',
|
|
|
|
'access-bandwidth', 'read-bandwidth', 'write-bandwidth' ] }
|
|
|
|
|
|
|
|
##
|
|
|
|
# @NumaHmatLBOptions:
|
|
|
|
#
|
2023-04-28 12:54:29 +02:00
|
|
|
# Set the system locality latency and bandwidth information between
|
|
|
|
# Initiator and Target proximity Domains.
|
2019-12-13 02:19:23 +01:00
|
|
|
#
|
2023-04-28 12:54:29 +02:00
|
|
|
# For more information about @NumaHmatLBOptions, see chapter 5.2.27.4:
|
|
|
|
# Table 5-146 of ACPI 6.3 spec.
|
2019-12-13 02:19:23 +01:00
|
|
|
#
|
|
|
|
# @initiator: the Initiator Proximity Domain.
|
|
|
|
#
|
|
|
|
# @target: the Target Proximity Domain.
|
|
|
|
#
|
2023-04-28 12:54:29 +02:00
|
|
|
# @hierarchy: the Memory Hierarchy. Indicates the performance of
|
|
|
|
# memory or side cache.
|
2019-12-13 02:19:23 +01:00
|
|
|
#
|
2023-04-28 12:54:29 +02:00
|
|
|
# @data-type: presents the type of data, access/read/write latency or
|
|
|
|
# hit latency.
|
2019-12-13 02:19:23 +01:00
|
|
|
#
|
2023-04-28 12:54:29 +02:00
|
|
|
# @latency: the value of latency from @initiator to @target proximity
|
|
|
|
# domain, the latency unit is "ns(nanosecond)".
|
2019-12-13 02:19:23 +01:00
|
|
|
#
|
|
|
|
# @bandwidth: the value of bandwidth between @initiator and @target
|
2023-04-28 12:54:29 +02:00
|
|
|
# proximity domain, the bandwidth unit is "Bytes per second".
|
2019-12-13 02:19:23 +01:00
|
|
|
#
|
|
|
|
# Since: 5.0
|
|
|
|
##
|
|
|
|
{ 'struct': 'NumaHmatLBOptions',
|
|
|
|
'data': {
|
|
|
|
'initiator': 'uint16',
|
|
|
|
'target': 'uint16',
|
|
|
|
'hierarchy': 'HmatLBMemoryHierarchy',
|
|
|
|
'data-type': 'HmatLBDataType',
|
|
|
|
'*latency': 'uint64',
|
|
|
|
'*bandwidth': 'size' }}
|
|
|
|
|
2019-12-13 02:19:24 +01:00
|
|
|
##
|
|
|
|
# @HmatCacheAssociativity:
|
|
|
|
#
|
|
|
|
# Cache associativity in the Memory Side Cache Information Structure
|
|
|
|
# of HMAT
|
|
|
|
#
|
|
|
|
# For more information of @HmatCacheAssociativity, see chapter
|
|
|
|
# 5.2.27.5: Table 5-147 of ACPI 6.3 spec.
|
|
|
|
#
|
2023-04-28 12:54:29 +02:00
|
|
|
# @none: None (no memory side cache in this proximity domain, or cache
|
|
|
|
# associativity unknown)
|
2019-12-13 02:19:24 +01:00
|
|
|
#
|
|
|
|
# @direct: Direct Mapped
|
|
|
|
#
|
|
|
|
# @complex: Complex Cache Indexing (implementation specific)
|
|
|
|
#
|
|
|
|
# Since: 5.0
|
|
|
|
##
|
|
|
|
{ 'enum': 'HmatCacheAssociativity',
|
|
|
|
'data': [ 'none', 'direct', 'complex' ] }
|
|
|
|
|
|
|
|
##
|
|
|
|
# @HmatCacheWritePolicy:
|
|
|
|
#
|
2023-04-28 12:54:29 +02:00
|
|
|
# Cache write policy in the Memory Side Cache Information Structure of
|
|
|
|
# HMAT
|
2019-12-13 02:19:24 +01:00
|
|
|
#
|
2023-04-28 12:54:29 +02:00
|
|
|
# For more information of @HmatCacheWritePolicy, see chapter 5.2.27.5:
|
|
|
|
# Table 5-147: Field "Cache Attributes" of ACPI 6.3 spec.
|
2019-12-13 02:19:24 +01:00
|
|
|
#
|
2023-04-28 12:54:29 +02:00
|
|
|
# @none: None (no memory side cache in this proximity domain, or cache
|
|
|
|
# write policy unknown)
|
2019-12-13 02:19:24 +01:00
|
|
|
#
|
|
|
|
# @write-back: Write Back (WB)
|
|
|
|
#
|
|
|
|
# @write-through: Write Through (WT)
|
|
|
|
#
|
|
|
|
# Since: 5.0
|
|
|
|
##
|
|
|
|
{ 'enum': 'HmatCacheWritePolicy',
|
|
|
|
'data': [ 'none', 'write-back', 'write-through' ] }
|
|
|
|
|
|
|
|
##
|
|
|
|
# @NumaHmatCacheOptions:
|
|
|
|
#
|
|
|
|
# Set the memory side cache information for a given memory domain.
|
|
|
|
#
|
2023-04-28 12:54:29 +02:00
|
|
|
# For more information of @NumaHmatCacheOptions, see chapter 5.2.27.5:
|
|
|
|
# Table 5-147: Field "Cache Attributes" of ACPI 6.3 spec.
|
2019-12-13 02:19:24 +01:00
|
|
|
#
|
|
|
|
# @node-id: the memory proximity domain to which the memory belongs.
|
|
|
|
#
|
|
|
|
# @size: the size of memory side cache in bytes.
|
|
|
|
#
|
|
|
|
# @level: the cache level described in this structure.
|
|
|
|
#
|
|
|
|
# @associativity: the cache associativity,
|
2023-04-28 12:54:29 +02:00
|
|
|
# none/direct-mapped/complex(complex cache indexing).
|
2019-12-13 02:19:24 +01:00
|
|
|
#
|
|
|
|
# @policy: the write policy, none/write-back/write-through.
|
|
|
|
#
|
|
|
|
# @line: the cache Line size in bytes.
|
|
|
|
#
|
|
|
|
# Since: 5.0
|
|
|
|
##
|
|
|
|
{ 'struct': 'NumaHmatCacheOptions',
|
|
|
|
'data': {
|
|
|
|
'node-id': 'uint32',
|
|
|
|
'size': 'size',
|
|
|
|
'level': 'uint8',
|
|
|
|
'associativity': 'HmatCacheAssociativity',
|
|
|
|
'policy': 'HmatCacheWritePolicy',
|
|
|
|
'line': 'uint16' }}
|
|
|
|
|
2020-10-12 14:15:34 +02:00
|
|
|
##
|
|
|
|
# @memsave:
|
|
|
|
#
|
|
|
|
# Save a portion of guest memory to a file.
|
|
|
|
#
|
|
|
|
# @val: the virtual address of the guest to start from
|
|
|
|
#
|
|
|
|
# @size: the size of memory region to save
|
|
|
|
#
|
|
|
|
# @filename: the file to save the memory to as binary data
|
|
|
|
#
|
|
|
|
# @cpu-index: the index of the virtual CPU to use for translating the
|
2023-04-28 12:54:29 +02:00
|
|
|
# virtual address (defaults to CPU 0)
|
2020-10-12 14:15:34 +02:00
|
|
|
#
|
|
|
|
# Returns: Nothing on success
|
|
|
|
#
|
2020-11-18 07:41:58 +01:00
|
|
|
# Since: 0.14
|
2020-10-12 14:15:34 +02:00
|
|
|
#
|
|
|
|
# Notes: Errors were not reliably returned until 1.1
|
|
|
|
#
|
|
|
|
# Example:
|
|
|
|
#
|
|
|
|
# -> { "execute": "memsave",
|
|
|
|
# "arguments": { "val": 10,
|
|
|
|
# "size": 100,
|
|
|
|
# "filename": "/tmp/virtual-mem-dump" } }
|
|
|
|
# <- { "return": {} }
|
|
|
|
##
|
|
|
|
{ 'command': 'memsave',
|
|
|
|
'data': {'val': 'int', 'size': 'int', 'filename': 'str', '*cpu-index': 'int'} }
|
|
|
|
|
|
|
|
##
|
|
|
|
# @pmemsave:
|
|
|
|
#
|
|
|
|
# Save a portion of guest physical memory to a file.
|
|
|
|
#
|
|
|
|
# @val: the physical address of the guest to start from
|
|
|
|
#
|
|
|
|
# @size: the size of memory region to save
|
|
|
|
#
|
|
|
|
# @filename: the file to save the memory to as binary data
|
|
|
|
#
|
|
|
|
# Returns: Nothing on success
|
|
|
|
#
|
2020-11-18 07:41:58 +01:00
|
|
|
# Since: 0.14
|
2020-10-12 14:15:34 +02:00
|
|
|
#
|
|
|
|
# Notes: Errors were not reliably returned until 1.1
|
|
|
|
#
|
|
|
|
# Example:
|
|
|
|
#
|
|
|
|
# -> { "execute": "pmemsave",
|
|
|
|
# "arguments": { "val": 10,
|
|
|
|
# "size": 100,
|
|
|
|
# "filename": "/tmp/physical-mem-dump" } }
|
|
|
|
# <- { "return": {} }
|
|
|
|
##
|
|
|
|
{ 'command': 'pmemsave',
|
|
|
|
'data': {'val': 'int', 'size': 'int', 'filename': 'str'} }
|
|
|
|
|
2019-06-19 22:10:41 +02:00
|
|
|
##
|
|
|
|
# @Memdev:
|
|
|
|
#
|
|
|
|
# Information about memory backend
|
|
|
|
#
|
|
|
|
# @id: backend's ID if backend has 'id' property (since 2.9)
|
|
|
|
#
|
|
|
|
# @size: memory backend size
|
|
|
|
#
|
2021-05-10 13:43:24 +02:00
|
|
|
# @merge: whether memory merge support is enabled
|
2019-06-19 22:10:41 +02:00
|
|
|
#
|
2021-05-10 13:43:24 +02:00
|
|
|
# @dump: whether memory backend's memory is included in a core dump
|
2019-06-19 22:10:41 +02:00
|
|
|
#
|
2021-05-10 13:43:24 +02:00
|
|
|
# @prealloc: whether memory was preallocated
|
2019-06-19 22:10:41 +02:00
|
|
|
#
|
2021-05-10 13:43:25 +02:00
|
|
|
# @share: whether memory is private to QEMU or shared (since 6.1)
|
|
|
|
#
|
2023-04-28 12:54:29 +02:00
|
|
|
# @reserve: whether swap space (or huge pages) was reserved if
|
|
|
|
# applicable. This corresponds to the user configuration and not
|
|
|
|
# the actual behavior implemented in the OS to perform the
|
|
|
|
# reservation. For example, Linux will never reserve swap space
|
|
|
|
# for shared file mappings. (since 6.1)
|
2021-05-10 13:43:27 +02:00
|
|
|
#
|
2019-06-19 22:10:41 +02:00
|
|
|
# @host-nodes: host nodes for its memory policy
|
|
|
|
#
|
|
|
|
# @policy: memory policy of memory backend
|
|
|
|
#
|
|
|
|
# Since: 2.1
|
|
|
|
##
|
|
|
|
{ 'struct': 'Memdev',
|
|
|
|
'data': {
|
|
|
|
'*id': 'str',
|
|
|
|
'size': 'size',
|
|
|
|
'merge': 'bool',
|
|
|
|
'dump': 'bool',
|
|
|
|
'prealloc': 'bool',
|
2021-05-10 13:43:25 +02:00
|
|
|
'share': 'bool',
|
2021-05-10 13:43:27 +02:00
|
|
|
'*reserve': 'bool',
|
2019-06-19 22:10:41 +02:00
|
|
|
'host-nodes': ['uint16'],
|
|
|
|
'policy': 'HostMemPolicy' }}
|
|
|
|
|
|
|
|
##
|
|
|
|
# @query-memdev:
|
|
|
|
#
|
|
|
|
# Returns information for all memory backends.
|
|
|
|
#
|
|
|
|
# Returns: a list of @Memdev.
|
|
|
|
#
|
|
|
|
# Since: 2.1
|
|
|
|
#
|
|
|
|
# Example:
|
|
|
|
#
|
|
|
|
# -> { "execute": "query-memdev" }
|
|
|
|
# <- { "return": [
|
|
|
|
# {
|
|
|
|
# "id": "mem1",
|
|
|
|
# "size": 536870912,
|
|
|
|
# "merge": false,
|
|
|
|
# "dump": true,
|
|
|
|
# "prealloc": false,
|
2022-03-31 21:06:33 +02:00
|
|
|
# "share": false,
|
2019-06-19 22:10:41 +02:00
|
|
|
# "host-nodes": [0, 1],
|
|
|
|
# "policy": "bind"
|
|
|
|
# },
|
|
|
|
# {
|
|
|
|
# "size": 536870912,
|
|
|
|
# "merge": false,
|
|
|
|
# "dump": true,
|
|
|
|
# "prealloc": true,
|
2022-03-31 21:06:33 +02:00
|
|
|
# "share": false,
|
2019-06-19 22:10:41 +02:00
|
|
|
# "host-nodes": [2, 3],
|
|
|
|
# "policy": "preferred"
|
|
|
|
# }
|
|
|
|
# ]
|
|
|
|
# }
|
|
|
|
##
|
|
|
|
{ 'command': 'query-memdev', 'returns': ['Memdev'], 'allow-preconfig': true }
|
|
|
|
|
|
|
|
##
|
|
|
|
# @CpuInstanceProperties:
|
|
|
|
#
|
2023-04-28 12:54:29 +02:00
|
|
|
# List of properties to be used for hotplugging a CPU instance, it
|
|
|
|
# should be passed by management with device_add command when a CPU is
|
|
|
|
# being hotplugged.
|
2019-06-19 22:10:41 +02:00
|
|
|
#
|
2023-10-16 20:39:05 +02:00
|
|
|
# Which members are optional and which mandatory depends on the
|
|
|
|
# architecture and board.
|
|
|
|
#
|
2023-10-16 20:39:18 +02:00
|
|
|
# For s390x see :ref:`cpu-topology-s390x`.
|
|
|
|
#
|
2023-10-16 20:39:05 +02:00
|
|
|
# The ids other than the node-id specify the position of the CPU
|
|
|
|
# within the CPU topology (as defined by the machine property "smp",
|
|
|
|
# thus see also type @SMPConfiguration)
|
|
|
|
#
|
2019-06-19 22:10:41 +02:00
|
|
|
# @node-id: NUMA node ID the CPU belongs to
|
2023-04-28 12:54:29 +02:00
|
|
|
#
|
2023-10-16 20:39:06 +02:00
|
|
|
# @drawer-id: drawer number within CPU topology the CPU belongs to
|
|
|
|
# (since 8.2)
|
|
|
|
#
|
|
|
|
# @book-id: book number within parent container the CPU belongs to
|
|
|
|
# (since 8.2)
|
|
|
|
#
|
|
|
|
# @socket-id: socket number within parent container the CPU belongs to
|
2023-04-28 12:54:29 +02:00
|
|
|
#
|
2023-10-16 20:39:05 +02:00
|
|
|
# @die-id: die number within the parent container the CPU belongs to
|
|
|
|
# (since 4.1)
|
2023-04-28 12:54:29 +02:00
|
|
|
#
|
2023-10-16 20:39:05 +02:00
|
|
|
# @cluster-id: cluster number within the parent container the CPU
|
|
|
|
# belongs to (since 7.1)
|
2023-04-28 12:54:29 +02:00
|
|
|
#
|
2023-10-16 20:39:05 +02:00
|
|
|
# @core-id: core number within the parent container the CPU
|
|
|
|
# belongs to
|
2023-04-28 12:54:29 +02:00
|
|
|
#
|
2023-10-16 20:39:05 +02:00
|
|
|
# @thread-id: thread number within the core the CPU belongs to
|
2019-06-19 22:10:41 +02:00
|
|
|
#
|
2023-10-16 20:39:05 +02:00
|
|
|
# Note: management should be prepared to pass through additional
|
|
|
|
# properties with device_add.
|
2019-06-19 22:10:41 +02:00
|
|
|
#
|
|
|
|
# Since: 2.7
|
|
|
|
##
|
|
|
|
{ 'struct': 'CpuInstanceProperties',
|
2023-10-16 20:39:05 +02:00
|
|
|
# Keep these in sync with the properties device_add accepts
|
2019-06-19 22:10:41 +02:00
|
|
|
'data': { '*node-id': 'int',
|
2023-10-16 20:39:06 +02:00
|
|
|
'*drawer-id': 'int',
|
|
|
|
'*book-id': 'int',
|
2019-06-19 22:10:41 +02:00
|
|
|
'*socket-id': 'int',
|
2019-06-12 10:40:58 +02:00
|
|
|
'*die-id': 'int',
|
2022-05-03 16:02:59 +02:00
|
|
|
'*cluster-id': 'int',
|
2019-06-19 22:10:41 +02:00
|
|
|
'*core-id': 'int',
|
|
|
|
'*thread-id': 'int'
|
|
|
|
}
|
|
|
|
}
|
|
|
|
|
|
|
|
##
|
|
|
|
# @HotpluggableCPU:
|
|
|
|
#
|
|
|
|
# @type: CPU object type for usage with device_add command
|
2023-04-28 12:54:29 +02:00
|
|
|
#
|
2019-06-19 22:10:41 +02:00
|
|
|
# @props: list of properties to be used for hotplugging CPU
|
2023-04-28 12:54:29 +02:00
|
|
|
#
|
|
|
|
# @vcpus-count: number of logical VCPU threads @HotpluggableCPU
|
|
|
|
# provides
|
|
|
|
#
|
|
|
|
# @qom-path: link to existing CPU object if CPU is present or omitted
|
|
|
|
# if CPU is not present.
|
2019-06-19 22:10:41 +02:00
|
|
|
#
|
|
|
|
# Since: 2.7
|
|
|
|
##
|
|
|
|
{ 'struct': 'HotpluggableCPU',
|
|
|
|
'data': { 'type': 'str',
|
|
|
|
'vcpus-count': 'int',
|
|
|
|
'props': 'CpuInstanceProperties',
|
|
|
|
'*qom-path': 'str'
|
|
|
|
}
|
|
|
|
}
|
|
|
|
|
|
|
|
##
|
|
|
|
# @query-hotpluggable-cpus:
|
|
|
|
#
|
|
|
|
# TODO: Better documentation; currently there is none.
|
|
|
|
#
|
|
|
|
# Returns: a list of HotpluggableCPU objects.
|
|
|
|
#
|
|
|
|
# Since: 2.7
|
|
|
|
#
|
2023-04-25 08:42:14 +02:00
|
|
|
# Examples:
|
2019-06-19 22:10:41 +02:00
|
|
|
#
|
2023-04-28 12:54:29 +02:00
|
|
|
# For pseries machine type started with -smp 2,cores=2,maxcpus=4 -cpu
|
|
|
|
# POWER8:
|
2019-06-19 22:10:41 +02:00
|
|
|
#
|
|
|
|
# -> { "execute": "query-hotpluggable-cpus" }
|
|
|
|
# <- {"return": [
|
2022-09-01 10:58:39 +02:00
|
|
|
# { "props": { "core-id": 8 }, "type": "POWER8-spapr-cpu-core",
|
2019-06-19 22:10:41 +02:00
|
|
|
# "vcpus-count": 1 },
|
2022-09-01 10:58:39 +02:00
|
|
|
# { "props": { "core-id": 0 }, "type": "POWER8-spapr-cpu-core",
|
2019-06-19 22:10:41 +02:00
|
|
|
# "vcpus-count": 1, "qom-path": "/machine/unattached/device[0]"}
|
|
|
|
# ]}'
|
|
|
|
#
|
|
|
|
# For pc machine type started with -smp 1,maxcpus=2:
|
|
|
|
#
|
|
|
|
# -> { "execute": "query-hotpluggable-cpus" }
|
|
|
|
# <- {"return": [
|
|
|
|
# {
|
|
|
|
# "type": "qemu64-x86_64-cpu", "vcpus-count": 1,
|
|
|
|
# "props": {"core-id": 0, "socket-id": 1, "thread-id": 0}
|
|
|
|
# },
|
|
|
|
# {
|
|
|
|
# "qom-path": "/machine/unattached/device[0]",
|
|
|
|
# "type": "qemu64-x86_64-cpu", "vcpus-count": 1,
|
|
|
|
# "props": {"core-id": 0, "socket-id": 0, "thread-id": 0}
|
|
|
|
# }
|
|
|
|
# ]}
|
|
|
|
#
|
2023-04-28 12:54:29 +02:00
|
|
|
# For s390x-virtio-ccw machine type started with -smp 1,maxcpus=2 -cpu
|
|
|
|
# qemu (Since: 2.11):
|
2019-06-19 22:10:41 +02:00
|
|
|
#
|
|
|
|
# -> { "execute": "query-hotpluggable-cpus" }
|
|
|
|
# <- {"return": [
|
|
|
|
# {
|
|
|
|
# "type": "qemu-s390x-cpu", "vcpus-count": 1,
|
|
|
|
# "props": { "core-id": 1 }
|
|
|
|
# },
|
|
|
|
# {
|
|
|
|
# "qom-path": "/machine/unattached/device[0]",
|
|
|
|
# "type": "qemu-s390x-cpu", "vcpus-count": 1,
|
|
|
|
# "props": { "core-id": 0 }
|
|
|
|
# }
|
|
|
|
# ]}
|
|
|
|
##
|
|
|
|
{ 'command': 'query-hotpluggable-cpus', 'returns': ['HotpluggableCPU'],
|
|
|
|
'allow-preconfig': true }
|
|
|
|
|
|
|
|
##
|
|
|
|
# @set-numa-node:
|
|
|
|
#
|
2023-04-28 12:54:29 +02:00
|
|
|
# Runtime equivalent of '-numa' CLI option, available at preconfigure
|
|
|
|
# stage to configure numa mapping before initializing machine.
|
2019-06-19 22:10:41 +02:00
|
|
|
#
|
2022-04-22 15:28:07 +02:00
|
|
|
# Since: 3.0
|
2019-06-19 22:10:41 +02:00
|
|
|
##
|
|
|
|
{ 'command': 'set-numa-node', 'boxed': true,
|
|
|
|
'data': 'NumaOptions',
|
|
|
|
'allow-preconfig': true
|
|
|
|
}
|
2020-09-13 21:53:43 +02:00
|
|
|
|
|
|
|
##
|
|
|
|
# @balloon:
|
|
|
|
#
|
|
|
|
# Request the balloon driver to change its balloon size.
|
|
|
|
#
|
2023-04-28 12:54:29 +02:00
|
|
|
# @value: the target logical size of the VM in bytes. We can deduce
|
|
|
|
# the size of the balloon using this formula:
|
2020-09-25 18:22:56 +02:00
|
|
|
#
|
2023-04-28 12:54:29 +02:00
|
|
|
# logical_vm_size = vm_ram_size - balloon_size
|
2020-09-25 18:22:56 +02:00
|
|
|
#
|
2023-04-28 12:54:29 +02:00
|
|
|
# From it we have: balloon_size = vm_ram_size - @value
|
2020-09-13 21:53:43 +02:00
|
|
|
#
|
2023-04-28 12:54:29 +02:00
|
|
|
# Returns:
|
|
|
|
# - Nothing on success
|
|
|
|
# - If the balloon driver is enabled but not functional because the
|
|
|
|
# KVM kernel module cannot support it, KVMMissingCap
|
|
|
|
# - If no balloon device is present, DeviceNotActive
|
2020-09-13 21:53:43 +02:00
|
|
|
#
|
2023-04-28 12:54:29 +02:00
|
|
|
# Notes: This command just issues a request to the guest. When it
|
|
|
|
# returns, the balloon size may not have changed. A guest can
|
|
|
|
# change the balloon size independent of this command.
|
2020-09-13 21:53:43 +02:00
|
|
|
#
|
2020-11-18 07:41:58 +01:00
|
|
|
# Since: 0.14
|
2020-09-13 21:53:43 +02:00
|
|
|
#
|
|
|
|
# Example:
|
|
|
|
#
|
|
|
|
# -> { "execute": "balloon", "arguments": { "value": 536870912 } }
|
|
|
|
# <- { "return": {} }
|
|
|
|
#
|
|
|
|
# With a 2.5GiB guest this command inflated the ballon to 3GiB.
|
|
|
|
##
|
|
|
|
{ 'command': 'balloon', 'data': {'value': 'int'} }
|
|
|
|
|
|
|
|
##
|
|
|
|
# @BalloonInfo:
|
|
|
|
#
|
|
|
|
# Information about the guest balloon device.
|
|
|
|
#
|
2023-04-28 12:54:29 +02:00
|
|
|
# @actual: the logical size of the VM in bytes Formula used:
|
|
|
|
# logical_vm_size = vm_ram_size - balloon_size
|
2020-09-13 21:53:43 +02:00
|
|
|
#
|
2020-11-18 07:41:58 +01:00
|
|
|
# Since: 0.14
|
2020-09-13 21:53:43 +02:00
|
|
|
##
|
|
|
|
{ 'struct': 'BalloonInfo', 'data': {'actual': 'int' } }
|
|
|
|
|
|
|
|
##
|
|
|
|
# @query-balloon:
|
|
|
|
#
|
|
|
|
# Return information about the balloon device.
|
|
|
|
#
|
2023-04-28 12:54:29 +02:00
|
|
|
# Returns:
|
|
|
|
# - @BalloonInfo on success
|
|
|
|
# - If the balloon driver is enabled but not functional because the
|
|
|
|
# KVM kernel module cannot support it, KVMMissingCap
|
|
|
|
# - If no balloon device is present, DeviceNotActive
|
2020-09-13 21:53:43 +02:00
|
|
|
#
|
2020-11-18 07:41:58 +01:00
|
|
|
# Since: 0.14
|
2020-09-13 21:53:43 +02:00
|
|
|
#
|
|
|
|
# Example:
|
|
|
|
#
|
|
|
|
# -> { "execute": "query-balloon" }
|
|
|
|
# <- { "return": {
|
2022-09-01 10:58:31 +02:00
|
|
|
# "actual": 1073741824
|
2020-09-13 21:53:43 +02:00
|
|
|
# }
|
|
|
|
# }
|
|
|
|
##
|
|
|
|
{ 'command': 'query-balloon', 'returns': 'BalloonInfo' }
|
|
|
|
|
|
|
|
##
|
|
|
|
# @BALLOON_CHANGE:
|
|
|
|
#
|
2023-04-28 12:54:29 +02:00
|
|
|
# Emitted when the guest changes the actual BALLOON level. This value
|
|
|
|
# is equivalent to the @actual field return by the 'query-balloon'
|
|
|
|
# command
|
2020-09-13 21:53:43 +02:00
|
|
|
#
|
2023-04-28 12:54:29 +02:00
|
|
|
# @actual: the logical size of the VM in bytes Formula used:
|
|
|
|
# logical_vm_size = vm_ram_size - balloon_size
|
2020-09-13 21:53:43 +02:00
|
|
|
#
|
|
|
|
# Note: this event is rate-limited.
|
|
|
|
#
|
|
|
|
# Since: 1.2
|
|
|
|
#
|
|
|
|
# Example:
|
|
|
|
#
|
|
|
|
# <- { "event": "BALLOON_CHANGE",
|
|
|
|
# "data": { "actual": 944766976 },
|
|
|
|
# "timestamp": { "seconds": 1267020223, "microseconds": 435656 } }
|
|
|
|
##
|
|
|
|
{ 'event': 'BALLOON_CHANGE',
|
|
|
|
'data': { 'actual': 'int' } }
|
2020-09-13 21:53:46 +02:00
|
|
|
|
|
|
|
##
|
|
|
|
# @MemoryInfo:
|
|
|
|
#
|
|
|
|
# Actual memory information in bytes.
|
|
|
|
#
|
|
|
|
# @base-memory: size of "base" memory specified with command line
|
2023-04-28 12:54:29 +02:00
|
|
|
# option -m.
|
2020-09-13 21:53:46 +02:00
|
|
|
#
|
2023-04-28 12:54:29 +02:00
|
|
|
# @plugged-memory: size of memory that can be hot-unplugged. This
|
|
|
|
# field is omitted if target doesn't support memory hotplug (i.e.
|
|
|
|
# CONFIG_MEM_DEVICE not defined at build time).
|
2020-09-13 21:53:46 +02:00
|
|
|
#
|
2020-11-18 07:41:58 +01:00
|
|
|
# Since: 2.11
|
2020-09-13 21:53:46 +02:00
|
|
|
##
|
|
|
|
{ 'struct': 'MemoryInfo',
|
|
|
|
'data' : { 'base-memory': 'size', '*plugged-memory': 'size' } }
|
|
|
|
|
|
|
|
##
|
|
|
|
# @query-memory-size-summary:
|
|
|
|
#
|
2023-04-28 12:54:29 +02:00
|
|
|
# Return the amount of initially allocated and present hotpluggable
|
|
|
|
# (if enabled) memory in bytes.
|
2020-09-13 21:53:46 +02:00
|
|
|
#
|
|
|
|
# Example:
|
|
|
|
#
|
|
|
|
# -> { "execute": "query-memory-size-summary" }
|
|
|
|
# <- { "return": { "base-memory": 4294967296, "plugged-memory": 0 } }
|
|
|
|
#
|
2020-11-18 07:41:58 +01:00
|
|
|
# Since: 2.11
|
2020-09-13 21:53:46 +02:00
|
|
|
##
|
|
|
|
{ 'command': 'query-memory-size-summary', 'returns': 'MemoryInfo' }
|
|
|
|
|
|
|
|
##
|
|
|
|
# @PCDIMMDeviceInfo:
|
|
|
|
#
|
|
|
|
# PCDIMMDevice state information
|
|
|
|
#
|
|
|
|
# @id: device's ID
|
|
|
|
#
|
|
|
|
# @addr: physical address, where device is mapped
|
|
|
|
#
|
|
|
|
# @size: size of memory that the device provides
|
|
|
|
#
|
|
|
|
# @slot: slot number at which device is plugged in
|
|
|
|
#
|
|
|
|
# @node: NUMA node number where device is plugged in
|
|
|
|
#
|
|
|
|
# @memdev: memory backend linked with device
|
|
|
|
#
|
|
|
|
# @hotplugged: true if device was hotplugged
|
|
|
|
#
|
2023-04-28 12:54:29 +02:00
|
|
|
# @hotpluggable: true if device if could be added/removed while
|
|
|
|
# machine is running
|
2020-09-13 21:53:46 +02:00
|
|
|
#
|
|
|
|
# Since: 2.1
|
|
|
|
##
|
|
|
|
{ 'struct': 'PCDIMMDeviceInfo',
|
|
|
|
'data': { '*id': 'str',
|
|
|
|
'addr': 'int',
|
|
|
|
'size': 'int',
|
|
|
|
'slot': 'int',
|
|
|
|
'node': 'int',
|
|
|
|
'memdev': 'str',
|
|
|
|
'hotplugged': 'bool',
|
|
|
|
'hotpluggable': 'bool'
|
|
|
|
}
|
|
|
|
}
|
|
|
|
|
|
|
|
##
|
|
|
|
# @VirtioPMEMDeviceInfo:
|
|
|
|
#
|
|
|
|
# VirtioPMEM state information
|
|
|
|
#
|
|
|
|
# @id: device's ID
|
|
|
|
#
|
|
|
|
# @memaddr: physical address in memory, where device is mapped
|
|
|
|
#
|
|
|
|
# @size: size of memory that the device provides
|
|
|
|
#
|
|
|
|
# @memdev: memory backend linked with device
|
|
|
|
#
|
|
|
|
# Since: 4.1
|
|
|
|
##
|
|
|
|
{ 'struct': 'VirtioPMEMDeviceInfo',
|
|
|
|
'data': { '*id': 'str',
|
|
|
|
'memaddr': 'size',
|
|
|
|
'size': 'size',
|
|
|
|
'memdev': 'str'
|
|
|
|
}
|
|
|
|
}
|
|
|
|
|
|
|
|
##
|
|
|
|
# @VirtioMEMDeviceInfo:
|
|
|
|
#
|
|
|
|
# VirtioMEMDevice state information
|
|
|
|
#
|
|
|
|
# @id: device's ID
|
|
|
|
#
|
|
|
|
# @memaddr: physical address in memory, where device is mapped
|
|
|
|
#
|
|
|
|
# @requested-size: the user requested size of the device
|
|
|
|
#
|
|
|
|
# @size: the (current) size of memory that the device provides
|
|
|
|
#
|
|
|
|
# @max-size: the maximum size of memory that the device can provide
|
|
|
|
#
|
|
|
|
# @block-size: the block size of memory that the device provides
|
|
|
|
#
|
|
|
|
# @node: NUMA node number where device is assigned to
|
|
|
|
#
|
|
|
|
# @memdev: memory backend linked with the region
|
|
|
|
#
|
|
|
|
# Since: 5.1
|
|
|
|
##
|
|
|
|
{ 'struct': 'VirtioMEMDeviceInfo',
|
|
|
|
'data': { '*id': 'str',
|
|
|
|
'memaddr': 'size',
|
|
|
|
'requested-size': 'size',
|
|
|
|
'size': 'size',
|
|
|
|
'max-size': 'size',
|
|
|
|
'block-size': 'size',
|
|
|
|
'node': 'int',
|
|
|
|
'memdev': 'str'
|
|
|
|
}
|
|
|
|
}
|
|
|
|
|
2021-07-19 13:21:35 +02:00
|
|
|
##
|
|
|
|
# @SgxEPCDeviceInfo:
|
|
|
|
#
|
|
|
|
# Sgx EPC state information
|
|
|
|
#
|
|
|
|
# @id: device's ID
|
|
|
|
#
|
|
|
|
# @memaddr: physical address in memory, where device is mapped
|
|
|
|
#
|
|
|
|
# @size: size of memory that the device provides
|
|
|
|
#
|
|
|
|
# @memdev: memory backend linked with device
|
|
|
|
#
|
2022-01-20 23:31:04 +01:00
|
|
|
# @node: the numa node (Since: 7.0)
|
numa: Enable numa for SGX EPC sections
The basic SGX did not enable numa for SGX EPC sections, which
result in all EPC sections located in numa node 0. This patch
enable SGX numa function in the guest and the EPC section can
work with RAM as one numa node.
The Guest kernel related log:
[ 0.009981] ACPI: SRAT: Node 0 PXM 0 [mem 0x180000000-0x183ffffff]
[ 0.009982] ACPI: SRAT: Node 1 PXM 1 [mem 0x184000000-0x185bfffff]
The SRAT table can normally show SGX EPC sections menory info in different
numa nodes.
The SGX EPC numa related command:
......
-m 4G,maxmem=20G \
-smp sockets=2,cores=2 \
-cpu host,+sgx-provisionkey \
-object memory-backend-ram,size=2G,host-nodes=0,policy=bind,id=node0 \
-object memory-backend-epc,id=mem0,size=64M,prealloc=on,host-nodes=0,policy=bind \
-numa node,nodeid=0,cpus=0-1,memdev=node0 \
-object memory-backend-ram,size=2G,host-nodes=1,policy=bind,id=node1 \
-object memory-backend-epc,id=mem1,size=28M,prealloc=on,host-nodes=1,policy=bind \
-numa node,nodeid=1,cpus=2-3,memdev=node1 \
-M sgx-epc.0.memdev=mem0,sgx-epc.0.node=0,sgx-epc.1.memdev=mem1,sgx-epc.1.node=1 \
......
Signed-off-by: Yang Zhong <yang.zhong@intel.com>
Message-Id: <20211101162009.62161-2-yang.zhong@intel.com>
Signed-off-by: Paolo Bonzini <pbonzini@redhat.com>
2021-11-01 17:20:05 +01:00
|
|
|
#
|
2021-07-19 13:21:35 +02:00
|
|
|
# Since: 6.2
|
|
|
|
##
|
|
|
|
{ 'struct': 'SgxEPCDeviceInfo',
|
|
|
|
'data': { '*id': 'str',
|
|
|
|
'memaddr': 'size',
|
|
|
|
'size': 'size',
|
numa: Enable numa for SGX EPC sections
The basic SGX did not enable numa for SGX EPC sections, which
result in all EPC sections located in numa node 0. This patch
enable SGX numa function in the guest and the EPC section can
work with RAM as one numa node.
The Guest kernel related log:
[ 0.009981] ACPI: SRAT: Node 0 PXM 0 [mem 0x180000000-0x183ffffff]
[ 0.009982] ACPI: SRAT: Node 1 PXM 1 [mem 0x184000000-0x185bfffff]
The SRAT table can normally show SGX EPC sections menory info in different
numa nodes.
The SGX EPC numa related command:
......
-m 4G,maxmem=20G \
-smp sockets=2,cores=2 \
-cpu host,+sgx-provisionkey \
-object memory-backend-ram,size=2G,host-nodes=0,policy=bind,id=node0 \
-object memory-backend-epc,id=mem0,size=64M,prealloc=on,host-nodes=0,policy=bind \
-numa node,nodeid=0,cpus=0-1,memdev=node0 \
-object memory-backend-ram,size=2G,host-nodes=1,policy=bind,id=node1 \
-object memory-backend-epc,id=mem1,size=28M,prealloc=on,host-nodes=1,policy=bind \
-numa node,nodeid=1,cpus=2-3,memdev=node1 \
-M sgx-epc.0.memdev=mem0,sgx-epc.0.node=0,sgx-epc.1.memdev=mem1,sgx-epc.1.node=1 \
......
Signed-off-by: Yang Zhong <yang.zhong@intel.com>
Message-Id: <20211101162009.62161-2-yang.zhong@intel.com>
Signed-off-by: Paolo Bonzini <pbonzini@redhat.com>
2021-11-01 17:20:05 +01:00
|
|
|
'node': 'int',
|
2021-07-19 13:21:35 +02:00
|
|
|
'memdev': 'str'
|
|
|
|
}
|
|
|
|
}
|
|
|
|
|
2023-08-23 23:31:35 +02:00
|
|
|
##
|
|
|
|
# @HvBalloonDeviceInfo:
|
|
|
|
#
|
|
|
|
# hv-balloon provided memory state information
|
|
|
|
#
|
|
|
|
# @id: device's ID
|
|
|
|
#
|
|
|
|
# @memaddr: physical address in memory, where device is mapped
|
|
|
|
#
|
|
|
|
# @max-size: the maximum size of memory that the device can provide
|
|
|
|
#
|
|
|
|
# @memdev: memory backend linked with device
|
|
|
|
#
|
|
|
|
# Since: 8.2
|
|
|
|
##
|
|
|
|
{ 'struct': 'HvBalloonDeviceInfo',
|
|
|
|
'data': { '*id': 'str',
|
|
|
|
'*memaddr': 'size',
|
|
|
|
'max-size': 'size',
|
|
|
|
'*memdev': 'str'
|
|
|
|
}
|
|
|
|
}
|
|
|
|
|
2021-09-17 16:31:17 +02:00
|
|
|
##
|
|
|
|
# @MemoryDeviceInfoKind:
|
|
|
|
#
|
2023-04-25 08:42:20 +02:00
|
|
|
# @nvdimm: since 2.12
|
|
|
|
#
|
|
|
|
# @virtio-pmem: since 4.1
|
|
|
|
#
|
|
|
|
# @virtio-mem: since 5.1
|
|
|
|
#
|
|
|
|
# @sgx-epc: since 6.2.
|
|
|
|
#
|
2023-08-23 23:31:35 +02:00
|
|
|
# @hv-balloon: since 8.2.
|
|
|
|
#
|
2021-09-17 16:31:17 +02:00
|
|
|
# Since: 2.1
|
|
|
|
##
|
|
|
|
{ 'enum': 'MemoryDeviceInfoKind',
|
2023-08-23 23:31:35 +02:00
|
|
|
'data': [ 'dimm', 'nvdimm', 'virtio-pmem', 'virtio-mem', 'sgx-epc',
|
|
|
|
'hv-balloon' ] }
|
2021-09-17 16:31:17 +02:00
|
|
|
|
|
|
|
##
|
|
|
|
# @PCDIMMDeviceInfoWrapper:
|
|
|
|
#
|
|
|
|
# Since: 2.1
|
|
|
|
##
|
|
|
|
{ 'struct': 'PCDIMMDeviceInfoWrapper',
|
|
|
|
'data': { 'data': 'PCDIMMDeviceInfo' } }
|
|
|
|
|
|
|
|
##
|
|
|
|
# @VirtioPMEMDeviceInfoWrapper:
|
|
|
|
#
|
|
|
|
# Since: 2.1
|
|
|
|
##
|
|
|
|
{ 'struct': 'VirtioPMEMDeviceInfoWrapper',
|
|
|
|
'data': { 'data': 'VirtioPMEMDeviceInfo' } }
|
|
|
|
|
|
|
|
##
|
|
|
|
# @VirtioMEMDeviceInfoWrapper:
|
|
|
|
#
|
|
|
|
# Since: 2.1
|
|
|
|
##
|
|
|
|
{ 'struct': 'VirtioMEMDeviceInfoWrapper',
|
|
|
|
'data': { 'data': 'VirtioMEMDeviceInfo' } }
|
|
|
|
|
2021-07-19 13:21:35 +02:00
|
|
|
##
|
|
|
|
# @SgxEPCDeviceInfoWrapper:
|
|
|
|
#
|
|
|
|
# Since: 6.2
|
|
|
|
##
|
|
|
|
{ 'struct': 'SgxEPCDeviceInfoWrapper',
|
|
|
|
'data': { 'data': 'SgxEPCDeviceInfo' } }
|
|
|
|
|
2023-08-23 23:31:35 +02:00
|
|
|
##
|
|
|
|
# @HvBalloonDeviceInfoWrapper:
|
|
|
|
#
|
|
|
|
# Since: 8.2
|
|
|
|
##
|
|
|
|
{ 'struct': 'HvBalloonDeviceInfoWrapper',
|
|
|
|
'data': { 'data': 'HvBalloonDeviceInfo' } }
|
|
|
|
|
2020-09-13 21:53:46 +02:00
|
|
|
##
|
|
|
|
# @MemoryDeviceInfo:
|
|
|
|
#
|
|
|
|
# Union containing information about a memory device
|
|
|
|
#
|
|
|
|
# Since: 2.1
|
|
|
|
##
|
|
|
|
{ 'union': 'MemoryDeviceInfo',
|
2021-09-17 16:31:17 +02:00
|
|
|
'base': { 'type': 'MemoryDeviceInfoKind' },
|
|
|
|
'discriminator': 'type',
|
|
|
|
'data': { 'dimm': 'PCDIMMDeviceInfoWrapper',
|
|
|
|
'nvdimm': 'PCDIMMDeviceInfoWrapper',
|
|
|
|
'virtio-pmem': 'VirtioPMEMDeviceInfoWrapper',
|
2021-07-19 13:21:35 +02:00
|
|
|
'virtio-mem': 'VirtioMEMDeviceInfoWrapper',
|
2023-08-23 23:31:35 +02:00
|
|
|
'sgx-epc': 'SgxEPCDeviceInfoWrapper',
|
|
|
|
'hv-balloon': 'HvBalloonDeviceInfoWrapper'
|
2020-09-13 21:53:46 +02:00
|
|
|
}
|
|
|
|
}
|
|
|
|
|
vl: Add sgx compound properties to expose SGX EPC sections to guest
Because SGX EPC is enumerated through CPUID, EPC "devices" need to be
realized prior to realizing the vCPUs themselves, i.e. long before
generic devices are parsed and realized. From a virtualization
perspective, the CPUID aspect also means that EPC sections cannot be
hotplugged without paravirtualizing the guest kernel (hardware does
not support hotplugging as EPC sections must be locked down during
pre-boot to provide EPC's security properties).
So even though EPC sections could be realized through the generic
-devices command, they need to be created much earlier for them to
actually be usable by the guest. Place all EPC sections in a
contiguous block, somewhat arbitrarily starting after RAM above 4g.
Ensuring EPC is in a contiguous region simplifies calculations, e.g.
device memory base, PCI hole, etc..., allows dynamic calculation of the
total EPC size, e.g. exposing EPC to guests does not require -maxmem,
and last but not least allows all of EPC to be enumerated in a single
ACPI entry, which is expected by some kernels, e.g. Windows 7 and 8.
The new compound properties command for sgx like below:
......
-object memory-backend-epc,id=mem1,size=28M,prealloc=on \
-object memory-backend-epc,id=mem2,size=10M \
-M sgx-epc.0.memdev=mem1,sgx-epc.1.memdev=mem2
Signed-off-by: Sean Christopherson <sean.j.christopherson@intel.com>
Signed-off-by: Yang Zhong <yang.zhong@intel.com>
Message-Id: <20210719112136.57018-6-yang.zhong@intel.com>
Signed-off-by: Paolo Bonzini <pbonzini@redhat.com>
2021-09-28 10:40:58 +02:00
|
|
|
##
|
|
|
|
# @SgxEPC:
|
|
|
|
#
|
|
|
|
# Sgx EPC cmdline information
|
|
|
|
#
|
|
|
|
# @memdev: memory backend linked with device
|
|
|
|
#
|
2022-01-20 23:31:04 +01:00
|
|
|
# @node: the numa node (Since: 7.0)
|
numa: Enable numa for SGX EPC sections
The basic SGX did not enable numa for SGX EPC sections, which
result in all EPC sections located in numa node 0. This patch
enable SGX numa function in the guest and the EPC section can
work with RAM as one numa node.
The Guest kernel related log:
[ 0.009981] ACPI: SRAT: Node 0 PXM 0 [mem 0x180000000-0x183ffffff]
[ 0.009982] ACPI: SRAT: Node 1 PXM 1 [mem 0x184000000-0x185bfffff]
The SRAT table can normally show SGX EPC sections menory info in different
numa nodes.
The SGX EPC numa related command:
......
-m 4G,maxmem=20G \
-smp sockets=2,cores=2 \
-cpu host,+sgx-provisionkey \
-object memory-backend-ram,size=2G,host-nodes=0,policy=bind,id=node0 \
-object memory-backend-epc,id=mem0,size=64M,prealloc=on,host-nodes=0,policy=bind \
-numa node,nodeid=0,cpus=0-1,memdev=node0 \
-object memory-backend-ram,size=2G,host-nodes=1,policy=bind,id=node1 \
-object memory-backend-epc,id=mem1,size=28M,prealloc=on,host-nodes=1,policy=bind \
-numa node,nodeid=1,cpus=2-3,memdev=node1 \
-M sgx-epc.0.memdev=mem0,sgx-epc.0.node=0,sgx-epc.1.memdev=mem1,sgx-epc.1.node=1 \
......
Signed-off-by: Yang Zhong <yang.zhong@intel.com>
Message-Id: <20211101162009.62161-2-yang.zhong@intel.com>
Signed-off-by: Paolo Bonzini <pbonzini@redhat.com>
2021-11-01 17:20:05 +01:00
|
|
|
#
|
vl: Add sgx compound properties to expose SGX EPC sections to guest
Because SGX EPC is enumerated through CPUID, EPC "devices" need to be
realized prior to realizing the vCPUs themselves, i.e. long before
generic devices are parsed and realized. From a virtualization
perspective, the CPUID aspect also means that EPC sections cannot be
hotplugged without paravirtualizing the guest kernel (hardware does
not support hotplugging as EPC sections must be locked down during
pre-boot to provide EPC's security properties).
So even though EPC sections could be realized through the generic
-devices command, they need to be created much earlier for them to
actually be usable by the guest. Place all EPC sections in a
contiguous block, somewhat arbitrarily starting after RAM above 4g.
Ensuring EPC is in a contiguous region simplifies calculations, e.g.
device memory base, PCI hole, etc..., allows dynamic calculation of the
total EPC size, e.g. exposing EPC to guests does not require -maxmem,
and last but not least allows all of EPC to be enumerated in a single
ACPI entry, which is expected by some kernels, e.g. Windows 7 and 8.
The new compound properties command for sgx like below:
......
-object memory-backend-epc,id=mem1,size=28M,prealloc=on \
-object memory-backend-epc,id=mem2,size=10M \
-M sgx-epc.0.memdev=mem1,sgx-epc.1.memdev=mem2
Signed-off-by: Sean Christopherson <sean.j.christopherson@intel.com>
Signed-off-by: Yang Zhong <yang.zhong@intel.com>
Message-Id: <20210719112136.57018-6-yang.zhong@intel.com>
Signed-off-by: Paolo Bonzini <pbonzini@redhat.com>
2021-09-28 10:40:58 +02:00
|
|
|
# Since: 6.2
|
|
|
|
##
|
|
|
|
{ 'struct': 'SgxEPC',
|
numa: Enable numa for SGX EPC sections
The basic SGX did not enable numa for SGX EPC sections, which
result in all EPC sections located in numa node 0. This patch
enable SGX numa function in the guest and the EPC section can
work with RAM as one numa node.
The Guest kernel related log:
[ 0.009981] ACPI: SRAT: Node 0 PXM 0 [mem 0x180000000-0x183ffffff]
[ 0.009982] ACPI: SRAT: Node 1 PXM 1 [mem 0x184000000-0x185bfffff]
The SRAT table can normally show SGX EPC sections menory info in different
numa nodes.
The SGX EPC numa related command:
......
-m 4G,maxmem=20G \
-smp sockets=2,cores=2 \
-cpu host,+sgx-provisionkey \
-object memory-backend-ram,size=2G,host-nodes=0,policy=bind,id=node0 \
-object memory-backend-epc,id=mem0,size=64M,prealloc=on,host-nodes=0,policy=bind \
-numa node,nodeid=0,cpus=0-1,memdev=node0 \
-object memory-backend-ram,size=2G,host-nodes=1,policy=bind,id=node1 \
-object memory-backend-epc,id=mem1,size=28M,prealloc=on,host-nodes=1,policy=bind \
-numa node,nodeid=1,cpus=2-3,memdev=node1 \
-M sgx-epc.0.memdev=mem0,sgx-epc.0.node=0,sgx-epc.1.memdev=mem1,sgx-epc.1.node=1 \
......
Signed-off-by: Yang Zhong <yang.zhong@intel.com>
Message-Id: <20211101162009.62161-2-yang.zhong@intel.com>
Signed-off-by: Paolo Bonzini <pbonzini@redhat.com>
2021-11-01 17:20:05 +01:00
|
|
|
'data': { 'memdev': 'str',
|
|
|
|
'node': 'int'
|
|
|
|
}
|
|
|
|
}
|
vl: Add sgx compound properties to expose SGX EPC sections to guest
Because SGX EPC is enumerated through CPUID, EPC "devices" need to be
realized prior to realizing the vCPUs themselves, i.e. long before
generic devices are parsed and realized. From a virtualization
perspective, the CPUID aspect also means that EPC sections cannot be
hotplugged without paravirtualizing the guest kernel (hardware does
not support hotplugging as EPC sections must be locked down during
pre-boot to provide EPC's security properties).
So even though EPC sections could be realized through the generic
-devices command, they need to be created much earlier for them to
actually be usable by the guest. Place all EPC sections in a
contiguous block, somewhat arbitrarily starting after RAM above 4g.
Ensuring EPC is in a contiguous region simplifies calculations, e.g.
device memory base, PCI hole, etc..., allows dynamic calculation of the
total EPC size, e.g. exposing EPC to guests does not require -maxmem,
and last but not least allows all of EPC to be enumerated in a single
ACPI entry, which is expected by some kernels, e.g. Windows 7 and 8.
The new compound properties command for sgx like below:
......
-object memory-backend-epc,id=mem1,size=28M,prealloc=on \
-object memory-backend-epc,id=mem2,size=10M \
-M sgx-epc.0.memdev=mem1,sgx-epc.1.memdev=mem2
Signed-off-by: Sean Christopherson <sean.j.christopherson@intel.com>
Signed-off-by: Yang Zhong <yang.zhong@intel.com>
Message-Id: <20210719112136.57018-6-yang.zhong@intel.com>
Signed-off-by: Paolo Bonzini <pbonzini@redhat.com>
2021-09-28 10:40:58 +02:00
|
|
|
|
|
|
|
##
|
|
|
|
# @SgxEPCProperties:
|
|
|
|
#
|
|
|
|
# SGX properties of machine types.
|
|
|
|
#
|
|
|
|
# @sgx-epc: list of ids of memory-backend-epc objects.
|
|
|
|
#
|
|
|
|
# Since: 6.2
|
|
|
|
##
|
|
|
|
{ 'struct': 'SgxEPCProperties',
|
|
|
|
'data': { 'sgx-epc': ['SgxEPC'] }
|
|
|
|
}
|
|
|
|
|
2020-09-13 21:53:46 +02:00
|
|
|
##
|
|
|
|
# @query-memory-devices:
|
|
|
|
#
|
|
|
|
# Lists available memory devices and their state
|
|
|
|
#
|
|
|
|
# Since: 2.1
|
|
|
|
#
|
|
|
|
# Example:
|
|
|
|
#
|
|
|
|
# -> { "execute": "query-memory-devices" }
|
|
|
|
# <- { "return": [ { "data":
|
|
|
|
# { "addr": 5368709120,
|
|
|
|
# "hotpluggable": true,
|
|
|
|
# "hotplugged": true,
|
|
|
|
# "id": "d1",
|
|
|
|
# "memdev": "/objects/memX",
|
|
|
|
# "node": 0,
|
|
|
|
# "size": 1073741824,
|
|
|
|
# "slot": 0},
|
|
|
|
# "type": "dimm"
|
|
|
|
# } ] }
|
|
|
|
##
|
|
|
|
{ 'command': 'query-memory-devices', 'returns': ['MemoryDeviceInfo'] }
|
|
|
|
|
|
|
|
##
|
|
|
|
# @MEMORY_DEVICE_SIZE_CHANGE:
|
|
|
|
#
|
2023-04-28 12:54:29 +02:00
|
|
|
# Emitted when the size of a memory device changes. Only emitted for
|
|
|
|
# memory devices that can actually change the size (e.g., virtio-mem
|
|
|
|
# due to guest action).
|
2020-09-13 21:53:46 +02:00
|
|
|
#
|
|
|
|
# @id: device's ID
|
2021-09-29 18:24:44 +02:00
|
|
|
#
|
2020-09-13 21:53:46 +02:00
|
|
|
# @size: the new size of memory that the device provides
|
|
|
|
#
|
2021-09-29 18:24:44 +02:00
|
|
|
# @qom-path: path to the device object in the QOM tree (since 6.2)
|
|
|
|
#
|
2020-09-13 21:53:46 +02:00
|
|
|
# Note: this event is rate-limited.
|
|
|
|
#
|
|
|
|
# Since: 5.1
|
|
|
|
#
|
|
|
|
# Example:
|
|
|
|
#
|
|
|
|
# <- { "event": "MEMORY_DEVICE_SIZE_CHANGE",
|
2022-03-28 16:05:56 +02:00
|
|
|
# "data": { "id": "vm0", "size": 1073741824,
|
|
|
|
# "qom-path": "/machine/unattached/device[2]" },
|
2020-09-13 21:53:46 +02:00
|
|
|
# "timestamp": { "seconds": 1588168529, "microseconds": 201316 } }
|
|
|
|
##
|
|
|
|
{ 'event': 'MEMORY_DEVICE_SIZE_CHANGE',
|
2021-09-29 18:24:44 +02:00
|
|
|
'data': { '*id': 'str', 'size': 'size', 'qom-path' : 'str'} }
|
2020-09-13 21:53:46 +02:00
|
|
|
|
|
|
|
##
|
|
|
|
# @MEM_UNPLUG_ERROR:
|
|
|
|
#
|
|
|
|
# Emitted when memory hot unplug error occurs.
|
|
|
|
#
|
|
|
|
# @device: device name
|
|
|
|
#
|
|
|
|
# @msg: Informative message
|
|
|
|
#
|
2021-09-07 02:47:53 +02:00
|
|
|
# Features:
|
2023-04-28 12:54:29 +02:00
|
|
|
#
|
|
|
|
# @deprecated: This event is deprecated. Use
|
|
|
|
# @DEVICE_UNPLUG_GUEST_ERROR instead.
|
2021-09-07 02:47:53 +02:00
|
|
|
#
|
2020-09-13 21:53:46 +02:00
|
|
|
# Since: 2.4
|
|
|
|
#
|
|
|
|
# Example:
|
|
|
|
#
|
2022-09-01 10:58:37 +02:00
|
|
|
# <- { "event": "MEM_UNPLUG_ERROR",
|
2020-09-13 21:53:46 +02:00
|
|
|
# "data": { "device": "dimm1",
|
|
|
|
# "msg": "acpi: device unplug for unsupported device"
|
|
|
|
# },
|
|
|
|
# "timestamp": { "seconds": 1265044230, "microseconds": 450486 } }
|
|
|
|
##
|
|
|
|
{ 'event': 'MEM_UNPLUG_ERROR',
|
2021-09-07 02:47:53 +02:00
|
|
|
'data': { 'device': 'str', 'msg': 'str' },
|
|
|
|
'features': ['deprecated'] }
|
2021-06-17 17:53:06 +02:00
|
|
|
|
2022-04-14 18:52:56 +02:00
|
|
|
##
|
|
|
|
# @BootConfiguration:
|
|
|
|
#
|
|
|
|
# Schema for virtual machine boot configuration.
|
|
|
|
#
|
|
|
|
# @order: Boot order (a=floppy, c=hard disk, d=CD-ROM, n=network)
|
|
|
|
#
|
|
|
|
# @once: Boot order to apply on first boot
|
|
|
|
#
|
|
|
|
# @menu: Whether to show a boot menu
|
|
|
|
#
|
2023-04-28 12:54:29 +02:00
|
|
|
# @splash: The name of the file to be passed to the firmware as logo
|
|
|
|
# picture, if @menu is true.
|
2022-04-14 18:52:56 +02:00
|
|
|
#
|
|
|
|
# @splash-time: How long to show the logo picture, in milliseconds
|
|
|
|
#
|
|
|
|
# @reboot-timeout: Timeout before guest reboots after boot fails
|
|
|
|
#
|
2023-04-28 12:54:29 +02:00
|
|
|
# @strict: Whether to attempt booting from devices not included in the
|
|
|
|
# boot order
|
2022-04-14 18:52:56 +02:00
|
|
|
#
|
|
|
|
# Since: 7.1
|
|
|
|
##
|
|
|
|
{ 'struct': 'BootConfiguration', 'data': {
|
|
|
|
'*order': 'str',
|
|
|
|
'*once': 'str',
|
|
|
|
'*menu': 'bool',
|
|
|
|
'*splash': 'str',
|
|
|
|
'*splash-time': 'int',
|
|
|
|
'*reboot-timeout': 'int',
|
|
|
|
'*strict': 'bool' } }
|
|
|
|
|
2021-06-17 17:53:06 +02:00
|
|
|
##
|
|
|
|
# @SMPConfiguration:
|
|
|
|
#
|
2023-04-28 12:54:29 +02:00
|
|
|
# Schema for CPU topology configuration. A missing value lets QEMU
|
|
|
|
# figure out a suitable value based on the ones that are provided.
|
2021-06-17 17:53:06 +02:00
|
|
|
#
|
2023-10-16 20:39:05 +02:00
|
|
|
# The members other than @cpus and @maxcpus define a topology of
|
|
|
|
# containers.
|
2021-06-17 17:53:06 +02:00
|
|
|
#
|
2023-10-16 20:39:05 +02:00
|
|
|
# The ordering from highest/coarsest to lowest/finest is:
|
2023-10-16 20:39:06 +02:00
|
|
|
# @drawers, @books, @sockets, @dies, @clusters, @cores, @threads.
|
2021-06-17 17:53:06 +02:00
|
|
|
#
|
2023-10-16 20:39:05 +02:00
|
|
|
# Different architectures support different subsets of topology
|
|
|
|
# containers.
|
hw/core/machine: Introduce CPU cluster topology support
The new Cluster-Aware Scheduling support has landed in Linux 5.16,
which has been proved to benefit the scheduling performance (e.g.
load balance and wake_affine strategy) on both x86_64 and AArch64.
So now in Linux 5.16 we have four-level arch-neutral CPU topology
definition like below and a new scheduler level for clusters.
struct cpu_topology {
int thread_id;
int core_id;
int cluster_id;
int package_id;
int llc_id;
cpumask_t thread_sibling;
cpumask_t core_sibling;
cpumask_t cluster_sibling;
cpumask_t llc_sibling;
}
A cluster generally means a group of CPU cores which share L2 cache
or other mid-level resources, and it is the shared resources that
is used to improve scheduler's behavior. From the point of view of
the size range, it's between CPU die and CPU core. For example, on
some ARM64 Kunpeng servers, we have 6 clusters in each NUMA node,
and 4 CPU cores in each cluster. The 4 CPU cores share a separate
L2 cache and a L3 cache tag, which brings cache affinity advantage.
In virtualization, on the Hosts which have pClusters (physical
clusters), if we can design a vCPU topology with cluster level for
guest kernel and have a dedicated vCPU pinning. A Cluster-Aware
Guest kernel can also make use of the cache affinity of CPU clusters
to gain similar scheduling performance.
This patch adds infrastructure for CPU cluster level topology
configuration and parsing, so that the user can specify cluster
parameter if their machines support it.
Signed-off-by: Yanan Wang <wangyanan55@huawei.com>
Message-Id: <20211228092221.21068-3-wangyanan55@huawei.com>
Reviewed-by: Philippe Mathieu-Daudé <philmd@redhat.com>
[PMD: Added '(since 7.0)' to @clusters in qapi/machine.json]
Signed-off-by: Philippe Mathieu-Daudé <philmd@redhat.com>
2021-12-28 10:22:09 +01:00
|
|
|
#
|
2023-10-16 20:39:05 +02:00
|
|
|
# For example, s390x does not have clusters and dies, and the socket
|
|
|
|
# is the parent container of cores.
|
2021-06-17 17:53:06 +02:00
|
|
|
#
|
2023-10-16 20:39:05 +02:00
|
|
|
# @cpus: number of virtual CPUs in the virtual machine
|
2021-06-17 17:53:06 +02:00
|
|
|
#
|
2023-04-28 12:54:29 +02:00
|
|
|
# @maxcpus: maximum number of hotpluggable virtual CPUs in the virtual
|
|
|
|
# machine
|
2021-06-17 17:53:06 +02:00
|
|
|
#
|
2023-10-16 20:39:06 +02:00
|
|
|
# @drawers: number of drawers in the CPU topology (since 8.2)
|
|
|
|
#
|
|
|
|
# @books: number of books in the CPU topology (since 8.2)
|
|
|
|
#
|
|
|
|
# @sockets: number of sockets per parent container
|
2023-10-16 20:39:05 +02:00
|
|
|
#
|
|
|
|
# @dies: number of dies per parent container
|
|
|
|
#
|
|
|
|
# @clusters: number of clusters per parent container (since 7.0)
|
|
|
|
#
|
|
|
|
# @cores: number of cores per parent container
|
|
|
|
#
|
|
|
|
# @threads: number of threads per core
|
|
|
|
#
|
2021-06-17 17:53:06 +02:00
|
|
|
# Since: 6.1
|
|
|
|
##
|
|
|
|
{ 'struct': 'SMPConfiguration', 'data': {
|
|
|
|
'*cpus': 'int',
|
2023-10-16 20:39:06 +02:00
|
|
|
'*drawers': 'int',
|
|
|
|
'*books': 'int',
|
2021-06-17 17:53:06 +02:00
|
|
|
'*sockets': 'int',
|
|
|
|
'*dies': 'int',
|
hw/core/machine: Introduce CPU cluster topology support
The new Cluster-Aware Scheduling support has landed in Linux 5.16,
which has been proved to benefit the scheduling performance (e.g.
load balance and wake_affine strategy) on both x86_64 and AArch64.
So now in Linux 5.16 we have four-level arch-neutral CPU topology
definition like below and a new scheduler level for clusters.
struct cpu_topology {
int thread_id;
int core_id;
int cluster_id;
int package_id;
int llc_id;
cpumask_t thread_sibling;
cpumask_t core_sibling;
cpumask_t cluster_sibling;
cpumask_t llc_sibling;
}
A cluster generally means a group of CPU cores which share L2 cache
or other mid-level resources, and it is the shared resources that
is used to improve scheduler's behavior. From the point of view of
the size range, it's between CPU die and CPU core. For example, on
some ARM64 Kunpeng servers, we have 6 clusters in each NUMA node,
and 4 CPU cores in each cluster. The 4 CPU cores share a separate
L2 cache and a L3 cache tag, which brings cache affinity advantage.
In virtualization, on the Hosts which have pClusters (physical
clusters), if we can design a vCPU topology with cluster level for
guest kernel and have a dedicated vCPU pinning. A Cluster-Aware
Guest kernel can also make use of the cache affinity of CPU clusters
to gain similar scheduling performance.
This patch adds infrastructure for CPU cluster level topology
configuration and parsing, so that the user can specify cluster
parameter if their machines support it.
Signed-off-by: Yanan Wang <wangyanan55@huawei.com>
Message-Id: <20211228092221.21068-3-wangyanan55@huawei.com>
Reviewed-by: Philippe Mathieu-Daudé <philmd@redhat.com>
[PMD: Added '(since 7.0)' to @clusters in qapi/machine.json]
Signed-off-by: Philippe Mathieu-Daudé <philmd@redhat.com>
2021-12-28 10:22:09 +01:00
|
|
|
'*clusters': 'int',
|
2021-06-17 17:53:06 +02:00
|
|
|
'*cores': 'int',
|
|
|
|
'*threads': 'int',
|
|
|
|
'*maxcpus': 'int' } }
|
2021-09-08 11:35:43 +02:00
|
|
|
|
2021-09-08 11:35:43 +02:00
|
|
|
##
|
|
|
|
# @x-query-irq:
|
|
|
|
#
|
|
|
|
# Query interrupt statistics
|
|
|
|
#
|
2021-11-09 15:55:59 +01:00
|
|
|
# Features:
|
2023-04-28 12:54:29 +02:00
|
|
|
#
|
2021-11-09 15:55:59 +01:00
|
|
|
# @unstable: This command is meant for debugging.
|
|
|
|
#
|
2021-09-08 11:35:43 +02:00
|
|
|
# Returns: interrupt statistics
|
|
|
|
#
|
|
|
|
# Since: 6.2
|
|
|
|
##
|
|
|
|
{ 'command': 'x-query-irq',
|
2021-11-09 15:55:59 +01:00
|
|
|
'returns': 'HumanReadableText',
|
|
|
|
'features': [ 'unstable' ] }
|
2021-09-08 11:35:43 +02:00
|
|
|
|
2021-09-08 11:35:43 +02:00
|
|
|
##
|
|
|
|
# @x-query-jit:
|
|
|
|
#
|
|
|
|
# Query TCG compiler statistics
|
|
|
|
#
|
2021-11-09 15:55:59 +01:00
|
|
|
# Features:
|
2023-04-28 12:54:29 +02:00
|
|
|
#
|
2021-11-09 15:55:59 +01:00
|
|
|
# @unstable: This command is meant for debugging.
|
|
|
|
#
|
2021-09-08 11:35:43 +02:00
|
|
|
# Returns: TCG compiler statistics
|
|
|
|
#
|
|
|
|
# Since: 6.2
|
|
|
|
##
|
|
|
|
{ 'command': 'x-query-jit',
|
|
|
|
'returns': 'HumanReadableText',
|
2021-11-09 15:55:59 +01:00
|
|
|
'if': 'CONFIG_TCG',
|
|
|
|
'features': [ 'unstable' ] }
|
2021-09-08 11:35:43 +02:00
|
|
|
|
2021-09-08 11:35:43 +02:00
|
|
|
##
|
|
|
|
# @x-query-numa:
|
|
|
|
#
|
|
|
|
# Query NUMA topology information
|
|
|
|
#
|
2021-11-09 15:55:59 +01:00
|
|
|
# Features:
|
2023-04-28 12:54:29 +02:00
|
|
|
#
|
2021-11-09 15:55:59 +01:00
|
|
|
# @unstable: This command is meant for debugging.
|
|
|
|
#
|
2021-09-08 11:35:43 +02:00
|
|
|
# Returns: topology information
|
|
|
|
#
|
|
|
|
# Since: 6.2
|
|
|
|
##
|
|
|
|
{ 'command': 'x-query-numa',
|
2021-11-09 15:55:59 +01:00
|
|
|
'returns': 'HumanReadableText',
|
|
|
|
'features': [ 'unstable' ] }
|
2021-09-08 11:35:43 +02:00
|
|
|
|
2021-09-08 11:35:43 +02:00
|
|
|
##
|
|
|
|
# @x-query-opcount:
|
|
|
|
#
|
|
|
|
# Query TCG opcode counters
|
|
|
|
#
|
2021-11-09 15:55:59 +01:00
|
|
|
# Features:
|
2023-04-28 12:54:29 +02:00
|
|
|
#
|
2021-11-09 15:55:59 +01:00
|
|
|
# @unstable: This command is meant for debugging.
|
|
|
|
#
|
2021-09-08 11:35:43 +02:00
|
|
|
# Returns: TCG opcode counters
|
|
|
|
#
|
|
|
|
# Since: 6.2
|
|
|
|
##
|
|
|
|
{ 'command': 'x-query-opcount',
|
|
|
|
'returns': 'HumanReadableText',
|
2021-11-09 15:55:59 +01:00
|
|
|
'if': 'CONFIG_TCG',
|
|
|
|
'features': [ 'unstable' ] }
|
2021-09-08 11:35:43 +02:00
|
|
|
|
2021-09-08 11:35:43 +02:00
|
|
|
##
|
|
|
|
# @x-query-ramblock:
|
|
|
|
#
|
|
|
|
# Query system ramblock information
|
|
|
|
#
|
2021-11-09 15:55:59 +01:00
|
|
|
# Features:
|
2023-04-28 12:54:29 +02:00
|
|
|
#
|
2021-11-09 15:55:59 +01:00
|
|
|
# @unstable: This command is meant for debugging.
|
|
|
|
#
|
2021-09-08 11:35:43 +02:00
|
|
|
# Returns: system ramblock information
|
|
|
|
#
|
|
|
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# Since: 6.2
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##
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|
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|
{ 'command': 'x-query-ramblock',
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2021-11-09 15:55:59 +01:00
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'returns': 'HumanReadableText',
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'features': [ 'unstable' ] }
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2021-09-08 11:35:43 +02:00
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2021-09-08 11:35:43 +02:00
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##
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|
# @x-query-rdma:
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|
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|
#
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|
# Query RDMA state
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#
|
2021-11-09 15:55:59 +01:00
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# Features:
|
2023-04-28 12:54:29 +02:00
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|
#
|
2021-11-09 15:55:59 +01:00
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|
# @unstable: This command is meant for debugging.
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|
#
|
2021-09-08 11:35:43 +02:00
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# Returns: RDMA state
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|
#
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|
|
|
# Since: 6.2
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|
|
|
##
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|
|
{ 'command': 'x-query-rdma',
|
2021-11-09 15:55:59 +01:00
|
|
|
'returns': 'HumanReadableText',
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|
|
'features': [ 'unstable' ] }
|
2021-09-08 11:35:43 +02:00
|
|
|
|
2021-09-08 11:35:43 +02:00
|
|
|
##
|
|
|
|
# @x-query-roms:
|
|
|
|
#
|
|
|
|
# Query information on the registered ROMS
|
|
|
|
#
|
2021-11-09 15:55:59 +01:00
|
|
|
# Features:
|
2023-04-28 12:54:29 +02:00
|
|
|
#
|
2021-11-09 15:55:59 +01:00
|
|
|
# @unstable: This command is meant for debugging.
|
|
|
|
#
|
2021-09-08 11:35:43 +02:00
|
|
|
# Returns: registered ROMs
|
|
|
|
#
|
|
|
|
# Since: 6.2
|
|
|
|
##
|
|
|
|
{ 'command': 'x-query-roms',
|
2021-11-09 15:55:59 +01:00
|
|
|
'returns': 'HumanReadableText',
|
|
|
|
'features': [ 'unstable' ] }
|
2021-09-08 11:35:43 +02:00
|
|
|
|
|
|
|
##
|
|
|
|
# @x-query-usb:
|
|
|
|
#
|
|
|
|
# Query information on the USB devices
|
|
|
|
#
|
2021-11-09 15:55:59 +01:00
|
|
|
# Features:
|
2023-04-28 12:54:29 +02:00
|
|
|
#
|
2021-11-09 15:55:59 +01:00
|
|
|
# @unstable: This command is meant for debugging.
|
|
|
|
#
|
2021-09-08 11:35:43 +02:00
|
|
|
# Returns: USB device information
|
|
|
|
#
|
|
|
|
# Since: 6.2
|
|
|
|
##
|
|
|
|
{ 'command': 'x-query-usb',
|
2021-11-09 15:55:59 +01:00
|
|
|
'returns': 'HumanReadableText',
|
|
|
|
'features': [ 'unstable' ] }
|
2021-10-26 17:10:59 +02:00
|
|
|
|
|
|
|
##
|
|
|
|
# @SmbiosEntryPointType:
|
|
|
|
#
|
|
|
|
# @32: SMBIOS version 2.1 (32-bit) Entry Point
|
|
|
|
#
|
|
|
|
# @64: SMBIOS version 3.0 (64-bit) Entry Point
|
|
|
|
#
|
|
|
|
# Since: 7.0
|
|
|
|
##
|
|
|
|
{ 'enum': 'SmbiosEntryPointType',
|
|
|
|
'data': [ '32', '64' ] }
|
2022-04-14 18:52:58 +02:00
|
|
|
|
|
|
|
##
|
|
|
|
# @MemorySizeConfiguration:
|
|
|
|
#
|
|
|
|
# Schema for memory size configuration.
|
|
|
|
#
|
|
|
|
# @size: memory size in bytes
|
|
|
|
#
|
|
|
|
# @max-size: maximum hotpluggable memory size in bytes
|
|
|
|
#
|
|
|
|
# @slots: number of available memory slots for hotplug
|
|
|
|
#
|
|
|
|
# Since: 7.1
|
|
|
|
##
|
|
|
|
{ 'struct': 'MemorySizeConfiguration', 'data': {
|
|
|
|
'*size': 'size',
|
|
|
|
'*max-size': 'size',
|
|
|
|
'*slots': 'uint64' } }
|
2022-09-26 19:38:40 +02:00
|
|
|
|
|
|
|
##
|
|
|
|
# @dumpdtb:
|
|
|
|
#
|
|
|
|
# Save the FDT in dtb format.
|
|
|
|
#
|
|
|
|
# @filename: name of the dtb file to be created
|
|
|
|
#
|
|
|
|
# Since: 7.2
|
|
|
|
#
|
|
|
|
# Example:
|
2023-04-28 12:54:29 +02:00
|
|
|
#
|
2023-04-25 08:42:14 +02:00
|
|
|
# -> { "execute": "dumpdtb" }
|
|
|
|
# "arguments": { "filename": "fdt.dtb" } }
|
|
|
|
# <- { "return": {} }
|
2022-09-26 19:38:40 +02:00
|
|
|
##
|
|
|
|
{ 'command': 'dumpdtb',
|
|
|
|
'data': { 'filename': 'str' },
|
|
|
|
'if': 'CONFIG_FDT' }
|