hw/loongarch: Add support loongson3 virt machine type.

Emulate a 3A5000 board use the new loongarch instruction.
3A5000 belongs to the Loongson3 series processors.
The board consists of a 3A5000 cpu model and the virt
bridge. The host 3A5000 board is really complicated and
contains many functions.Now for the tcg softmmu mode
only part functions are emulated.

More detailed info you can see
https://github.com/loongson/LoongArch-Documentation

Signed-off-by: Xiaojuan Yang <yangxiaojuan@loongson.cn>
Signed-off-by: Song Gao <gaosong@loongson.cn>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Message-Id: <20220606124333.2060567-31-yangxiaojuan@loongson.cn>
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
master
Xiaojuan Yang 8 months ago committed by Richard Henderson
parent f9bf50745f
commit a8a506c390
  1. 4
      MAINTAINERS
  2. 3
      configs/devices/loongarch64-softmmu/default.mak
  3. 3
      configs/targets/loongarch64-softmmu.mak
  4. 1
      hw/Kconfig
  5. 4
      hw/loongarch/Kconfig
  6. 94
      hw/loongarch/loongson3.c
  7. 4
      hw/loongarch/meson.build
  8. 1
      hw/meson.build
  9. 2
      include/exec/poison.h
  10. 31
      include/hw/loongarch/virt.h
  11. 1
      include/sysemu/arch_init.h
  12. 2
      qapi/machine.json
  13. 1
      target/Kconfig
  14. 2
      target/loongarch/Kconfig
  15. 2
      target/loongarch/cpu.c

@ -1129,6 +1129,10 @@ M: Xiaojuan Yang <yangxiaojuan@loongson.cn>
M: Song Gao <gaosong@loongson.cn>
S: Maintained
F: docs/system/loongarch/loongson3.rst
F: configs/targets/loongarch64-softmmu.mak
F: configs/devices/loongarch64-softmmu/default.mak
F: hw/loongarch/
F: include/hw/loongarch/virt.h
M68K Machines
-------------

@ -0,0 +1,3 @@
# Default configuration for loongarch64-softmmu
CONFIG_LOONGARCH_VIRT=y

@ -0,0 +1,3 @@
TARGET_ARCH=loongarch64
TARGET_BASE_ARCH=loongarch
TARGET_SUPPORTS_MTTCG=y

@ -50,6 +50,7 @@ source avr/Kconfig
source cris/Kconfig
source hppa/Kconfig
source i386/Kconfig
source loongarch/Kconfig
source m68k/Kconfig
source microblaze/Kconfig
source mips/Kconfig

@ -0,0 +1,4 @@
config LOONGARCH_VIRT
bool
select PCI
select PCI_EXPRESS_GENERIC_BRIDGE

@ -0,0 +1,94 @@
/* SPDX-License-Identifier: GPL-2.0-or-later */
/*
* QEMU loongson 3a5000 develop board emulation
*
* Copyright (c) 2021 Loongson Technology Corporation Limited
*/
#include "qemu/osdep.h"
#include "qemu/units.h"
#include "qemu/datadir.h"
#include "qapi/error.h"
#include "hw/boards.h"
#include "sysemu/sysemu.h"
#include "sysemu/qtest.h"
#include "sysemu/runstate.h"
#include "sysemu/reset.h"
#include "sysemu/rtc.h"
#include "hw/loongarch/virt.h"
#include "exec/address-spaces.h"
#include "target/loongarch/cpu.h"
static void loongarch_init(MachineState *machine)
{
const char *cpu_model = machine->cpu_type;
ram_addr_t offset = 0;
ram_addr_t ram_size = machine->ram_size;
uint64_t highram_size = 0;
MemoryRegion *address_space_mem = get_system_memory();
LoongArchMachineState *lams = LOONGARCH_MACHINE(machine);
int i;
if (!cpu_model) {
cpu_model = LOONGARCH_CPU_TYPE_NAME("la464");
}
if (!strstr(cpu_model, "la464")) {
error_report("LoongArch/TCG needs cpu type la464");
exit(1);
}
if (ram_size < 1 * GiB) {
error_report("ram_size must be greater than 1G.");
exit(1);
}
/* Init CPUs */
for (i = 0; i < machine->smp.cpus; i++) {
cpu_create(machine->cpu_type);
}
/* Add memory region */
memory_region_init_alias(&lams->lowmem, NULL, "loongarch.lowram",
machine->ram, 0, 256 * MiB);
memory_region_add_subregion(address_space_mem, offset, &lams->lowmem);
offset += 256 * MiB;
highram_size = ram_size - 256 * MiB;
memory_region_init_alias(&lams->highmem, NULL, "loongarch.highmem",
machine->ram, offset, highram_size);
memory_region_add_subregion(address_space_mem, 0x90000000, &lams->highmem);
/* Add isa io region */
memory_region_init_alias(&lams->isa_io, NULL, "isa-io",
get_system_io(), 0, LOONGARCH_ISA_IO_SIZE);
memory_region_add_subregion(address_space_mem, LOONGARCH_ISA_IO_BASE,
&lams->isa_io);
}
static void loongarch_class_init(ObjectClass *oc, void *data)
{
MachineClass *mc = MACHINE_CLASS(oc);
mc->desc = "Loongson-3A5000 LS7A1000 machine";
mc->init = loongarch_init;
mc->default_ram_size = 1 * GiB;
mc->default_cpu_type = LOONGARCH_CPU_TYPE_NAME("la464");
mc->default_ram_id = "loongarch.ram";
mc->max_cpus = LOONGARCH_MAX_VCPUS;
mc->is_default = 1;
mc->default_kernel_irqchip_split = false;
mc->block_default_type = IF_VIRTIO;
mc->default_boot_order = "c";
mc->no_cdrom = 1;
}
static const TypeInfo loongarch_machine_types[] = {
{
.name = TYPE_LOONGARCH_MACHINE,
.parent = TYPE_MACHINE,
.instance_size = sizeof(LoongArchMachineState),
.class_init = loongarch_class_init,
}
};
DEFINE_TYPES(loongarch_machine_types)

@ -0,0 +1,4 @@
loongarch_ss = ss.source_set()
loongarch_ss.add(when: 'CONFIG_LOONGARCH_VIRT', if_true: files('loongson3.c'))
hw_arch += {'loongarch': loongarch_ss}

@ -50,6 +50,7 @@ subdir('avr')
subdir('cris')
subdir('hppa')
subdir('i386')
subdir('loongarch')
subdir('m68k')
subdir('microblaze')
subdir('mips')

@ -14,6 +14,7 @@
#pragma GCC poison TARGET_CRIS
#pragma GCC poison TARGET_HEXAGON
#pragma GCC poison TARGET_HPPA
#pragma GCC poison TARGET_LOONGARCH64
#pragma GCC poison TARGET_M68K
#pragma GCC poison TARGET_MICROBLAZE
#pragma GCC poison TARGET_MIPS
@ -71,6 +72,7 @@
#pragma GCC poison CONFIG_HPPA_DIS
#pragma GCC poison CONFIG_I386_DIS
#pragma GCC poison CONFIG_HEXAGON_DIS
#pragma GCC poison CONFIG_LOONGARCH_DIS
#pragma GCC poison CONFIG_M68K_DIS
#pragma GCC poison CONFIG_MICROBLAZE_DIS
#pragma GCC poison CONFIG_MIPS_DIS

@ -0,0 +1,31 @@
/* SPDX-License-Identifier: GPL-2.0-or-later */
/*
* Definitions for loongarch board emulation.
*
* Copyright (C) 2021 Loongson Technology Corporation Limited
*/
#ifndef HW_LOONGARCH_H
#define HW_LOONGARCH_H
#include "target/loongarch/cpu.h"
#include "hw/boards.h"
#include "qemu/queue.h"
#define LOONGARCH_MAX_VCPUS 4
#define LOONGARCH_ISA_IO_BASE 0x18000000UL
#define LOONGARCH_ISA_IO_SIZE 0x0004000
struct LoongArchMachineState {
/*< private >*/
MachineState parent_obj;
MemoryRegion lowmem;
MemoryRegion highmem;
MemoryRegion isa_io;
};
#define TYPE_LOONGARCH_MACHINE MACHINE_TYPE_NAME("virt")
OBJECT_DECLARE_SIMPLE_TYPE(LoongArchMachineState, LOONGARCH_MACHINE)
#endif

@ -24,6 +24,7 @@ enum {
QEMU_ARCH_RX = (1 << 20),
QEMU_ARCH_AVR = (1 << 21),
QEMU_ARCH_HEXAGON = (1 << 22),
QEMU_ARCH_LOONGARCH = (1 << 23),
};
extern const uint32_t arch_type;

@ -30,7 +30,7 @@
##
{ 'enum' : 'SysEmuTarget',
'data' : [ 'aarch64', 'alpha', 'arm', 'avr', 'cris', 'hppa', 'i386',
'm68k', 'microblaze', 'microblazeel', 'mips', 'mips64',
'loongarch64', 'm68k', 'microblaze', 'microblazeel', 'mips', 'mips64',
'mips64el', 'mipsel', 'nios2', 'or1k', 'ppc',
'ppc64', 'riscv32', 'riscv64', 'rx', 's390x', 'sh4',
'sh4eb', 'sparc', 'sparc64', 'tricore',

@ -4,6 +4,7 @@ source avr/Kconfig
source cris/Kconfig
source hppa/Kconfig
source i386/Kconfig
source loongarch/Kconfig
source m68k/Kconfig
source microblaze/Kconfig
source mips/Kconfig

@ -0,0 +1,2 @@
config LOONGARCH64
bool

@ -82,6 +82,8 @@ static void loongarch_cpu_set_pc(CPUState *cs, vaddr value)
env->pc = value;
}
#include "hw/loongarch/virt.h"
void loongarch_cpu_set_irq(void *opaque, int irq, int level)
{
LoongArchCPU *cpu = opaque;

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