2012-09-02 16:52:59 +02:00
|
|
|
DEF_HELPER_3(raise_exception_err, noreturn, env, i32, int)
|
|
|
|
|
DEF_HELPER_2(raise_exception, noreturn, env, i32)
|
2015-07-10 11:57:08 +02:00
|
|
|
DEF_HELPER_1(raise_exception_debug, noreturn, env)
|
2008-06-08 09:42:23 +02:00
|
|
|
|
2008-06-20 17:12:14 +02:00
|
|
|
#ifdef TARGET_MIPS64
|
2012-09-02 16:52:59 +02:00
|
|
|
DEF_HELPER_4(sdl, void, env, tl, tl, int)
|
|
|
|
|
DEF_HELPER_4(sdr, void, env, tl, tl, int)
|
2008-06-20 17:12:14 +02:00
|
|
|
#endif
|
2012-09-02 16:52:59 +02:00
|
|
|
DEF_HELPER_4(swl, void, env, tl, tl, int)
|
|
|
|
|
DEF_HELPER_4(swr, void, env, tl, tl, int)
|
2008-06-20 17:12:14 +02:00
|
|
|
|
2009-11-30 15:39:54 +01:00
|
|
|
#ifndef CONFIG_USER_ONLY
|
2012-09-02 16:52:59 +02:00
|
|
|
DEF_HELPER_3(ll, tl, env, tl, int)
|
2009-11-30 15:39:54 +01:00
|
|
|
#ifdef TARGET_MIPS64
|
2012-09-02 16:52:59 +02:00
|
|
|
DEF_HELPER_3(lld, tl, env, tl, int)
|
2009-11-30 15:39:54 +01:00
|
|
|
#endif
|
|
|
|
|
#endif
|
|
|
|
|
|
2014-06-27 09:49:05 +02:00
|
|
|
DEF_HELPER_FLAGS_1(bitswap, TCG_CALL_NO_RWG_SE, tl, tl)
|
|
|
|
|
#ifdef TARGET_MIPS64
|
|
|
|
|
DEF_HELPER_FLAGS_1(dbitswap, TCG_CALL_NO_RWG_SE, tl, tl)
|
|
|
|
|
#endif
|
|
|
|
|
|
2018-08-02 16:16:20 +02:00
|
|
|
DEF_HELPER_FLAGS_4(rotx, TCG_CALL_NO_RWG_SE, tl, tl, i32, i32, i32)
|
|
|
|
|
|
2010-06-08 22:29:59 +02:00
|
|
|
/* microMIPS functions */
|
2013-09-15 00:38:30 +02:00
|
|
|
DEF_HELPER_4(lwm, void, env, tl, tl, i32)
|
|
|
|
|
DEF_HELPER_4(swm, void, env, tl, tl, i32)
|
2010-06-08 22:29:59 +02:00
|
|
|
#ifdef TARGET_MIPS64
|
2013-09-15 00:38:30 +02:00
|
|
|
DEF_HELPER_4(ldm, void, env, tl, tl, i32)
|
|
|
|
|
DEF_HELPER_4(sdm, void, env, tl, tl, i32)
|
2010-06-08 22:29:59 +02:00
|
|
|
#endif
|
|
|
|
|
|
2008-11-17 15:43:54 +01:00
|
|
|
DEF_HELPER_2(fork, void, tl, tl)
|
2012-09-02 16:52:59 +02:00
|
|
|
DEF_HELPER_2(yield, tl, env, tl)
|
2008-06-09 09:13:38 +02:00
|
|
|
|
|
|
|
|
/* CP1 functions */
|
2012-09-02 16:52:59 +02:00
|
|
|
DEF_HELPER_2(cfc1, tl, env, i32)
|
2014-01-22 18:35:32 +01:00
|
|
|
DEF_HELPER_4(ctc1, void, env, tl, i32, i32)
|
2008-06-11 17:27:54 +02:00
|
|
|
|
2012-09-02 16:52:59 +02:00
|
|
|
DEF_HELPER_2(float_cvtd_s, i64, env, i32)
|
|
|
|
|
DEF_HELPER_2(float_cvtd_w, i64, env, i32)
|
|
|
|
|
DEF_HELPER_2(float_cvtd_l, i64, env, i64)
|
|
|
|
|
DEF_HELPER_2(float_cvtps_pw, i64, env, i64)
|
|
|
|
|
DEF_HELPER_2(float_cvtpw_ps, i64, env, i64)
|
|
|
|
|
DEF_HELPER_2(float_cvts_d, i32, env, i64)
|
|
|
|
|
DEF_HELPER_2(float_cvts_w, i32, env, i32)
|
|
|
|
|
DEF_HELPER_2(float_cvts_l, i32, env, i64)
|
|
|
|
|
DEF_HELPER_2(float_cvts_pl, i32, env, i32)
|
|
|
|
|
DEF_HELPER_2(float_cvts_pu, i32, env, i32)
|
2008-07-09 13:05:10 +02:00
|
|
|
|
2012-09-02 16:52:59 +02:00
|
|
|
DEF_HELPER_3(float_addr_ps, i64, env, i64, i64)
|
|
|
|
|
DEF_HELPER_3(float_mulr_ps, i64, env, i64, i64)
|
2008-07-09 13:05:10 +02:00
|
|
|
|
softfloat: Implement run-time-configurable meaning of signaling NaN bit
This patch modifies SoftFloat library so that it can be configured in
run-time in relation to the meaning of signaling NaN bit, while, at the
same time, strictly preserving its behavior on all existing platforms.
Background:
In floating-point calculations, there is a need for denoting undefined or
unrepresentable values. This is achieved by defining certain floating-point
numerical values to be NaNs (which stands for "not a number"). For additional
reasons, virtually all modern floating-point unit implementations use two
kinds of NaNs: quiet and signaling. The binary representations of these two
kinds of NaNs, as a rule, differ only in one bit (that bit is, traditionally,
the first bit of mantissa).
Up to 2008, standards for floating-point did not specify all details about
binary representation of NaNs. More specifically, the meaning of the bit
that is used for distinguishing between signaling and quiet NaNs was not
strictly prescribed. (IEEE 754-2008 was the first floating-point standard
that defined that meaning clearly, see [1], p. 35) As a result, different
platforms took different approaches, and that presented considerable
challenge for multi-platform emulators like QEMU.
Mips platform represents the most complex case among QEMU-supported
platforms regarding signaling NaN bit. Up to the Release 6 of Mips
architecture, "1" in signaling NaN bit denoted signaling NaN, which is
opposite to IEEE 754-2008 standard. From Release 6 on, Mips architecture
adopted IEEE standard prescription, and "0" denotes signaling NaN. On top of
that, Mips architecture for SIMD (also known as MSA, or vector instructions)
also specifies signaling bit in accordance to IEEE standard. MSA unit can be
implemented with both pre-Release 6 and Release 6 main processor units.
QEMU uses SoftFloat library to implement various floating-point-related
instructions on all platforms. The current QEMU implementation allows for
defining meaning of signaling NaN bit during build time, and is implemented
via preprocessor macro called SNAN_BIT_IS_ONE.
On the other hand, the change in this patch enables SoftFloat library to be
configured in run-time. This configuration is meant to occur during CPU
initialization, at the moment when it is definitely known what desired
behavior for particular CPU (or any additional FPUs) is.
The change is implemented so that it is consistent with existing
implementation of similar cases. This means that structure float_status is
used for passing the information about desired signaling NaN bit on each
invocation of SoftFloat functions. The additional field in float_status is
called snan_bit_is_one, which supersedes macro SNAN_BIT_IS_ONE.
IMPORTANT:
This change is not meant to create any change in emulator behavior or
functionality on any platform. It just provides the means for SoftFloat
library to be used in a more flexible way - in other words, it will just
prepare SoftFloat library for usage related to Mips platform and its
specifics regarding signaling bit meaning, which is done in some of
subsequent patches from this series.
Further break down of changes:
1) Added field snan_bit_is_one to the structure float_status, and
correspondent setter function set_snan_bit_is_one().
2) Constants <float16|float32|float64|floatx80|float128>_default_nan
(used both internally and externally) converted to functions
<float16|float32|float64|floatx80|float128>_default_nan(float_status*).
This is necessary since they are dependent on signaling bit meaning.
At the same time, for the sake of code cleanup and simplicity, constants
<floatx80|float128>_default_nan_<low|high> (used only internally within
SoftFloat library) are removed, as not needed.
3) Added a float_status* argument to SoftFloat library functions
XXX_is_quiet_nan(XXX a_), XXX_is_signaling_nan(XXX a_),
XXX_maybe_silence_nan(XXX a_). This argument must be present in
order to enable correct invocation of new version of functions
XXX_default_nan(). (XXX is <float16|float32|float64|floatx80|float128>
here)
4) Updated code for all platforms to reflect changes in SoftFloat library.
This change is twofolds: it includes modifications of SoftFloat library
functions invocations, and an addition of invocation of function
set_snan_bit_is_one() during CPU initialization, with arguments that
are appropriate for each particular platform. It was established that
all platforms zero their main CPU data structures, so snan_bit_is_one(0)
in appropriate places is not added, as it is not needed.
[1] "IEEE Standard for Floating-Point Arithmetic",
IEEE Computer Society, August 29, 2008.
Signed-off-by: Thomas Schwinge <thomas@codesourcery.com>
Signed-off-by: Maciej W. Rozycki <macro@codesourcery.com>
Signed-off-by: Aleksandar Markovic <aleksandar.markovic@imgtec.com>
Tested-by: Bastian Koppelmann <kbastian@mail.uni-paderborn.de>
Reviewed-by: Leon Alrae <leon.alrae@imgtec.com>
Tested-by: Leon Alrae <leon.alrae@imgtec.com>
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
[leon.alrae@imgtec.com:
* cherry-picked 2 chunks from patch #2 to fix compilation warnings]
Signed-off-by: Leon Alrae <leon.alrae@imgtec.com>
2016-06-10 11:57:28 +02:00
|
|
|
DEF_HELPER_FLAGS_2(float_class_s, TCG_CALL_NO_RWG_SE, i32, env, i32)
|
|
|
|
|
DEF_HELPER_FLAGS_2(float_class_d, TCG_CALL_NO_RWG_SE, i64, env, i64)
|
2014-06-27 09:49:07 +02:00
|
|
|
|
|
|
|
|
#define FOP_PROTO(op) \
|
|
|
|
|
DEF_HELPER_4(float_ ## op ## _s, i32, env, i32, i32, i32) \
|
|
|
|
|
DEF_HELPER_4(float_ ## op ## _d, i64, env, i64, i64, i64)
|
|
|
|
|
FOP_PROTO(maddf)
|
|
|
|
|
FOP_PROTO(msubf)
|
|
|
|
|
#undef FOP_PROTO
|
|
|
|
|
|
|
|
|
|
#define FOP_PROTO(op) \
|
|
|
|
|
DEF_HELPER_3(float_ ## op ## _s, i32, env, i32, i32) \
|
|
|
|
|
DEF_HELPER_3(float_ ## op ## _d, i64, env, i64, i64)
|
|
|
|
|
FOP_PROTO(max)
|
|
|
|
|
FOP_PROTO(maxa)
|
|
|
|
|
FOP_PROTO(min)
|
|
|
|
|
FOP_PROTO(mina)
|
|
|
|
|
#undef FOP_PROTO
|
|
|
|
|
|
2012-09-02 16:52:59 +02:00
|
|
|
#define FOP_PROTO(op) \
|
target-mips: Add nan2008 flavor of <CEIL|CVT|FLOOR|ROUND|TRUNC>.<L|W>.<S|D>
New set of helpers for handling nan2008-syle versions of instructions
<CEIL|CVT|FLOOR|ROUND|TRUNC>.<L|W>.<S|D>, for Mips R6.
All involved instructions have float operand and integer result. Their
core functionality is implemented via invocations of appropriate SoftFloat
functions. The problematic cases are when the operand is a NaN, and also
when the operand (float) is out of the range of the result.
Here one can distinguish three cases:
CASE MIPS-A: (FCR31.NAN2008 == 1)
1. Operand is a NaN, result should be 0;
2. Operand is larger than INT_MAX, result should be INT_MAX;
3. Operand is smaller than INT_MIN, result should be INT_MIN.
CASE MIPS-B: (FCR31.NAN2008 == 0)
1. Operand is a NaN, result should be INT_MAX;
2. Operand is larger than INT_MAX, result should be INT_MAX;
3. Operand is smaller than INT_MIN, result should be INT_MAX.
CASE SoftFloat:
1. Operand is a NaN, result is INT_MAX;
2. Operand is larger than INT_MAX, result is INT_MAX;
3. Operand is smaller than INT_MIN, result is INT_MIN.
Current implementation of <CEIL|CVT|FLOOR|ROUND|TRUNC>.<L|W>.<S|D>
implements case MIPS-B. This patch relates to case MIPS-A. For case
MIPS-A, only return value for NaN-operands should be corrected after
appropriate SoftFloat library function is called.
Related MSA instructions FTRUNC_S and FTINT_S already handle well
all cases, in the fashion similar to the code from this patch.
Signed-off-by: Aleksandar Markovic <aleksandar.markovic@imgtec.com>
Reviewed-by: Leon Alrae <leon.alrae@imgtec.com>
[leon.alrae@imgtec.com:
* removed a statement from the description which caused slight confusion]
Signed-off-by: Leon Alrae <leon.alrae@imgtec.com>
2016-06-10 11:57:35 +02:00
|
|
|
DEF_HELPER_2(float_ ## op ## _l_s, i64, env, i32) \
|
|
|
|
|
DEF_HELPER_2(float_ ## op ## _l_d, i64, env, i64) \
|
|
|
|
|
DEF_HELPER_2(float_ ## op ## _w_s, i32, env, i32) \
|
|
|
|
|
DEF_HELPER_2(float_ ## op ## _w_d, i32, env, i64)
|
|
|
|
|
FOP_PROTO(cvt)
|
2008-07-09 13:05:10 +02:00
|
|
|
FOP_PROTO(round)
|
|
|
|
|
FOP_PROTO(trunc)
|
|
|
|
|
FOP_PROTO(ceil)
|
|
|
|
|
FOP_PROTO(floor)
|
target-mips: Add nan2008 flavor of <CEIL|CVT|FLOOR|ROUND|TRUNC>.<L|W>.<S|D>
New set of helpers for handling nan2008-syle versions of instructions
<CEIL|CVT|FLOOR|ROUND|TRUNC>.<L|W>.<S|D>, for Mips R6.
All involved instructions have float operand and integer result. Their
core functionality is implemented via invocations of appropriate SoftFloat
functions. The problematic cases are when the operand is a NaN, and also
when the operand (float) is out of the range of the result.
Here one can distinguish three cases:
CASE MIPS-A: (FCR31.NAN2008 == 1)
1. Operand is a NaN, result should be 0;
2. Operand is larger than INT_MAX, result should be INT_MAX;
3. Operand is smaller than INT_MIN, result should be INT_MIN.
CASE MIPS-B: (FCR31.NAN2008 == 0)
1. Operand is a NaN, result should be INT_MAX;
2. Operand is larger than INT_MAX, result should be INT_MAX;
3. Operand is smaller than INT_MIN, result should be INT_MAX.
CASE SoftFloat:
1. Operand is a NaN, result is INT_MAX;
2. Operand is larger than INT_MAX, result is INT_MAX;
3. Operand is smaller than INT_MIN, result is INT_MIN.
Current implementation of <CEIL|CVT|FLOOR|ROUND|TRUNC>.<L|W>.<S|D>
implements case MIPS-B. This patch relates to case MIPS-A. For case
MIPS-A, only return value for NaN-operands should be corrected after
appropriate SoftFloat library function is called.
Related MSA instructions FTRUNC_S and FTINT_S already handle well
all cases, in the fashion similar to the code from this patch.
Signed-off-by: Aleksandar Markovic <aleksandar.markovic@imgtec.com>
Reviewed-by: Leon Alrae <leon.alrae@imgtec.com>
[leon.alrae@imgtec.com:
* removed a statement from the description which caused slight confusion]
Signed-off-by: Leon Alrae <leon.alrae@imgtec.com>
2016-06-10 11:57:35 +02:00
|
|
|
FOP_PROTO(cvt_2008)
|
|
|
|
|
FOP_PROTO(round_2008)
|
|
|
|
|
FOP_PROTO(trunc_2008)
|
|
|
|
|
FOP_PROTO(ceil_2008)
|
|
|
|
|
FOP_PROTO(floor_2008)
|
2008-07-09 13:05:10 +02:00
|
|
|
#undef FOP_PROTO
|
|
|
|
|
|
2012-09-02 16:52:59 +02:00
|
|
|
#define FOP_PROTO(op) \
|
|
|
|
|
DEF_HELPER_2(float_ ## op ## _s, i32, env, i32) \
|
|
|
|
|
DEF_HELPER_2(float_ ## op ## _d, i64, env, i64)
|
2008-06-19 20:35:02 +02:00
|
|
|
FOP_PROTO(sqrt)
|
2008-06-11 17:27:54 +02:00
|
|
|
FOP_PROTO(rsqrt)
|
|
|
|
|
FOP_PROTO(recip)
|
2014-06-27 09:49:07 +02:00
|
|
|
FOP_PROTO(rint)
|
2008-06-11 17:27:54 +02:00
|
|
|
#undef FOP_PROTO
|
|
|
|
|
|
2008-11-17 15:43:54 +01:00
|
|
|
#define FOP_PROTO(op) \
|
|
|
|
|
DEF_HELPER_1(float_ ## op ## _s, i32, i32) \
|
|
|
|
|
DEF_HELPER_1(float_ ## op ## _d, i64, i64) \
|
|
|
|
|
DEF_HELPER_1(float_ ## op ## _ps, i64, i64)
|
2008-07-09 13:05:10 +02:00
|
|
|
FOP_PROTO(abs)
|
|
|
|
|
FOP_PROTO(chs)
|
2012-09-02 16:52:59 +02:00
|
|
|
#undef FOP_PROTO
|
|
|
|
|
|
|
|
|
|
#define FOP_PROTO(op) \
|
|
|
|
|
DEF_HELPER_2(float_ ## op ## _s, i32, env, i32) \
|
|
|
|
|
DEF_HELPER_2(float_ ## op ## _d, i64, env, i64) \
|
|
|
|
|
DEF_HELPER_2(float_ ## op ## _ps, i64, env, i64)
|
2008-07-09 13:05:10 +02:00
|
|
|
FOP_PROTO(recip1)
|
|
|
|
|
FOP_PROTO(rsqrt1)
|
|
|
|
|
#undef FOP_PROTO
|
|
|
|
|
|
2012-09-02 16:52:59 +02:00
|
|
|
#define FOP_PROTO(op) \
|
|
|
|
|
DEF_HELPER_3(float_ ## op ## _s, i32, env, i32, i32) \
|
|
|
|
|
DEF_HELPER_3(float_ ## op ## _d, i64, env, i64, i64) \
|
|
|
|
|
DEF_HELPER_3(float_ ## op ## _ps, i64, env, i64, i64)
|
2008-06-11 17:27:54 +02:00
|
|
|
FOP_PROTO(add)
|
|
|
|
|
FOP_PROTO(sub)
|
|
|
|
|
FOP_PROTO(mul)
|
|
|
|
|
FOP_PROTO(div)
|
2008-07-09 13:05:10 +02:00
|
|
|
FOP_PROTO(recip2)
|
|
|
|
|
FOP_PROTO(rsqrt2)
|
|
|
|
|
#undef FOP_PROTO
|
|
|
|
|
|
2012-09-02 16:52:59 +02:00
|
|
|
#define FOP_PROTO(op) \
|
|
|
|
|
DEF_HELPER_4(float_ ## op ## _s, i32, env, i32, i32, i32) \
|
|
|
|
|
DEF_HELPER_4(float_ ## op ## _d, i64, env, i64, i64, i64) \
|
|
|
|
|
DEF_HELPER_4(float_ ## op ## _ps, i64, env, i64, i64, i64)
|
2012-10-09 21:53:20 +02:00
|
|
|
FOP_PROTO(madd)
|
|
|
|
|
FOP_PROTO(msub)
|
|
|
|
|
FOP_PROTO(nmadd)
|
|
|
|
|
FOP_PROTO(nmsub)
|
2008-06-11 17:27:54 +02:00
|
|
|
#undef FOP_PROTO
|
|
|
|
|
|
2012-09-02 16:52:59 +02:00
|
|
|
#define FOP_PROTO(op) \
|
|
|
|
|
DEF_HELPER_4(cmp_d_ ## op, void, env, i64, i64, int) \
|
|
|
|
|
DEF_HELPER_4(cmpabs_d_ ## op, void, env, i64, i64, int) \
|
|
|
|
|
DEF_HELPER_4(cmp_s_ ## op, void, env, i32, i32, int) \
|
|
|
|
|
DEF_HELPER_4(cmpabs_s_ ## op, void, env, i32, i32, int) \
|
|
|
|
|
DEF_HELPER_4(cmp_ps_ ## op, void, env, i64, i64, int) \
|
|
|
|
|
DEF_HELPER_4(cmpabs_ps_ ## op, void, env, i64, i64, int)
|
2008-06-11 17:27:54 +02:00
|
|
|
FOP_PROTO(f)
|
|
|
|
|
FOP_PROTO(un)
|
|
|
|
|
FOP_PROTO(eq)
|
|
|
|
|
FOP_PROTO(ueq)
|
|
|
|
|
FOP_PROTO(olt)
|
|
|
|
|
FOP_PROTO(ult)
|
|
|
|
|
FOP_PROTO(ole)
|
|
|
|
|
FOP_PROTO(ule)
|
|
|
|
|
FOP_PROTO(sf)
|
|
|
|
|
FOP_PROTO(ngle)
|
|
|
|
|
FOP_PROTO(seq)
|
|
|
|
|
FOP_PROTO(ngl)
|
|
|
|
|
FOP_PROTO(lt)
|
|
|
|
|
FOP_PROTO(nge)
|
|
|
|
|
FOP_PROTO(le)
|
|
|
|
|
FOP_PROTO(ngt)
|
|
|
|
|
#undef FOP_PROTO
|
2008-06-12 05:15:13 +02:00
|
|
|
|
2014-06-27 09:49:07 +02:00
|
|
|
#define FOP_PROTO(op) \
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DEF_HELPER_3(r6_cmp_d_ ## op, i64, env, i64, i64) \
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DEF_HELPER_3(r6_cmp_s_ ## op, i32, env, i32, i32)
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FOP_PROTO(af)
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FOP_PROTO(un)
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FOP_PROTO(eq)
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FOP_PROTO(ueq)
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FOP_PROTO(lt)
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FOP_PROTO(ult)
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FOP_PROTO(le)
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FOP_PROTO(ule)
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FOP_PROTO(saf)
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FOP_PROTO(sun)
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FOP_PROTO(seq)
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FOP_PROTO(sueq)
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FOP_PROTO(slt)
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FOP_PROTO(sult)
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FOP_PROTO(sle)
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FOP_PROTO(sule)
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FOP_PROTO(or)
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FOP_PROTO(une)
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FOP_PROTO(ne)
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FOP_PROTO(sor)
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FOP_PROTO(sune)
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FOP_PROTO(sne)
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#undef FOP_PROTO
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2012-09-02 16:52:59 +02:00
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DEF_HELPER_1(rdhwr_cpunum, tl, env)
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DEF_HELPER_1(rdhwr_synci_step, tl, env)
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DEF_HELPER_1(rdhwr_cc, tl, env)
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DEF_HELPER_1(rdhwr_ccres, tl, env)
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2015-10-29 16:18:39 +01:00
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DEF_HELPER_1(rdhwr_performance, tl, env)
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DEF_HELPER_1(rdhwr_xnp, tl, env)
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2012-09-02 16:52:59 +02:00
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DEF_HELPER_2(pmon, void, env, int)
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DEF_HELPER_1(wait, void, env)
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2008-11-17 15:43:54 +01:00
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2023-05-21 20:01:46 +02:00
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#ifdef TARGET_MIPS64
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DEF_HELPER_FLAGS_2(lcsr_cpucfg, TCG_CALL_NO_RWG_SE, tl, env, tl)
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#endif
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2012-09-19 06:59:44 +02:00
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/* Loongson multimedia functions. */
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2012-10-09 21:53:09 +02:00
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DEF_HELPER_FLAGS_2(paddsh, TCG_CALL_NO_RWG_SE, i64, i64, i64)
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DEF_HELPER_FLAGS_2(paddush, TCG_CALL_NO_RWG_SE, i64, i64, i64)
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DEF_HELPER_FLAGS_2(paddh, TCG_CALL_NO_RWG_SE, i64, i64, i64)
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DEF_HELPER_FLAGS_2(paddw, TCG_CALL_NO_RWG_SE, i64, i64, i64)
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DEF_HELPER_FLAGS_2(paddsb, TCG_CALL_NO_RWG_SE, i64, i64, i64)
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DEF_HELPER_FLAGS_2(paddusb, TCG_CALL_NO_RWG_SE, i64, i64, i64)
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DEF_HELPER_FLAGS_2(paddb, TCG_CALL_NO_RWG_SE, i64, i64, i64)
|
2012-09-19 06:59:44 +02:00
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2012-10-09 21:53:09 +02:00
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DEF_HELPER_FLAGS_2(psubsh, TCG_CALL_NO_RWG_SE, i64, i64, i64)
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DEF_HELPER_FLAGS_2(psubush, TCG_CALL_NO_RWG_SE, i64, i64, i64)
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DEF_HELPER_FLAGS_2(psubh, TCG_CALL_NO_RWG_SE, i64, i64, i64)
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DEF_HELPER_FLAGS_2(psubw, TCG_CALL_NO_RWG_SE, i64, i64, i64)
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DEF_HELPER_FLAGS_2(psubsb, TCG_CALL_NO_RWG_SE, i64, i64, i64)
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DEF_HELPER_FLAGS_2(psubusb, TCG_CALL_NO_RWG_SE, i64, i64, i64)
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DEF_HELPER_FLAGS_2(psubb, TCG_CALL_NO_RWG_SE, i64, i64, i64)
|
2012-09-19 06:59:44 +02:00
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2012-10-09 21:53:09 +02:00
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DEF_HELPER_FLAGS_2(pshufh, TCG_CALL_NO_RWG_SE, i64, i64, i64)
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DEF_HELPER_FLAGS_2(packsswh, TCG_CALL_NO_RWG_SE, i64, i64, i64)
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DEF_HELPER_FLAGS_2(packsshb, TCG_CALL_NO_RWG_SE, i64, i64, i64)
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DEF_HELPER_FLAGS_2(packushb, TCG_CALL_NO_RWG_SE, i64, i64, i64)
|
2012-09-19 06:59:44 +02:00
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|
2012-10-09 21:53:09 +02:00
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|
DEF_HELPER_FLAGS_2(punpcklhw, TCG_CALL_NO_RWG_SE, i64, i64, i64)
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DEF_HELPER_FLAGS_2(punpckhhw, TCG_CALL_NO_RWG_SE, i64, i64, i64)
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DEF_HELPER_FLAGS_2(punpcklbh, TCG_CALL_NO_RWG_SE, i64, i64, i64)
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DEF_HELPER_FLAGS_2(punpckhbh, TCG_CALL_NO_RWG_SE, i64, i64, i64)
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DEF_HELPER_FLAGS_2(punpcklwd, TCG_CALL_NO_RWG_SE, i64, i64, i64)
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DEF_HELPER_FLAGS_2(punpckhwd, TCG_CALL_NO_RWG_SE, i64, i64, i64)
|
2012-09-19 06:59:44 +02:00
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|
2012-10-09 21:53:09 +02:00
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|
DEF_HELPER_FLAGS_2(pavgh, TCG_CALL_NO_RWG_SE, i64, i64, i64)
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|
DEF_HELPER_FLAGS_2(pavgb, TCG_CALL_NO_RWG_SE, i64, i64, i64)
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|
DEF_HELPER_FLAGS_2(pmaxsh, TCG_CALL_NO_RWG_SE, i64, i64, i64)
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DEF_HELPER_FLAGS_2(pminsh, TCG_CALL_NO_RWG_SE, i64, i64, i64)
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DEF_HELPER_FLAGS_2(pmaxub, TCG_CALL_NO_RWG_SE, i64, i64, i64)
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|
DEF_HELPER_FLAGS_2(pminub, TCG_CALL_NO_RWG_SE, i64, i64, i64)
|
2012-09-19 06:59:44 +02:00
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|
2012-10-09 21:53:09 +02:00
|
|
|
DEF_HELPER_FLAGS_2(pcmpeqw, TCG_CALL_NO_RWG_SE, i64, i64, i64)
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|
DEF_HELPER_FLAGS_2(pcmpgtw, TCG_CALL_NO_RWG_SE, i64, i64, i64)
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|
DEF_HELPER_FLAGS_2(pcmpeqh, TCG_CALL_NO_RWG_SE, i64, i64, i64)
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|
DEF_HELPER_FLAGS_2(pcmpgth, TCG_CALL_NO_RWG_SE, i64, i64, i64)
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|
DEF_HELPER_FLAGS_2(pcmpeqb, TCG_CALL_NO_RWG_SE, i64, i64, i64)
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|
DEF_HELPER_FLAGS_2(pcmpgtb, TCG_CALL_NO_RWG_SE, i64, i64, i64)
|
2012-09-19 06:59:44 +02:00
|
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|
2012-10-09 21:53:09 +02:00
|
|
|
DEF_HELPER_FLAGS_2(psllw, TCG_CALL_NO_RWG_SE, i64, i64, i64)
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|
|
DEF_HELPER_FLAGS_2(psllh, TCG_CALL_NO_RWG_SE, i64, i64, i64)
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|
|
DEF_HELPER_FLAGS_2(psrlw, TCG_CALL_NO_RWG_SE, i64, i64, i64)
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|
DEF_HELPER_FLAGS_2(psrlh, TCG_CALL_NO_RWG_SE, i64, i64, i64)
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|
DEF_HELPER_FLAGS_2(psraw, TCG_CALL_NO_RWG_SE, i64, i64, i64)
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|
DEF_HELPER_FLAGS_2(psrah, TCG_CALL_NO_RWG_SE, i64, i64, i64)
|
2012-09-19 06:59:44 +02:00
|
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|
2012-10-09 21:53:09 +02:00
|
|
|
DEF_HELPER_FLAGS_2(pmullh, TCG_CALL_NO_RWG_SE, i64, i64, i64)
|
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|
|
DEF_HELPER_FLAGS_2(pmulhh, TCG_CALL_NO_RWG_SE, i64, i64, i64)
|
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|
|
DEF_HELPER_FLAGS_2(pmulhuh, TCG_CALL_NO_RWG_SE, i64, i64, i64)
|
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|
|
DEF_HELPER_FLAGS_2(pmaddhw, TCG_CALL_NO_RWG_SE, i64, i64, i64)
|
2012-09-19 06:59:44 +02:00
|
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|
|
2012-10-09 21:53:09 +02:00
|
|
|
DEF_HELPER_FLAGS_2(pasubub, TCG_CALL_NO_RWG_SE, i64, i64, i64)
|
|
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|
|
DEF_HELPER_FLAGS_1(biadd, TCG_CALL_NO_RWG_SE, i64, i64)
|
|
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|
|
DEF_HELPER_FLAGS_1(pmovmskb, TCG_CALL_NO_RWG_SE, i64, i64)
|
2012-09-19 06:59:44 +02:00
|
|
|
|
2012-10-24 16:17:06 +02:00
|
|
|
/*** MIPS DSP ***/
|
|
|
|
|
/* DSP Arithmetic Sub-class insns */
|
|
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|
|
DEF_HELPER_FLAGS_3(addq_ph, 0, tl, tl, tl, env)
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|
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|
|
DEF_HELPER_FLAGS_3(addq_s_ph, 0, tl, tl, tl, env)
|
|
|
|
|
#if defined(TARGET_MIPS64)
|
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|
|
|
DEF_HELPER_FLAGS_3(addq_qh, 0, tl, tl, tl, env)
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|
|
|
|
DEF_HELPER_FLAGS_3(addq_s_qh, 0, tl, tl, tl, env)
|
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|
|
#endif
|
|
|
|
|
DEF_HELPER_FLAGS_3(addq_s_w, 0, tl, tl, tl, env)
|
|
|
|
|
#if defined(TARGET_MIPS64)
|
|
|
|
|
DEF_HELPER_FLAGS_3(addq_pw, 0, tl, tl, tl, env)
|
|
|
|
|
DEF_HELPER_FLAGS_3(addq_s_pw, 0, tl, tl, tl, env)
|
|
|
|
|
#endif
|
|
|
|
|
DEF_HELPER_FLAGS_3(addu_qb, 0, tl, tl, tl, env)
|
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|
|
DEF_HELPER_FLAGS_3(addu_s_qb, 0, tl, tl, tl, env)
|
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|
|
|
DEF_HELPER_FLAGS_2(adduh_qb, TCG_CALL_NO_RWG_SE, tl, tl, tl)
|
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|
|
DEF_HELPER_FLAGS_2(adduh_r_qb, TCG_CALL_NO_RWG_SE, tl, tl, tl)
|
|
|
|
|
DEF_HELPER_FLAGS_3(addu_ph, 0, tl, tl, tl, env)
|
|
|
|
|
DEF_HELPER_FLAGS_3(addu_s_ph, 0, tl, tl, tl, env)
|
|
|
|
|
DEF_HELPER_FLAGS_2(addqh_ph, TCG_CALL_NO_RWG_SE, tl, tl, tl)
|
|
|
|
|
DEF_HELPER_FLAGS_2(addqh_r_ph, TCG_CALL_NO_RWG_SE, tl, tl, tl)
|
|
|
|
|
DEF_HELPER_FLAGS_2(addqh_w, TCG_CALL_NO_RWG_SE, tl, tl, tl)
|
|
|
|
|
DEF_HELPER_FLAGS_2(addqh_r_w, TCG_CALL_NO_RWG_SE, tl, tl, tl)
|
|
|
|
|
#if defined(TARGET_MIPS64)
|
|
|
|
|
DEF_HELPER_FLAGS_3(addu_ob, 0, tl, tl, tl, env)
|
|
|
|
|
DEF_HELPER_FLAGS_3(addu_s_ob, 0, tl, tl, tl, env)
|
|
|
|
|
DEF_HELPER_FLAGS_2(adduh_ob, TCG_CALL_NO_RWG_SE, tl, tl, tl)
|
|
|
|
|
DEF_HELPER_FLAGS_2(adduh_r_ob, TCG_CALL_NO_RWG_SE, tl, tl, tl)
|
|
|
|
|
DEF_HELPER_FLAGS_3(addu_qh, 0, tl, tl, tl, env)
|
|
|
|
|
DEF_HELPER_FLAGS_3(addu_s_qh, 0, tl, tl, tl, env)
|
|
|
|
|
#endif
|
|
|
|
|
DEF_HELPER_FLAGS_3(subq_ph, 0, tl, tl, tl, env)
|
|
|
|
|
DEF_HELPER_FLAGS_3(subq_s_ph, 0, tl, tl, tl, env)
|
|
|
|
|
#if defined(TARGET_MIPS64)
|
|
|
|
|
DEF_HELPER_FLAGS_3(subq_qh, 0, tl, tl, tl, env)
|
|
|
|
|
DEF_HELPER_FLAGS_3(subq_s_qh, 0, tl, tl, tl, env)
|
|
|
|
|
#endif
|
|
|
|
|
DEF_HELPER_FLAGS_3(subq_s_w, 0, tl, tl, tl, env)
|
|
|
|
|
#if defined(TARGET_MIPS64)
|
|
|
|
|
DEF_HELPER_FLAGS_3(subq_pw, 0, tl, tl, tl, env)
|
|
|
|
|
DEF_HELPER_FLAGS_3(subq_s_pw, 0, tl, tl, tl, env)
|
|
|
|
|
#endif
|
|
|
|
|
DEF_HELPER_FLAGS_3(subu_qb, 0, tl, tl, tl, env)
|
|
|
|
|
DEF_HELPER_FLAGS_3(subu_s_qb, 0, tl, tl, tl, env)
|
|
|
|
|
DEF_HELPER_FLAGS_2(subuh_qb, TCG_CALL_NO_RWG_SE, tl, tl, tl)
|
|
|
|
|
DEF_HELPER_FLAGS_2(subuh_r_qb, TCG_CALL_NO_RWG_SE, tl, tl, tl)
|
|
|
|
|
DEF_HELPER_FLAGS_3(subu_ph, 0, tl, tl, tl, env)
|
|
|
|
|
DEF_HELPER_FLAGS_3(subu_s_ph, 0, tl, tl, tl, env)
|
|
|
|
|
DEF_HELPER_FLAGS_2(subqh_ph, TCG_CALL_NO_RWG_SE, tl, tl, tl)
|
|
|
|
|
DEF_HELPER_FLAGS_2(subqh_r_ph, TCG_CALL_NO_RWG_SE, tl, tl, tl)
|
|
|
|
|
DEF_HELPER_FLAGS_2(subqh_w, TCG_CALL_NO_RWG_SE, tl, tl, tl)
|
|
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|
|
DEF_HELPER_FLAGS_2(subqh_r_w, TCG_CALL_NO_RWG_SE, tl, tl, tl)
|
|
|
|
|
#if defined(TARGET_MIPS64)
|
|
|
|
|
DEF_HELPER_FLAGS_3(subu_ob, 0, tl, tl, tl, env)
|
|
|
|
|
DEF_HELPER_FLAGS_3(subu_s_ob, 0, tl, tl, tl, env)
|
|
|
|
|
DEF_HELPER_FLAGS_2(subuh_ob, TCG_CALL_NO_RWG_SE, tl, tl, tl)
|
|
|
|
|
DEF_HELPER_FLAGS_2(subuh_r_ob, TCG_CALL_NO_RWG_SE, tl, tl, tl)
|
|
|
|
|
DEF_HELPER_FLAGS_3(subu_qh, 0, tl, tl, tl, env)
|
|
|
|
|
DEF_HELPER_FLAGS_3(subu_s_qh, 0, tl, tl, tl, env)
|
|
|
|
|
#endif
|
|
|
|
|
DEF_HELPER_FLAGS_3(addsc, 0, tl, tl, tl, env)
|
|
|
|
|
DEF_HELPER_FLAGS_3(addwc, 0, tl, tl, tl, env)
|
|
|
|
|
DEF_HELPER_FLAGS_2(modsub, TCG_CALL_NO_RWG_SE, tl, tl, tl)
|
|
|
|
|
DEF_HELPER_FLAGS_1(raddu_w_qb, TCG_CALL_NO_RWG_SE, tl, tl)
|
|
|
|
|
#if defined(TARGET_MIPS64)
|
|
|
|
|
DEF_HELPER_FLAGS_1(raddu_l_ob, TCG_CALL_NO_RWG_SE, tl, tl)
|
|
|
|
|
#endif
|
|
|
|
|
DEF_HELPER_FLAGS_2(absq_s_qb, 0, tl, tl, env)
|
|
|
|
|
DEF_HELPER_FLAGS_2(absq_s_ph, 0, tl, tl, env)
|
|
|
|
|
DEF_HELPER_FLAGS_2(absq_s_w, 0, tl, tl, env)
|
|
|
|
|
#if defined(TARGET_MIPS64)
|
|
|
|
|
DEF_HELPER_FLAGS_2(absq_s_ob, 0, tl, tl, env)
|
|
|
|
|
DEF_HELPER_FLAGS_2(absq_s_qh, 0, tl, tl, env)
|
|
|
|
|
DEF_HELPER_FLAGS_2(absq_s_pw, 0, tl, tl, env)
|
|
|
|
|
#endif
|
|
|
|
|
DEF_HELPER_FLAGS_2(precr_qb_ph, TCG_CALL_NO_RWG_SE, tl, tl, tl)
|
|
|
|
|
DEF_HELPER_FLAGS_2(precrq_qb_ph, TCG_CALL_NO_RWG_SE, tl, tl, tl)
|
|
|
|
|
DEF_HELPER_FLAGS_3(precr_sra_ph_w, TCG_CALL_NO_RWG_SE,
|
|
|
|
|
tl, i32, tl, tl)
|
|
|
|
|
DEF_HELPER_FLAGS_3(precr_sra_r_ph_w, TCG_CALL_NO_RWG_SE,
|
|
|
|
|
tl, i32, tl, tl)
|
|
|
|
|
DEF_HELPER_FLAGS_2(precrq_ph_w, TCG_CALL_NO_RWG_SE, tl, tl, tl)
|
|
|
|
|
DEF_HELPER_FLAGS_3(precrq_rs_ph_w, 0, tl, tl, tl, env)
|
|
|
|
|
#if defined(TARGET_MIPS64)
|
|
|
|
|
DEF_HELPER_FLAGS_2(precr_ob_qh, TCG_CALL_NO_RWG_SE, tl, tl, tl)
|
|
|
|
|
DEF_HELPER_FLAGS_3(precr_sra_qh_pw,
|
|
|
|
|
TCG_CALL_NO_RWG_SE, tl, tl, tl, i32)
|
|
|
|
|
DEF_HELPER_FLAGS_3(precr_sra_r_qh_pw,
|
|
|
|
|
TCG_CALL_NO_RWG_SE, tl, tl, tl, i32)
|
|
|
|
|
DEF_HELPER_FLAGS_2(precrq_ob_qh, TCG_CALL_NO_RWG_SE, tl, tl, tl)
|
|
|
|
|
DEF_HELPER_FLAGS_2(precrq_qh_pw, TCG_CALL_NO_RWG_SE, tl, tl, tl)
|
|
|
|
|
DEF_HELPER_FLAGS_3(precrq_rs_qh_pw,
|
|
|
|
|
TCG_CALL_NO_RWG_SE, tl, tl, tl, env)
|
|
|
|
|
DEF_HELPER_FLAGS_2(precrq_pw_l, TCG_CALL_NO_RWG_SE, tl, tl, tl)
|
|
|
|
|
#endif
|
|
|
|
|
DEF_HELPER_FLAGS_3(precrqu_s_qb_ph, 0, tl, tl, tl, env)
|
|
|
|
|
#if defined(TARGET_MIPS64)
|
|
|
|
|
DEF_HELPER_FLAGS_3(precrqu_s_ob_qh,
|
|
|
|
|
TCG_CALL_NO_RWG_SE, tl, tl, tl, env)
|
|
|
|
|
|
|
|
|
|
DEF_HELPER_FLAGS_1(preceq_pw_qhl, TCG_CALL_NO_RWG_SE, tl, tl)
|
|
|
|
|
DEF_HELPER_FLAGS_1(preceq_pw_qhr, TCG_CALL_NO_RWG_SE, tl, tl)
|
|
|
|
|
DEF_HELPER_FLAGS_1(preceq_pw_qhla, TCG_CALL_NO_RWG_SE, tl, tl)
|
|
|
|
|
DEF_HELPER_FLAGS_1(preceq_pw_qhra, TCG_CALL_NO_RWG_SE, tl, tl)
|
|
|
|
|
#endif
|
|
|
|
|
DEF_HELPER_FLAGS_1(precequ_ph_qbl, TCG_CALL_NO_RWG_SE, tl, tl)
|
|
|
|
|
DEF_HELPER_FLAGS_1(precequ_ph_qbr, TCG_CALL_NO_RWG_SE, tl, tl)
|
|
|
|
|
DEF_HELPER_FLAGS_1(precequ_ph_qbla, TCG_CALL_NO_RWG_SE, tl, tl)
|
|
|
|
|
DEF_HELPER_FLAGS_1(precequ_ph_qbra, TCG_CALL_NO_RWG_SE, tl, tl)
|
|
|
|
|
#if defined(TARGET_MIPS64)
|
|
|
|
|
DEF_HELPER_FLAGS_1(precequ_qh_obl, TCG_CALL_NO_RWG_SE, tl, tl)
|
|
|
|
|
DEF_HELPER_FLAGS_1(precequ_qh_obr, TCG_CALL_NO_RWG_SE, tl, tl)
|
|
|
|
|
DEF_HELPER_FLAGS_1(precequ_qh_obla, TCG_CALL_NO_RWG_SE, tl, tl)
|
|
|
|
|
DEF_HELPER_FLAGS_1(precequ_qh_obra, TCG_CALL_NO_RWG_SE, tl, tl)
|
|
|
|
|
#endif
|
|
|
|
|
DEF_HELPER_FLAGS_1(preceu_ph_qbl, TCG_CALL_NO_RWG_SE, tl, tl)
|
|
|
|
|
DEF_HELPER_FLAGS_1(preceu_ph_qbr, TCG_CALL_NO_RWG_SE, tl, tl)
|
|
|
|
|
DEF_HELPER_FLAGS_1(preceu_ph_qbla, TCG_CALL_NO_RWG_SE, tl, tl)
|
|
|
|
|
DEF_HELPER_FLAGS_1(preceu_ph_qbra, TCG_CALL_NO_RWG_SE, tl, tl)
|
|
|
|
|
#if defined(TARGET_MIPS64)
|
|
|
|
|
DEF_HELPER_FLAGS_1(preceu_qh_obl, TCG_CALL_NO_RWG_SE, tl, tl)
|
|
|
|
|
DEF_HELPER_FLAGS_1(preceu_qh_obr, TCG_CALL_NO_RWG_SE, tl, tl)
|
|
|
|
|
DEF_HELPER_FLAGS_1(preceu_qh_obla, TCG_CALL_NO_RWG_SE, tl, tl)
|
|
|
|
|
DEF_HELPER_FLAGS_1(preceu_qh_obra, TCG_CALL_NO_RWG_SE, tl, tl)
|
|
|
|
|
#endif
|
|
|
|
|
|
2012-10-24 16:17:07 +02:00
|
|
|
/* DSP GPR-Based Shift Sub-class insns */
|
|
|
|
|
DEF_HELPER_FLAGS_3(shll_qb, 0, tl, tl, tl, env)
|
|
|
|
|
#if defined(TARGET_MIPS64)
|
|
|
|
|
DEF_HELPER_FLAGS_3(shll_ob, 0, tl, tl, tl, env)
|
|
|
|
|
#endif
|
|
|
|
|
DEF_HELPER_FLAGS_3(shll_ph, 0, tl, tl, tl, env)
|
|
|
|
|
DEF_HELPER_FLAGS_3(shll_s_ph, 0, tl, tl, tl, env)
|
|
|
|
|
#if defined(TARGET_MIPS64)
|
|
|
|
|
DEF_HELPER_FLAGS_3(shll_qh, 0, tl, tl, tl, env)
|
|
|
|
|
DEF_HELPER_FLAGS_3(shll_s_qh, 0, tl, tl, tl, env)
|
|
|
|
|
#endif
|
|
|
|
|
DEF_HELPER_FLAGS_3(shll_s_w, 0, tl, tl, tl, env)
|
|
|
|
|
#if defined(TARGET_MIPS64)
|
|
|
|
|
DEF_HELPER_FLAGS_3(shll_pw, 0, tl, tl, tl, env)
|
|
|
|
|
DEF_HELPER_FLAGS_3(shll_s_pw, 0, tl, tl, tl, env)
|
|
|
|
|
#endif
|
|
|
|
|
DEF_HELPER_FLAGS_2(shrl_qb, TCG_CALL_NO_RWG_SE, tl, tl, tl)
|
|
|
|
|
DEF_HELPER_FLAGS_2(shrl_ph, TCG_CALL_NO_RWG_SE, tl, tl, tl)
|
|
|
|
|
#if defined(TARGET_MIPS64)
|
|
|
|
|
DEF_HELPER_FLAGS_2(shrl_ob, TCG_CALL_NO_RWG_SE, tl, tl, tl)
|
|
|
|
|
DEF_HELPER_FLAGS_2(shrl_qh, TCG_CALL_NO_RWG_SE, tl, tl, tl)
|
|
|
|
|
#endif
|
|
|
|
|
DEF_HELPER_FLAGS_2(shra_qb, TCG_CALL_NO_RWG_SE, tl, tl, tl)
|
|
|
|
|
DEF_HELPER_FLAGS_2(shra_r_qb, TCG_CALL_NO_RWG_SE, tl, tl, tl)
|
|
|
|
|
#if defined(TARGET_MIPS64)
|
|
|
|
|
DEF_HELPER_FLAGS_2(shra_ob, TCG_CALL_NO_RWG_SE, tl, tl, tl)
|
|
|
|
|
DEF_HELPER_FLAGS_2(shra_r_ob, TCG_CALL_NO_RWG_SE, tl, tl, tl)
|
|
|
|
|
#endif
|
|
|
|
|
DEF_HELPER_FLAGS_2(shra_ph, TCG_CALL_NO_RWG_SE, tl, tl, tl)
|
|
|
|
|
DEF_HELPER_FLAGS_2(shra_r_ph, TCG_CALL_NO_RWG_SE, tl, tl, tl)
|
|
|
|
|
DEF_HELPER_FLAGS_2(shra_r_w, TCG_CALL_NO_RWG_SE, tl, tl, tl)
|
|
|
|
|
#if defined(TARGET_MIPS64)
|
|
|
|
|
DEF_HELPER_FLAGS_2(shra_qh, TCG_CALL_NO_RWG_SE, tl, tl, tl)
|
|
|
|
|
DEF_HELPER_FLAGS_2(shra_r_qh, TCG_CALL_NO_RWG_SE, tl, tl, tl)
|
|
|
|
|
DEF_HELPER_FLAGS_2(shra_pw, TCG_CALL_NO_RWG_SE, tl, tl, tl)
|
|
|
|
|
DEF_HELPER_FLAGS_2(shra_r_pw, TCG_CALL_NO_RWG_SE, tl, tl, tl)
|
|
|
|
|
#endif
|
|
|
|
|
|
2012-10-24 16:17:08 +02:00
|
|
|
/* DSP Multiply Sub-class insns */
|
|
|
|
|
DEF_HELPER_FLAGS_3(muleu_s_ph_qbl, 0, tl, tl, tl, env)
|
|
|
|
|
DEF_HELPER_FLAGS_3(muleu_s_ph_qbr, 0, tl, tl, tl, env)
|
|
|
|
|
#if defined(TARGET_MIPS64)
|
|
|
|
|
DEF_HELPER_FLAGS_3(muleu_s_qh_obl, 0, tl, tl, tl, env)
|
|
|
|
|
DEF_HELPER_FLAGS_3(muleu_s_qh_obr, 0, tl, tl, tl, env)
|
|
|
|
|
#endif
|
|
|
|
|
DEF_HELPER_FLAGS_3(mulq_rs_ph, 0, tl, tl, tl, env)
|
|
|
|
|
#if defined(TARGET_MIPS64)
|
|
|
|
|
DEF_HELPER_FLAGS_3(mulq_rs_qh, 0, tl, tl, tl, env)
|
|
|
|
|
#endif
|
|
|
|
|
DEF_HELPER_FLAGS_3(muleq_s_w_phl, 0, tl, tl, tl, env)
|
|
|
|
|
DEF_HELPER_FLAGS_3(muleq_s_w_phr, 0, tl, tl, tl, env)
|
|
|
|
|
#if defined(TARGET_MIPS64)
|
|
|
|
|
DEF_HELPER_FLAGS_3(muleq_s_pw_qhl, 0, tl, tl, tl, env)
|
|
|
|
|
DEF_HELPER_FLAGS_3(muleq_s_pw_qhr, 0, tl, tl, tl, env)
|
|
|
|
|
#endif
|
|
|
|
|
DEF_HELPER_FLAGS_4(dpau_h_qbl, 0, void, i32, tl, tl, env)
|
|
|
|
|
DEF_HELPER_FLAGS_4(dpau_h_qbr, 0, void, i32, tl, tl, env)
|
|
|
|
|
#if defined(TARGET_MIPS64)
|
|
|
|
|
DEF_HELPER_FLAGS_4(dpau_h_obl, 0, void, tl, tl, i32, env)
|
|
|
|
|
DEF_HELPER_FLAGS_4(dpau_h_obr, 0, void, tl, tl, i32, env)
|
|
|
|
|
#endif
|
|
|
|
|
DEF_HELPER_FLAGS_4(dpsu_h_qbl, 0, void, i32, tl, tl, env)
|
|
|
|
|
DEF_HELPER_FLAGS_4(dpsu_h_qbr, 0, void, i32, tl, tl, env)
|
|
|
|
|
#if defined(TARGET_MIPS64)
|
|
|
|
|
DEF_HELPER_FLAGS_4(dpsu_h_obl, 0, void, tl, tl, i32, env)
|
|
|
|
|
DEF_HELPER_FLAGS_4(dpsu_h_obr, 0, void, tl, tl, i32, env)
|
|
|
|
|
#endif
|
|
|
|
|
DEF_HELPER_FLAGS_4(dpa_w_ph, 0, void, i32, tl, tl, env)
|
|
|
|
|
#if defined(TARGET_MIPS64)
|
|
|
|
|
DEF_HELPER_FLAGS_4(dpa_w_qh, 0, void, tl, tl, i32, env)
|
|
|
|
|
#endif
|
|
|
|
|
DEF_HELPER_FLAGS_4(dpax_w_ph, 0, void, i32, tl, tl, env)
|
|
|
|
|
DEF_HELPER_FLAGS_4(dpaq_s_w_ph, 0, void, i32, tl, tl, env)
|
|
|
|
|
#if defined(TARGET_MIPS64)
|
|
|
|
|
DEF_HELPER_FLAGS_4(dpaq_s_w_qh, 0, void, tl, tl, i32, env)
|
|
|
|
|
#endif
|
|
|
|
|
DEF_HELPER_FLAGS_4(dpaqx_s_w_ph, 0, void, i32, tl, tl, env)
|
|
|
|
|
DEF_HELPER_FLAGS_4(dpaqx_sa_w_ph, 0, void, i32, tl, tl, env)
|
|
|
|
|
DEF_HELPER_FLAGS_4(dps_w_ph, 0, void, i32, tl, tl, env)
|
|
|
|
|
#if defined(TARGET_MIPS64)
|
|
|
|
|
DEF_HELPER_FLAGS_4(dps_w_qh, 0, void, tl, tl, i32, env)
|
|
|
|
|
#endif
|
|
|
|
|
DEF_HELPER_FLAGS_4(dpsx_w_ph, 0, void, i32, tl, tl, env)
|
|
|
|
|
DEF_HELPER_FLAGS_4(dpsq_s_w_ph, 0, void, i32, tl, tl, env)
|
|
|
|
|
#if defined(TARGET_MIPS64)
|
|
|
|
|
DEF_HELPER_FLAGS_4(dpsq_s_w_qh, 0, void, tl, tl, i32, env)
|
|
|
|
|
#endif
|
|
|
|
|
DEF_HELPER_FLAGS_4(dpsqx_s_w_ph, 0, void, i32, tl, tl, env)
|
|
|
|
|
DEF_HELPER_FLAGS_4(dpsqx_sa_w_ph, 0, void, i32, tl, tl, env)
|
|
|
|
|
DEF_HELPER_FLAGS_4(mulsaq_s_w_ph, 0, void, i32, tl, tl, env)
|
|
|
|
|
#if defined(TARGET_MIPS64)
|
|
|
|
|
DEF_HELPER_FLAGS_4(mulsaq_s_w_qh, 0, void, tl, tl, i32, env)
|
|
|
|
|
#endif
|
|
|
|
|
DEF_HELPER_FLAGS_4(dpaq_sa_l_w, 0, void, i32, tl, tl, env)
|
|
|
|
|
#if defined(TARGET_MIPS64)
|
|
|
|
|
DEF_HELPER_FLAGS_4(dpaq_sa_l_pw, 0, void, tl, tl, i32, env)
|
|
|
|
|
#endif
|
|
|
|
|
DEF_HELPER_FLAGS_4(dpsq_sa_l_w, 0, void, i32, tl, tl, env)
|
|
|
|
|
#if defined(TARGET_MIPS64)
|
|
|
|
|
DEF_HELPER_FLAGS_4(dpsq_sa_l_pw, 0, void, tl, tl, i32, env)
|
|
|
|
|
DEF_HELPER_FLAGS_4(mulsaq_s_l_pw, 0, void, tl, tl, i32, env)
|
|
|
|
|
#endif
|
|
|
|
|
DEF_HELPER_FLAGS_4(maq_s_w_phl, 0, void, i32, tl, tl, env)
|
|
|
|
|
DEF_HELPER_FLAGS_4(maq_s_w_phr, 0, void, i32, tl, tl, env)
|
|
|
|
|
DEF_HELPER_FLAGS_4(maq_sa_w_phl, 0, void, i32, tl, tl, env)
|
|
|
|
|
DEF_HELPER_FLAGS_4(maq_sa_w_phr, 0, void, i32, tl, tl, env)
|
|
|
|
|
DEF_HELPER_FLAGS_3(mul_ph, 0, tl, tl, tl, env)
|
|
|
|
|
DEF_HELPER_FLAGS_3(mul_s_ph, 0, tl, tl, tl, env)
|
|
|
|
|
DEF_HELPER_FLAGS_3(mulq_s_ph, 0, tl, tl, tl, env)
|
|
|
|
|
DEF_HELPER_FLAGS_3(mulq_s_w, 0, tl, tl, tl, env)
|
|
|
|
|
DEF_HELPER_FLAGS_3(mulq_rs_w, 0, tl, tl, tl, env)
|
|
|
|
|
DEF_HELPER_FLAGS_4(mulsa_w_ph, 0, void, i32, tl, tl, env)
|
|
|
|
|
#if defined(TARGET_MIPS64)
|
|
|
|
|
DEF_HELPER_FLAGS_4(maq_s_w_qhll, 0, void, tl, tl, i32, env)
|
|
|
|
|
DEF_HELPER_FLAGS_4(maq_s_w_qhlr, 0, void, tl, tl, i32, env)
|
|
|
|
|
DEF_HELPER_FLAGS_4(maq_s_w_qhrl, 0, void, tl, tl, i32, env)
|
|
|
|
|
DEF_HELPER_FLAGS_4(maq_s_w_qhrr, 0, void, tl, tl, i32, env)
|
|
|
|
|
DEF_HELPER_FLAGS_4(maq_sa_w_qhll, 0, void, tl, tl, i32, env)
|
|
|
|
|
DEF_HELPER_FLAGS_4(maq_sa_w_qhlr, 0, void, tl, tl, i32, env)
|
|
|
|
|
DEF_HELPER_FLAGS_4(maq_sa_w_qhrl, 0, void, tl, tl, i32, env)
|
|
|
|
|
DEF_HELPER_FLAGS_4(maq_sa_w_qhrr, 0, void, tl, tl, i32, env)
|
|
|
|
|
DEF_HELPER_FLAGS_4(maq_s_l_pwl, 0, void, tl, tl, i32, env)
|
|
|
|
|
DEF_HELPER_FLAGS_4(maq_s_l_pwr, 0, void, tl, tl, i32, env)
|
|
|
|
|
DEF_HELPER_FLAGS_4(dmadd, 0, void, tl, tl, i32, env)
|
|
|
|
|
DEF_HELPER_FLAGS_4(dmaddu, 0, void, tl, tl, i32, env)
|
|
|
|
|
DEF_HELPER_FLAGS_4(dmsub, 0, void, tl, tl, i32, env)
|
|
|
|
|
DEF_HELPER_FLAGS_4(dmsubu, 0, void, tl, tl, i32, env)
|
|
|
|
|
#endif
|
|
|
|
|
|
2012-10-24 16:17:09 +02:00
|
|
|
/* DSP Bit/Manipulation Sub-class insns */
|
|
|
|
|
DEF_HELPER_FLAGS_1(bitrev, TCG_CALL_NO_RWG_SE, tl, tl)
|
|
|
|
|
DEF_HELPER_FLAGS_3(insv, 0, tl, env, tl, tl)
|
|
|
|
|
#if defined(TARGET_MIPS64)
|
2013-09-15 00:38:30 +02:00
|
|
|
DEF_HELPER_FLAGS_3(dinsv, 0, tl, env, tl, tl)
|
2012-10-24 16:17:09 +02:00
|
|
|
#endif
|
|
|
|
|
|
2012-10-24 16:17:10 +02:00
|
|
|
/* DSP Compare-Pick Sub-class insns */
|
|
|
|
|
DEF_HELPER_FLAGS_3(cmpu_eq_qb, 0, void, tl, tl, env)
|
|
|
|
|
DEF_HELPER_FLAGS_3(cmpu_lt_qb, 0, void, tl, tl, env)
|
|
|
|
|
DEF_HELPER_FLAGS_3(cmpu_le_qb, 0, void, tl, tl, env)
|
|
|
|
|
DEF_HELPER_FLAGS_2(cmpgu_eq_qb, TCG_CALL_NO_RWG_SE, tl, tl, tl)
|
|
|
|
|
DEF_HELPER_FLAGS_2(cmpgu_lt_qb, TCG_CALL_NO_RWG_SE, tl, tl, tl)
|
|
|
|
|
DEF_HELPER_FLAGS_2(cmpgu_le_qb, TCG_CALL_NO_RWG_SE, tl, tl, tl)
|
|
|
|
|
DEF_HELPER_FLAGS_3(cmp_eq_ph, 0, void, tl, tl, env)
|
|
|
|
|
DEF_HELPER_FLAGS_3(cmp_lt_ph, 0, void, tl, tl, env)
|
|
|
|
|
DEF_HELPER_FLAGS_3(cmp_le_ph, 0, void, tl, tl, env)
|
|
|
|
|
#if defined(TARGET_MIPS64)
|
|
|
|
|
DEF_HELPER_FLAGS_3(cmpu_eq_ob, 0, void, tl, tl, env)
|
|
|
|
|
DEF_HELPER_FLAGS_3(cmpu_lt_ob, 0, void, tl, tl, env)
|
|
|
|
|
DEF_HELPER_FLAGS_3(cmpu_le_ob, 0, void, tl, tl, env)
|
|
|
|
|
DEF_HELPER_FLAGS_3(cmpgdu_eq_ob, 0, tl, tl, tl, env)
|
|
|
|
|
DEF_HELPER_FLAGS_3(cmpgdu_lt_ob, 0, tl, tl, tl, env)
|
|
|
|
|
DEF_HELPER_FLAGS_3(cmpgdu_le_ob, 0, tl, tl, tl, env)
|
|
|
|
|
DEF_HELPER_FLAGS_2(cmpgu_eq_ob, TCG_CALL_NO_RWG_SE, tl, tl, tl)
|
|
|
|
|
DEF_HELPER_FLAGS_2(cmpgu_lt_ob, TCG_CALL_NO_RWG_SE, tl, tl, tl)
|
|
|
|
|
DEF_HELPER_FLAGS_2(cmpgu_le_ob, TCG_CALL_NO_RWG_SE, tl, tl, tl)
|
|
|
|
|
DEF_HELPER_FLAGS_3(cmp_eq_qh, 0, void, tl, tl, env)
|
|
|
|
|
DEF_HELPER_FLAGS_3(cmp_lt_qh, 0, void, tl, tl, env)
|
|
|
|
|
DEF_HELPER_FLAGS_3(cmp_le_qh, 0, void, tl, tl, env)
|
|
|
|
|
DEF_HELPER_FLAGS_3(cmp_eq_pw, 0, void, tl, tl, env)
|
|
|
|
|
DEF_HELPER_FLAGS_3(cmp_lt_pw, 0, void, tl, tl, env)
|
|
|
|
|
DEF_HELPER_FLAGS_3(cmp_le_pw, 0, void, tl, tl, env)
|
|
|
|
|
#endif
|
|
|
|
|
DEF_HELPER_FLAGS_3(pick_qb, 0, tl, tl, tl, env)
|
|
|
|
|
DEF_HELPER_FLAGS_3(pick_ph, 0, tl, tl, tl, env)
|
|
|
|
|
#if defined(TARGET_MIPS64)
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DEF_HELPER_FLAGS_3(pick_ob, 0, tl, tl, tl, env)
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DEF_HELPER_FLAGS_3(pick_qh, 0, tl, tl, tl, env)
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DEF_HELPER_FLAGS_3(pick_pw, 0, tl, tl, tl, env)
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#endif
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DEF_HELPER_FLAGS_2(packrl_ph, TCG_CALL_NO_RWG_SE, tl, tl, tl)
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#if defined(TARGET_MIPS64)
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DEF_HELPER_FLAGS_2(packrl_pw, TCG_CALL_NO_RWG_SE, tl, tl, tl)
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#endif
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2012-10-24 16:17:11 +02:00
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/* DSP Accumulator and DSPControl Access Sub-class insns */
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DEF_HELPER_FLAGS_3(extr_w, 0, tl, tl, tl, env)
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DEF_HELPER_FLAGS_3(extr_r_w, 0, tl, tl, tl, env)
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DEF_HELPER_FLAGS_3(extr_rs_w, 0, tl, tl, tl, env)
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#if defined(TARGET_MIPS64)
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DEF_HELPER_FLAGS_3(dextr_w, 0, tl, tl, tl, env)
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DEF_HELPER_FLAGS_3(dextr_r_w, 0, tl, tl, tl, env)
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DEF_HELPER_FLAGS_3(dextr_rs_w, 0, tl, tl, tl, env)
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DEF_HELPER_FLAGS_3(dextr_l, 0, tl, tl, tl, env)
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DEF_HELPER_FLAGS_3(dextr_r_l, 0, tl, tl, tl, env)
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DEF_HELPER_FLAGS_3(dextr_rs_l, 0, tl, tl, tl, env)
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#endif
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DEF_HELPER_FLAGS_3(extr_s_h, 0, tl, tl, tl, env)
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#if defined(TARGET_MIPS64)
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DEF_HELPER_FLAGS_3(dextr_s_h, 0, tl, tl, tl, env)
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#endif
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DEF_HELPER_FLAGS_3(extp, 0, tl, tl, tl, env)
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DEF_HELPER_FLAGS_3(extpdp, 0, tl, tl, tl, env)
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#if defined(TARGET_MIPS64)
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DEF_HELPER_FLAGS_3(dextp, 0, tl, tl, tl, env)
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DEF_HELPER_FLAGS_3(dextpdp, 0, tl, tl, tl, env)
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#endif
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DEF_HELPER_FLAGS_3(shilo, 0, void, tl, tl, env)
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#if defined(TARGET_MIPS64)
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DEF_HELPER_FLAGS_3(dshilo, 0, void, tl, tl, env)
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#endif
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DEF_HELPER_FLAGS_3(mthlip, 0, void, tl, tl, env)
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#if defined(TARGET_MIPS64)
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DEF_HELPER_FLAGS_3(dmthlip, 0, void, tl, tl, env)
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#endif
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DEF_HELPER_FLAGS_3(wrdsp, 0, void, tl, tl, env)
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DEF_HELPER_FLAGS_2(rddsp, 0, tl, tl, env)
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2014-11-01 06:28:43 +01:00
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2021-04-13 11:51:53 +02:00
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#ifndef CONFIG_USER_ONLY
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#include "tcg/sysemu_helper.h.inc"
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#endif /* !CONFIG_USER_ONLY */
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2021-04-13 10:47:10 +02:00
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#include "tcg/msa_helper.h.inc"
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2020-11-16 16:39:20 +01:00
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/* Vendor extensions */
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#include "tcg/vr54xx_helper.h.inc"
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