2011-10-16 15:30:27 +02:00
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/*
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* KVM in-kernel PIC (i8259) support
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*
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* Copyright (c) 2011 Siemens AG
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*
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* Authors:
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* Jan Kiszka <jan.kiszka@siemens.com>
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*
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* This work is licensed under the terms of the GNU GPL version 2.
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* See the COPYING file in the top-level directory.
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*/
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2019-05-23 16:35:07 +02:00
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2016-01-26 19:17:03 +01:00
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#include "qemu/osdep.h"
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2013-02-05 17:06:20 +01:00
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#include "hw/isa/i8259_internal.h"
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2019-12-12 17:15:43 +01:00
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#include "hw/intc/i8259.h"
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2019-05-23 16:35:07 +02:00
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#include "qemu/module.h"
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2013-02-05 17:06:20 +01:00
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#include "hw/i386/apic_internal.h"
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2019-08-12 07:23:42 +02:00
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#include "hw/irq.h"
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2012-12-17 18:20:04 +01:00
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#include "sysemu/kvm.h"
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2020-09-03 22:43:22 +02:00
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#include "qom/object.h"
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2011-10-16 15:30:27 +02:00
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2012-11-25 22:38:13 +01:00
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#define TYPE_KVM_I8259 "kvm-i8259"
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2020-09-03 22:43:22 +02:00
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typedef struct KVMPICClass KVMPICClass;
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2020-08-31 23:07:33 +02:00
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DECLARE_CLASS_CHECKERS(KVMPICClass, KVM_PIC,
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TYPE_KVM_I8259)
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2012-11-25 22:54:47 +01:00
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/**
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* KVMPICClass:
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* @parent_realize: The parent's realizefn.
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*/
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2020-09-03 22:43:22 +02:00
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struct KVMPICClass {
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2012-11-25 22:54:47 +01:00
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PICCommonClass parent_class;
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DeviceRealize parent_realize;
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2020-09-03 22:43:22 +02:00
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};
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2012-11-25 22:38:13 +01:00
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2011-10-16 15:30:27 +02:00
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static void kvm_pic_get(PICCommonState *s)
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{
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struct kvm_irqchip chip;
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struct kvm_pic_state *kpic;
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int ret;
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chip.chip_id = s->master ? KVM_IRQCHIP_PIC_MASTER : KVM_IRQCHIP_PIC_SLAVE;
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ret = kvm_vm_ioctl(kvm_state, KVM_GET_IRQCHIP, &chip);
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if (ret < 0) {
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2021-05-19 13:35:28 +02:00
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fprintf(stderr, "KVM_GET_IRQCHIP failed: %s\n", strerror(-ret));
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2011-10-16 15:30:27 +02:00
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abort();
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}
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kpic = &chip.chip.pic;
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s->last_irr = kpic->last_irr;
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s->irr = kpic->irr;
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s->imr = kpic->imr;
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s->isr = kpic->isr;
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s->priority_add = kpic->priority_add;
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s->irq_base = kpic->irq_base;
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s->read_reg_select = kpic->read_reg_select;
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s->poll = kpic->poll;
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s->special_mask = kpic->special_mask;
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s->init_state = kpic->init_state;
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s->auto_eoi = kpic->auto_eoi;
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s->rotate_on_auto_eoi = kpic->rotate_on_auto_eoi;
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s->special_fully_nested_mode = kpic->special_fully_nested_mode;
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s->init4 = kpic->init4;
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s->elcr = kpic->elcr;
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s->elcr_mask = kpic->elcr_mask;
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}
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static void kvm_pic_put(PICCommonState *s)
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{
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struct kvm_irqchip chip;
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struct kvm_pic_state *kpic;
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int ret;
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chip.chip_id = s->master ? KVM_IRQCHIP_PIC_MASTER : KVM_IRQCHIP_PIC_SLAVE;
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kpic = &chip.chip.pic;
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kpic->last_irr = s->last_irr;
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kpic->irr = s->irr;
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kpic->imr = s->imr;
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kpic->isr = s->isr;
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kpic->priority_add = s->priority_add;
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kpic->irq_base = s->irq_base;
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kpic->read_reg_select = s->read_reg_select;
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kpic->poll = s->poll;
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kpic->special_mask = s->special_mask;
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kpic->init_state = s->init_state;
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kpic->auto_eoi = s->auto_eoi;
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kpic->rotate_on_auto_eoi = s->rotate_on_auto_eoi;
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kpic->special_fully_nested_mode = s->special_fully_nested_mode;
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kpic->init4 = s->init4;
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kpic->elcr = s->elcr;
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kpic->elcr_mask = s->elcr_mask;
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ret = kvm_vm_ioctl(kvm_state, KVM_SET_IRQCHIP, &chip);
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if (ret < 0) {
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2021-05-19 13:35:28 +02:00
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fprintf(stderr, "KVM_SET_IRQCHIP failed: %s\n", strerror(-ret));
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2011-10-16 15:30:27 +02:00
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abort();
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}
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}
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static void kvm_pic_reset(DeviceState *dev)
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{
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2013-04-27 22:18:40 +02:00
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PICCommonState *s = PIC_COMMON(dev);
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2011-10-16 15:30:27 +02:00
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s->elcr = 0;
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2012-01-24 16:29:29 +01:00
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pic_reset_common(s);
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2011-10-16 15:30:27 +02:00
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kvm_pic_put(s);
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}
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static void kvm_pic_set_irq(void *opaque, int irq, int level)
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{
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int delivered;
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2017-12-10 07:38:18 +01:00
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pic_stat_update_irq(irq, level);
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2012-07-26 16:35:12 +02:00
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delivered = kvm_set_irq(kvm_state, irq, level);
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2011-10-16 15:30:27 +02:00
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apic_report_irq_delivered(delivered);
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}
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2012-11-25 22:54:47 +01:00
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static void kvm_pic_realize(DeviceState *dev, Error **errp)
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2011-10-16 15:30:27 +02:00
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{
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2012-11-25 22:54:47 +01:00
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PICCommonState *s = PIC_COMMON(dev);
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KVMPICClass *kpc = KVM_PIC_GET_CLASS(dev);
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2018-05-15 16:35:16 +02:00
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memory_region_init_io(&s->base_io, OBJECT(dev), NULL, NULL, "kvm-pic", 2);
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memory_region_init_io(&s->elcr_io, OBJECT(dev), NULL, NULL, "kvm-elcr", 1);
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2012-11-25 22:54:47 +01:00
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kpc->parent_realize(dev, errp);
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2011-10-16 15:30:27 +02:00
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}
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qemu_irq *kvm_i8259_init(ISABus *bus)
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{
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2012-11-25 22:38:13 +01:00
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i8259_init_chip(TYPE_KVM_I8259, bus, true);
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i8259_init_chip(TYPE_KVM_I8259, bus, false);
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2011-10-16 15:30:27 +02:00
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return qemu_allocate_irqs(kvm_pic_set_irq, NULL, ISA_NUM_IRQS);
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}
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2011-12-04 18:52:49 +01:00
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static void kvm_i8259_class_init(ObjectClass *klass, void *data)
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{
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2012-11-25 22:54:47 +01:00
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KVMPICClass *kpc = KVM_PIC_CLASS(klass);
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2011-12-04 18:52:49 +01:00
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PICCommonClass *k = PIC_COMMON_CLASS(klass);
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2011-12-08 04:34:16 +01:00
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DeviceClass *dc = DEVICE_CLASS(klass);
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2011-12-04 18:52:49 +01:00
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2011-12-08 04:34:16 +01:00
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dc->reset = kvm_pic_reset;
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2018-01-14 03:04:12 +01:00
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device_class_set_parent_realize(dc, kvm_pic_realize, &kpc->parent_realize);
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2011-12-04 18:52:49 +01:00
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k->pre_save = kvm_pic_get;
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k->post_load = kvm_pic_put;
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}
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2013-01-10 16:19:07 +01:00
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static const TypeInfo kvm_i8259_info = {
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2012-11-25 22:38:13 +01:00
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.name = TYPE_KVM_I8259,
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2011-12-08 04:34:16 +01:00
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.parent = TYPE_PIC_COMMON,
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2012-02-03 22:06:47 +01:00
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.instance_size = sizeof(PICCommonState),
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2011-12-04 18:52:49 +01:00
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.class_init = kvm_i8259_class_init,
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2012-11-25 22:54:47 +01:00
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.class_size = sizeof(KVMPICClass),
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2011-10-16 15:30:27 +02:00
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};
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2012-02-09 15:20:55 +01:00
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static void kvm_pic_register_types(void)
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2011-10-16 15:30:27 +02:00
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{
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2011-12-08 04:34:16 +01:00
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type_register_static(&kvm_i8259_info);
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2011-10-16 15:30:27 +02:00
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}
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2012-02-09 15:20:55 +01:00
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type_init(kvm_pic_register_types)
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