2011-05-08 13:22:38 +02:00
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/*
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* User emulator execution
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*
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* Copyright (c) 2003-2005 Fabrice Bellard
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*
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* This library is free software; you can redistribute it and/or
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* modify it under the terms of the GNU Lesser General Public
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* License as published by the Free Software Foundation; either
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2019-01-23 15:08:56 +01:00
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* version 2.1 of the License, or (at your option) any later version.
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2011-05-08 13:22:38 +02:00
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*
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* This library is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
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* Lesser General Public License for more details.
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*
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* You should have received a copy of the GNU Lesser General Public
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* License along with this library; if not, see <http://www.gnu.org/licenses/>.
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*/
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2016-01-29 18:50:05 +01:00
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#include "qemu/osdep.h"
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2011-07-13 14:44:15 +02:00
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#include "cpu.h"
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2012-10-24 11:12:21 +02:00
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#include "disas/disas.h"
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2016-03-15 13:18:37 +01:00
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#include "exec/exec-all.h"
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2011-05-08 13:22:38 +02:00
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#include "tcg.h"
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2013-06-04 15:31:45 +02:00
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#include "qemu/bitops.h"
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2014-03-28 19:42:10 +01:00
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#include "exec/cpu_ldst.h"
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2015-04-22 14:15:48 +02:00
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#include "translate-all.h"
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2017-09-12 23:19:34 +02:00
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#include "exec/helper-proto.h"
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2018-08-16 01:31:47 +02:00
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#include "qemu/atomic128.h"
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2011-05-08 13:22:38 +02:00
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#undef EAX
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#undef ECX
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#undef EDX
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#undef EBX
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#undef ESP
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#undef EBP
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#undef ESI
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#undef EDI
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#undef EIP
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#ifdef __linux__
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#include <sys/ucontext.h>
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#endif
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2017-11-14 10:34:20 +01:00
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__thread uintptr_t helper_retaddr;
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2011-05-08 13:22:38 +02:00
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//#define DEBUG_SIGNAL
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/* exit the current TB from a signal handler. The host registers are
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restored in a state compatible with the CPU emulator
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*/
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2016-05-17 16:18:05 +02:00
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static void cpu_exit_tb_from_sighandler(CPUState *cpu, sigset_t *old_set)
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2011-05-08 13:22:38 +02:00
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{
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2016-05-17 16:18:03 +02:00
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/* XXX: use siglongjmp ? */
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2016-05-17 16:18:05 +02:00
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sigprocmask(SIG_SETMASK, old_set, NULL);
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2016-05-17 16:18:04 +02:00
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cpu_loop_exit_noexc(cpu);
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2011-05-08 13:22:38 +02:00
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}
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/* 'pc' is the host PC at which the exception was raised. 'address' is
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the effective address of the memory exception. 'is_write' is 1 if a
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write caused the exception and otherwise 0'. 'old_set' is the
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signal set which should be restored */
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2017-11-28 15:35:24 +01:00
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static inline int handle_cpu_signal(uintptr_t pc, siginfo_t *info,
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2016-05-17 16:18:05 +02:00
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int is_write, sigset_t *old_set)
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2011-05-08 13:22:38 +02:00
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{
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2017-03-20 12:31:44 +01:00
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CPUState *cpu = current_cpu;
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2013-08-26 03:01:33 +02:00
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CPUClass *cc;
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2017-11-28 15:35:24 +01:00
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unsigned long address = (unsigned long)info->si_addr;
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2019-04-02 09:37:51 +02:00
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MMUAccessType access_type;
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2011-05-08 13:22:38 +02:00
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2017-11-14 10:34:20 +01:00
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/* We must handle PC addresses from two different sources:
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* a call return address and a signal frame address.
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*
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* Within cpu_restore_state_from_tb we assume the former and adjust
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* the address by -GETPC_ADJ so that the address is within the call
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* insn so that addr does not accidentally match the beginning of the
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* next guest insn.
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*
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* However, when the PC comes from the signal frame, it points to
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* the actual faulting host insn and not a call insn. Subtracting
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* GETPC_ADJ in that case may accidentally match the previous guest insn.
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*
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* So for the later case, adjust forward to compensate for what
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* will be done later by cpu_restore_state_from_tb.
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*/
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if (helper_retaddr) {
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pc = helper_retaddr;
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} else {
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pc += GETPC_ADJ;
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}
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2017-03-20 12:31:44 +01:00
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/* For synchronous signals we expect to be coming from the vCPU
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* thread (so current_cpu should be valid) and either from running
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* code or during translation which can fault as we cross pages.
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*
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* If neither is true then something has gone wrong and we should
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* abort rather than try and restart the vCPU execution.
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*/
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if (!cpu || !cpu->running) {
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printf("qemu:%s received signal outside vCPU context @ pc=0x%"
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PRIxPTR "\n", __func__, pc);
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abort();
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}
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2011-05-08 13:22:38 +02:00
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#if defined(DEBUG_SIGNAL)
|
2015-08-19 17:20:19 +02:00
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printf("qemu: SIGSEGV pc=0x%08lx address=%08lx w=%d oldset=0x%08lx\n",
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pc, address, is_write, *(unsigned long *)old_set);
|
2011-05-08 13:22:38 +02:00
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#endif
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/* XXX: locking issue */
|
2017-11-28 15:35:25 +01:00
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/* Note that it is important that we don't call page_unprotect() unless
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* this is really a "write to nonwriteable page" fault, because
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* page_unprotect() assumes that if it is called for an access to
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* a page that's writeable this means we had two threads racing and
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* another thread got there first and already made the page writeable;
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* so we will retry the access. If we were to call page_unprotect()
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* for some other kind of fault that should really be passed to the
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* guest, we'd end up in an infinite loop of retrying the faulting
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* access.
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*/
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if (is_write && info->si_signo == SIGSEGV && info->si_code == SEGV_ACCERR &&
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h2g_valid(address)) {
|
2016-05-17 16:18:03 +02:00
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switch (page_unprotect(h2g(address), pc)) {
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case 0:
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/* Fault not caused by a page marked unwritable to protect
|
2017-11-14 10:34:20 +01:00
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* cached translations, must be the guest binary's problem.
|
2016-05-17 16:18:03 +02:00
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*/
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break;
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case 1:
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/* Fault caused by protection of cached translation; TBs
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2017-11-14 10:34:20 +01:00
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* invalidated, so resume execution. Retain helper_retaddr
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* for a possible second fault.
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2016-05-17 16:18:03 +02:00
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*/
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return 1;
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case 2:
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/* Fault caused by protection of cached translation, and the
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* currently executing TB was modified and must be exited
|
2017-11-14 10:34:20 +01:00
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* immediately. Clear helper_retaddr for next execution.
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2016-05-17 16:18:03 +02:00
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*/
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2017-11-14 10:34:20 +01:00
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helper_retaddr = 0;
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2017-03-20 12:31:44 +01:00
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cpu_exit_tb_from_sighandler(cpu, old_set);
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2017-11-14 10:34:20 +01:00
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/* NORETURN */
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2016-05-17 16:18:03 +02:00
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default:
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g_assert_not_reached();
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}
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2011-05-08 13:22:38 +02:00
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}
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|
2013-07-06 14:17:49 +02:00
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/* Convert forcefully to guest address space, invalid addresses
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are still valid segv ones */
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address = h2g_nocheck(address);
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|
2019-04-02 09:37:51 +02:00
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/*
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* There is no way the target can handle this other than raising
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* an exception. Undo signal and retaddr state prior to longjmp.
|
2017-11-14 10:34:20 +01:00
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*/
|
2019-04-02 09:37:51 +02:00
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sigprocmask(SIG_SETMASK, old_set, NULL);
|
2017-11-14 10:34:20 +01:00
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helper_retaddr = 0;
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|
2019-04-02 09:37:51 +02:00
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cc = CPU_GET_CLASS(cpu);
|
2019-04-03 05:37:13 +02:00
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access_type = is_write ? MMU_DATA_STORE : MMU_DATA_LOAD;
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cc->tlb_fill(cpu, address, 0, access_type, MMU_USER_IDX, false, pc);
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g_assert_not_reached();
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2011-05-08 13:22:38 +02:00
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}
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#if defined(__i386__)
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|
2016-06-13 12:48:27 +02:00
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#if defined(__NetBSD__)
|
2011-05-08 13:22:38 +02:00
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#include <ucontext.h>
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#define EIP_sig(context) ((context)->uc_mcontext.__gregs[_REG_EIP])
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#define TRAP_sig(context) ((context)->uc_mcontext.__gregs[_REG_TRAPNO])
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#define ERROR_sig(context) ((context)->uc_mcontext.__gregs[_REG_ERR])
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#define MASK_sig(context) ((context)->uc_sigmask)
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#elif defined(__FreeBSD__) || defined(__DragonFly__)
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#include <ucontext.h>
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#define EIP_sig(context) (*((unsigned long *)&(context)->uc_mcontext.mc_eip))
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#define TRAP_sig(context) ((context)->uc_mcontext.mc_trapno)
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#define ERROR_sig(context) ((context)->uc_mcontext.mc_err)
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#define MASK_sig(context) ((context)->uc_sigmask)
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#elif defined(__OpenBSD__)
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#define EIP_sig(context) ((context)->sc_eip)
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#define TRAP_sig(context) ((context)->sc_trapno)
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#define ERROR_sig(context) ((context)->sc_err)
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#define MASK_sig(context) ((context)->sc_mask)
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#else
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#define EIP_sig(context) ((context)->uc_mcontext.gregs[REG_EIP])
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#define TRAP_sig(context) ((context)->uc_mcontext.gregs[REG_TRAPNO])
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#define ERROR_sig(context) ((context)->uc_mcontext.gregs[REG_ERR])
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#define MASK_sig(context) ((context)->uc_sigmask)
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#endif
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int cpu_signal_handler(int host_signum, void *pinfo,
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void *puc)
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|
|
{
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siginfo_t *info = pinfo;
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|
#if defined(__NetBSD__) || defined(__FreeBSD__) || defined(__DragonFly__)
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ucontext_t *uc = puc;
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#elif defined(__OpenBSD__)
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struct sigcontext *uc = puc;
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#else
|
2017-06-28 22:44:52 +02:00
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ucontext_t *uc = puc;
|
2011-05-08 13:22:38 +02:00
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|
#endif
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unsigned long pc;
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int trapno;
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#ifndef REG_EIP
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|
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/* for glibc 2.1 */
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#define REG_EIP EIP
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#define REG_ERR ERR
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#define REG_TRAPNO TRAPNO
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#endif
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|
pc = EIP_sig(uc);
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trapno = TRAP_sig(uc);
|
2017-11-28 15:35:24 +01:00
|
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|
return handle_cpu_signal(pc, info,
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|
|
|
trapno == 0xe ? (ERROR_sig(uc) >> 1) & 1 : 0,
|
2016-05-17 16:18:05 +02:00
|
|
|
&MASK_sig(uc));
|
2011-05-08 13:22:38 +02:00
|
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}
|
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|
|
#elif defined(__x86_64__)
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|
|
#ifdef __NetBSD__
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|
|
#define PC_sig(context) _UC_MACHINE_PC(context)
|
|
|
|
#define TRAP_sig(context) ((context)->uc_mcontext.__gregs[_REG_TRAPNO])
|
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|
|
#define ERROR_sig(context) ((context)->uc_mcontext.__gregs[_REG_ERR])
|
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|
|
#define MASK_sig(context) ((context)->uc_sigmask)
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|
|
#elif defined(__OpenBSD__)
|
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|
|
#define PC_sig(context) ((context)->sc_rip)
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|
|
#define TRAP_sig(context) ((context)->sc_trapno)
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|
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#define ERROR_sig(context) ((context)->sc_err)
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|
|
|
#define MASK_sig(context) ((context)->sc_mask)
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|
|
#elif defined(__FreeBSD__) || defined(__DragonFly__)
|
|
|
|
#include <ucontext.h>
|
|
|
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|
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|
|
#define PC_sig(context) (*((unsigned long *)&(context)->uc_mcontext.mc_rip))
|
|
|
|
#define TRAP_sig(context) ((context)->uc_mcontext.mc_trapno)
|
|
|
|
#define ERROR_sig(context) ((context)->uc_mcontext.mc_err)
|
|
|
|
#define MASK_sig(context) ((context)->uc_sigmask)
|
|
|
|
#else
|
|
|
|
#define PC_sig(context) ((context)->uc_mcontext.gregs[REG_RIP])
|
|
|
|
#define TRAP_sig(context) ((context)->uc_mcontext.gregs[REG_TRAPNO])
|
|
|
|
#define ERROR_sig(context) ((context)->uc_mcontext.gregs[REG_ERR])
|
|
|
|
#define MASK_sig(context) ((context)->uc_sigmask)
|
|
|
|
#endif
|
|
|
|
|
|
|
|
int cpu_signal_handler(int host_signum, void *pinfo,
|
|
|
|
void *puc)
|
|
|
|
{
|
|
|
|
siginfo_t *info = pinfo;
|
|
|
|
unsigned long pc;
|
|
|
|
#if defined(__NetBSD__) || defined(__FreeBSD__) || defined(__DragonFly__)
|
|
|
|
ucontext_t *uc = puc;
|
|
|
|
#elif defined(__OpenBSD__)
|
|
|
|
struct sigcontext *uc = puc;
|
|
|
|
#else
|
2017-06-28 22:44:52 +02:00
|
|
|
ucontext_t *uc = puc;
|
2011-05-08 13:22:38 +02:00
|
|
|
#endif
|
|
|
|
|
|
|
|
pc = PC_sig(uc);
|
2017-11-28 15:35:24 +01:00
|
|
|
return handle_cpu_signal(pc, info,
|
|
|
|
TRAP_sig(uc) == 0xe ? (ERROR_sig(uc) >> 1) & 1 : 0,
|
2016-05-17 16:18:05 +02:00
|
|
|
&MASK_sig(uc));
|
2011-05-08 13:22:38 +02:00
|
|
|
}
|
|
|
|
|
|
|
|
#elif defined(_ARCH_PPC)
|
|
|
|
|
|
|
|
/***********************************************************************
|
|
|
|
* signal context platform-specific definitions
|
|
|
|
* From Wine
|
|
|
|
*/
|
|
|
|
#ifdef linux
|
|
|
|
/* All Registers access - only for local access */
|
|
|
|
#define REG_sig(reg_name, context) \
|
|
|
|
((context)->uc_mcontext.regs->reg_name)
|
|
|
|
/* Gpr Registers access */
|
|
|
|
#define GPR_sig(reg_num, context) REG_sig(gpr[reg_num], context)
|
|
|
|
/* Program counter */
|
|
|
|
#define IAR_sig(context) REG_sig(nip, context)
|
|
|
|
/* Machine State Register (Supervisor) */
|
|
|
|
#define MSR_sig(context) REG_sig(msr, context)
|
|
|
|
/* Count register */
|
|
|
|
#define CTR_sig(context) REG_sig(ctr, context)
|
|
|
|
/* User's integer exception register */
|
|
|
|
#define XER_sig(context) REG_sig(xer, context)
|
|
|
|
/* Link register */
|
|
|
|
#define LR_sig(context) REG_sig(link, context)
|
|
|
|
/* Condition register */
|
|
|
|
#define CR_sig(context) REG_sig(ccr, context)
|
|
|
|
|
|
|
|
/* Float Registers access */
|
|
|
|
#define FLOAT_sig(reg_num, context) \
|
|
|
|
(((double *)((char *)((context)->uc_mcontext.regs + 48 * 4)))[reg_num])
|
|
|
|
#define FPSCR_sig(context) \
|
|
|
|
(*(int *)((char *)((context)->uc_mcontext.regs + (48 + 32 * 2) * 4)))
|
|
|
|
/* Exception Registers access */
|
|
|
|
#define DAR_sig(context) REG_sig(dar, context)
|
|
|
|
#define DSISR_sig(context) REG_sig(dsisr, context)
|
|
|
|
#define TRAP_sig(context) REG_sig(trap, context)
|
|
|
|
#endif /* linux */
|
|
|
|
|
|
|
|
#if defined(__FreeBSD__) || defined(__FreeBSD_kernel__)
|
|
|
|
#include <ucontext.h>
|
|
|
|
#define IAR_sig(context) ((context)->uc_mcontext.mc_srr0)
|
|
|
|
#define MSR_sig(context) ((context)->uc_mcontext.mc_srr1)
|
|
|
|
#define CTR_sig(context) ((context)->uc_mcontext.mc_ctr)
|
|
|
|
#define XER_sig(context) ((context)->uc_mcontext.mc_xer)
|
|
|
|
#define LR_sig(context) ((context)->uc_mcontext.mc_lr)
|
|
|
|
#define CR_sig(context) ((context)->uc_mcontext.mc_cr)
|
|
|
|
/* Exception Registers access */
|
|
|
|
#define DAR_sig(context) ((context)->uc_mcontext.mc_dar)
|
|
|
|
#define DSISR_sig(context) ((context)->uc_mcontext.mc_dsisr)
|
|
|
|
#define TRAP_sig(context) ((context)->uc_mcontext.mc_exc)
|
|
|
|
#endif /* __FreeBSD__|| __FreeBSD_kernel__ */
|
|
|
|
|
|
|
|
int cpu_signal_handler(int host_signum, void *pinfo,
|
|
|
|
void *puc)
|
|
|
|
{
|
|
|
|
siginfo_t *info = pinfo;
|
|
|
|
#if defined(__FreeBSD__) || defined(__FreeBSD_kernel__)
|
|
|
|
ucontext_t *uc = puc;
|
|
|
|
#else
|
2017-06-28 22:44:52 +02:00
|
|
|
ucontext_t *uc = puc;
|
2011-05-08 13:22:38 +02:00
|
|
|
#endif
|
|
|
|
unsigned long pc;
|
|
|
|
int is_write;
|
|
|
|
|
|
|
|
pc = IAR_sig(uc);
|
|
|
|
is_write = 0;
|
|
|
|
#if 0
|
|
|
|
/* ppc 4xx case */
|
|
|
|
if (DSISR_sig(uc) & 0x00800000) {
|
|
|
|
is_write = 1;
|
|
|
|
}
|
|
|
|
#else
|
|
|
|
if (TRAP_sig(uc) != 0x400 && (DSISR_sig(uc) & 0x02000000)) {
|
|
|
|
is_write = 1;
|
|
|
|
}
|
|
|
|
#endif
|
2017-11-28 15:35:24 +01:00
|
|
|
return handle_cpu_signal(pc, info, is_write, &uc->uc_sigmask);
|
2011-05-08 13:22:38 +02:00
|
|
|
}
|
|
|
|
|
|
|
|
#elif defined(__alpha__)
|
|
|
|
|
|
|
|
int cpu_signal_handler(int host_signum, void *pinfo,
|
|
|
|
void *puc)
|
|
|
|
{
|
|
|
|
siginfo_t *info = pinfo;
|
2017-06-28 22:44:52 +02:00
|
|
|
ucontext_t *uc = puc;
|
2011-05-08 13:22:38 +02:00
|
|
|
uint32_t *pc = uc->uc_mcontext.sc_pc;
|
|
|
|
uint32_t insn = *pc;
|
|
|
|
int is_write = 0;
|
|
|
|
|
|
|
|
/* XXX: need kernel patch to get write flag faster */
|
|
|
|
switch (insn >> 26) {
|
|
|
|
case 0x0d: /* stw */
|
|
|
|
case 0x0e: /* stb */
|
|
|
|
case 0x0f: /* stq_u */
|
|
|
|
case 0x24: /* stf */
|
|
|
|
case 0x25: /* stg */
|
|
|
|
case 0x26: /* sts */
|
|
|
|
case 0x27: /* stt */
|
|
|
|
case 0x2c: /* stl */
|
|
|
|
case 0x2d: /* stq */
|
|
|
|
case 0x2e: /* stl_c */
|
|
|
|
case 0x2f: /* stq_c */
|
|
|
|
is_write = 1;
|
|
|
|
}
|
|
|
|
|
2017-11-28 15:35:24 +01:00
|
|
|
return handle_cpu_signal(pc, info, is_write, &uc->uc_sigmask);
|
2011-05-08 13:22:38 +02:00
|
|
|
}
|
|
|
|
#elif defined(__sparc__)
|
|
|
|
|
|
|
|
int cpu_signal_handler(int host_signum, void *pinfo,
|
|
|
|
void *puc)
|
|
|
|
{
|
|
|
|
siginfo_t *info = pinfo;
|
|
|
|
int is_write;
|
|
|
|
uint32_t insn;
|
|
|
|
#if !defined(__arch64__) || defined(CONFIG_SOLARIS)
|
|
|
|
uint32_t *regs = (uint32_t *)(info + 1);
|
|
|
|
void *sigmask = (regs + 20);
|
|
|
|
/* XXX: is there a standard glibc define ? */
|
|
|
|
unsigned long pc = regs[1];
|
|
|
|
#else
|
|
|
|
#ifdef __linux__
|
|
|
|
struct sigcontext *sc = puc;
|
|
|
|
unsigned long pc = sc->sigc_regs.tpc;
|
|
|
|
void *sigmask = (void *)sc->sigc_mask;
|
|
|
|
#elif defined(__OpenBSD__)
|
|
|
|
struct sigcontext *uc = puc;
|
|
|
|
unsigned long pc = uc->sc_pc;
|
|
|
|
void *sigmask = (void *)(long)uc->sc_mask;
|
2015-03-05 22:37:41 +01:00
|
|
|
#elif defined(__NetBSD__)
|
|
|
|
ucontext_t *uc = puc;
|
|
|
|
unsigned long pc = _UC_MACHINE_PC(uc);
|
|
|
|
void *sigmask = (void *)&uc->uc_sigmask;
|
2011-05-08 13:22:38 +02:00
|
|
|
#endif
|
|
|
|
#endif
|
|
|
|
|
|
|
|
/* XXX: need kernel patch to get write flag faster */
|
|
|
|
is_write = 0;
|
|
|
|
insn = *(uint32_t *)pc;
|
|
|
|
if ((insn >> 30) == 3) {
|
|
|
|
switch ((insn >> 19) & 0x3f) {
|
|
|
|
case 0x05: /* stb */
|
|
|
|
case 0x15: /* stba */
|
|
|
|
case 0x06: /* sth */
|
|
|
|
case 0x16: /* stha */
|
|
|
|
case 0x04: /* st */
|
|
|
|
case 0x14: /* sta */
|
|
|
|
case 0x07: /* std */
|
|
|
|
case 0x17: /* stda */
|
|
|
|
case 0x0e: /* stx */
|
|
|
|
case 0x1e: /* stxa */
|
|
|
|
case 0x24: /* stf */
|
|
|
|
case 0x34: /* stfa */
|
|
|
|
case 0x27: /* stdf */
|
|
|
|
case 0x37: /* stdfa */
|
|
|
|
case 0x26: /* stqf */
|
|
|
|
case 0x36: /* stqfa */
|
|
|
|
case 0x25: /* stfsr */
|
|
|
|
case 0x3c: /* casa */
|
|
|
|
case 0x3e: /* casxa */
|
|
|
|
is_write = 1;
|
|
|
|
break;
|
|
|
|
}
|
|
|
|
}
|
2017-11-28 15:35:24 +01:00
|
|
|
return handle_cpu_signal(pc, info, is_write, sigmask);
|
2011-05-08 13:22:38 +02:00
|
|
|
}
|
|
|
|
|
|
|
|
#elif defined(__arm__)
|
|
|
|
|
2015-03-05 22:37:41 +01:00
|
|
|
#if defined(__NetBSD__)
|
|
|
|
#include <ucontext.h>
|
|
|
|
#endif
|
|
|
|
|
2011-05-08 13:22:38 +02:00
|
|
|
int cpu_signal_handler(int host_signum, void *pinfo,
|
|
|
|
void *puc)
|
|
|
|
{
|
|
|
|
siginfo_t *info = pinfo;
|
2015-03-05 22:37:41 +01:00
|
|
|
#if defined(__NetBSD__)
|
|
|
|
ucontext_t *uc = puc;
|
|
|
|
#else
|
2017-06-28 22:44:52 +02:00
|
|
|
ucontext_t *uc = puc;
|
2015-03-05 22:37:41 +01:00
|
|
|
#endif
|
2011-05-08 13:22:38 +02:00
|
|
|
unsigned long pc;
|
|
|
|
int is_write;
|
|
|
|
|
2015-03-05 22:37:41 +01:00
|
|
|
#if defined(__NetBSD__)
|
|
|
|
pc = uc->uc_mcontext.__gregs[_REG_R15];
|
|
|
|
#elif defined(__GLIBC__) && (__GLIBC__ < 2 || (__GLIBC__ == 2 && __GLIBC_MINOR__ <= 3))
|
2011-05-08 13:22:38 +02:00
|
|
|
pc = uc->uc_mcontext.gregs[R15];
|
|
|
|
#else
|
|
|
|
pc = uc->uc_mcontext.arm_pc;
|
|
|
|
#endif
|
2013-06-04 15:31:45 +02:00
|
|
|
|
|
|
|
/* error_code is the FSR value, in which bit 11 is WnR (assuming a v6 or
|
|
|
|
* later processor; on v5 we will always report this as a read).
|
|
|
|
*/
|
|
|
|
is_write = extract32(uc->uc_mcontext.error_code, 11, 1);
|
2017-11-28 15:35:24 +01:00
|
|
|
return handle_cpu_signal(pc, info, is_write, &uc->uc_sigmask);
|
2011-05-08 13:22:38 +02:00
|
|
|
}
|
|
|
|
|
2013-06-12 17:20:23 +02:00
|
|
|
#elif defined(__aarch64__)
|
|
|
|
|
2019-01-29 12:46:04 +01:00
|
|
|
#ifndef ESR_MAGIC
|
|
|
|
/* Pre-3.16 kernel headers don't have these, so provide fallback definitions */
|
|
|
|
#define ESR_MAGIC 0x45535201
|
|
|
|
struct esr_context {
|
|
|
|
struct _aarch64_ctx head;
|
|
|
|
uint64_t esr;
|
|
|
|
};
|
|
|
|
#endif
|
|
|
|
|
|
|
|
static inline struct _aarch64_ctx *first_ctx(ucontext_t *uc)
|
|
|
|
{
|
|
|
|
return (struct _aarch64_ctx *)&uc->uc_mcontext.__reserved;
|
|
|
|
}
|
|
|
|
|
|
|
|
static inline struct _aarch64_ctx *next_ctx(struct _aarch64_ctx *hdr)
|
|
|
|
{
|
|
|
|
return (struct _aarch64_ctx *)((char *)hdr + hdr->size);
|
|
|
|
}
|
|
|
|
|
2014-03-15 03:24:57 +01:00
|
|
|
int cpu_signal_handler(int host_signum, void *pinfo, void *puc)
|
2013-06-12 17:20:23 +02:00
|
|
|
{
|
|
|
|
siginfo_t *info = pinfo;
|
2017-06-28 22:44:52 +02:00
|
|
|
ucontext_t *uc = puc;
|
2014-03-15 03:24:57 +01:00
|
|
|
uintptr_t pc = uc->uc_mcontext.pc;
|
|
|
|
bool is_write;
|
2019-01-29 12:46:04 +01:00
|
|
|
struct _aarch64_ctx *hdr;
|
|
|
|
struct esr_context const *esrctx = NULL;
|
2014-03-15 03:24:57 +01:00
|
|
|
|
2019-01-29 12:46:04 +01:00
|
|
|
/* Find the esr_context, which has the WnR bit in it */
|
|
|
|
for (hdr = first_ctx(uc); hdr->magic; hdr = next_ctx(hdr)) {
|
|
|
|
if (hdr->magic == ESR_MAGIC) {
|
|
|
|
esrctx = (struct esr_context const *)hdr;
|
|
|
|
break;
|
|
|
|
}
|
|
|
|
}
|
2014-03-15 03:24:57 +01:00
|
|
|
|
2019-01-29 12:46:04 +01:00
|
|
|
if (esrctx) {
|
|
|
|
/* For data aborts ESR.EC is 0b10010x: then bit 6 is the WnR bit */
|
|
|
|
uint64_t esr = esrctx->esr;
|
|
|
|
is_write = extract32(esr, 27, 5) == 0x12 && extract32(esr, 6, 1) == 1;
|
|
|
|
} else {
|
|
|
|
/*
|
|
|
|
* Fall back to parsing instructions; will only be needed
|
|
|
|
* for really ancient (pre-3.16) kernels.
|
|
|
|
*/
|
|
|
|
uint32_t insn = *(uint32_t *)pc;
|
|
|
|
|
|
|
|
is_write = ((insn & 0xbfff0000) == 0x0c000000 /* C3.3.1 */
|
|
|
|
|| (insn & 0xbfe00000) == 0x0c800000 /* C3.3.2 */
|
|
|
|
|| (insn & 0xbfdf0000) == 0x0d000000 /* C3.3.3 */
|
|
|
|
|| (insn & 0xbfc00000) == 0x0d800000 /* C3.3.4 */
|
|
|
|
|| (insn & 0x3f400000) == 0x08000000 /* C3.3.6 */
|
|
|
|
|| (insn & 0x3bc00000) == 0x39000000 /* C3.3.13 */
|
|
|
|
|| (insn & 0x3fc00000) == 0x3d800000 /* ... 128bit */
|
|
|
|
/* Ignore bits 10, 11 & 21, controlling indexing. */
|
|
|
|
|| (insn & 0x3bc00000) == 0x38000000 /* C3.3.8-12 */
|
|
|
|
|| (insn & 0x3fe00000) == 0x3c800000 /* ... 128bit */
|
|
|
|
/* Ignore bits 23 & 24, controlling indexing. */
|
|
|
|
|| (insn & 0x3a400000) == 0x28000000); /* C3.3.7,14-16 */
|
|
|
|
}
|
2017-11-28 15:35:24 +01:00
|
|
|
return handle_cpu_signal(pc, info, is_write, &uc->uc_sigmask);
|
2013-06-12 17:20:23 +02:00
|
|
|
}
|
|
|
|
|
2011-05-08 13:22:38 +02:00
|
|
|
#elif defined(__s390__)
|
|
|
|
|
|
|
|
int cpu_signal_handler(int host_signum, void *pinfo,
|
|
|
|
void *puc)
|
|
|
|
{
|
|
|
|
siginfo_t *info = pinfo;
|
2017-06-28 22:44:52 +02:00
|
|
|
ucontext_t *uc = puc;
|
2011-05-08 13:22:38 +02:00
|
|
|
unsigned long pc;
|
|
|
|
uint16_t *pinsn;
|
|
|
|
int is_write = 0;
|
|
|
|
|
|
|
|
pc = uc->uc_mcontext.psw.addr;
|
|
|
|
|
|
|
|
/* ??? On linux, the non-rt signal handler has 4 (!) arguments instead
|
|
|
|
of the normal 2 arguments. The 3rd argument contains the "int_code"
|
|
|
|
from the hardware which does in fact contain the is_write value.
|
|
|
|
The rt signal handler, as far as I can tell, does not give this value
|
|
|
|
at all. Not that we could get to it from here even if it were. */
|
|
|
|
/* ??? This is not even close to complete, since it ignores all
|
|
|
|
of the read-modify-write instructions. */
|
|
|
|
pinsn = (uint16_t *)pc;
|
|
|
|
switch (pinsn[0] >> 8) {
|
|
|
|
case 0x50: /* ST */
|
|
|
|
case 0x42: /* STC */
|
|
|
|
case 0x40: /* STH */
|
|
|
|
is_write = 1;
|
|
|
|
break;
|
|
|
|
case 0xc4: /* RIL format insns */
|
|
|
|
switch (pinsn[0] & 0xf) {
|
|
|
|
case 0xf: /* STRL */
|
|
|
|
case 0xb: /* STGRL */
|
|
|
|
case 0x7: /* STHRL */
|
|
|
|
is_write = 1;
|
|
|
|
}
|
|
|
|
break;
|
|
|
|
case 0xe3: /* RXY format insns */
|
|
|
|
switch (pinsn[2] & 0xff) {
|
|
|
|
case 0x50: /* STY */
|
|
|
|
case 0x24: /* STG */
|
|
|
|
case 0x72: /* STCY */
|
|
|
|
case 0x70: /* STHY */
|
|
|
|
case 0x8e: /* STPQ */
|
|
|
|
case 0x3f: /* STRVH */
|
|
|
|
case 0x3e: /* STRV */
|
|
|
|
case 0x2f: /* STRVG */
|
|
|
|
is_write = 1;
|
|
|
|
}
|
|
|
|
break;
|
|
|
|
}
|
2017-11-28 15:35:24 +01:00
|
|
|
return handle_cpu_signal(pc, info, is_write, &uc->uc_sigmask);
|
2011-05-08 13:22:38 +02:00
|
|
|
}
|
|
|
|
|
|
|
|
#elif defined(__mips__)
|
|
|
|
|
|
|
|
int cpu_signal_handler(int host_signum, void *pinfo,
|
|
|
|
void *puc)
|
|
|
|
{
|
|
|
|
siginfo_t *info = pinfo;
|
2017-06-28 22:44:52 +02:00
|
|
|
ucontext_t *uc = puc;
|
2011-05-08 13:22:38 +02:00
|
|
|
greg_t pc = uc->uc_mcontext.pc;
|
|
|
|
int is_write;
|
|
|
|
|
|
|
|
/* XXX: compute is_write */
|
|
|
|
is_write = 0;
|
2017-11-28 15:35:24 +01:00
|
|
|
return handle_cpu_signal(pc, info, is_write, &uc->uc_sigmask);
|
2011-05-08 13:22:38 +02:00
|
|
|
}
|
|
|
|
|
2018-12-19 20:19:59 +01:00
|
|
|
#elif defined(__riscv)
|
|
|
|
|
|
|
|
int cpu_signal_handler(int host_signum, void *pinfo,
|
|
|
|
void *puc)
|
|
|
|
{
|
|
|
|
siginfo_t *info = pinfo;
|
|
|
|
ucontext_t *uc = puc;
|
|
|
|
greg_t pc = uc->uc_mcontext.__gregs[REG_PC];
|
|
|
|
uint32_t insn = *(uint32_t *)pc;
|
|
|
|
int is_write = 0;
|
|
|
|
|
|
|
|
/* Detect store by reading the instruction at the program
|
|
|
|
counter. Note: we currently only generate 32-bit
|
|
|
|
instructions so we thus only detect 32-bit stores */
|
|
|
|
switch (((insn >> 0) & 0b11)) {
|
|
|
|
case 3:
|
|
|
|
switch (((insn >> 2) & 0b11111)) {
|
|
|
|
case 8:
|
|
|
|
switch (((insn >> 12) & 0b111)) {
|
|
|
|
case 0: /* sb */
|
|
|
|
case 1: /* sh */
|
|
|
|
case 2: /* sw */
|
|
|
|
case 3: /* sd */
|
|
|
|
case 4: /* sq */
|
|
|
|
is_write = 1;
|
|
|
|
break;
|
|
|
|
default:
|
|
|
|
break;
|
|
|
|
}
|
|
|
|
break;
|
|
|
|
case 9:
|
|
|
|
switch (((insn >> 12) & 0b111)) {
|
|
|
|
case 2: /* fsw */
|
|
|
|
case 3: /* fsd */
|
|
|
|
case 4: /* fsq */
|
|
|
|
is_write = 1;
|
|
|
|
break;
|
|
|
|
default:
|
|
|
|
break;
|
|
|
|
}
|
|
|
|
break;
|
|
|
|
default:
|
|
|
|
break;
|
|
|
|
}
|
|
|
|
}
|
|
|
|
|
|
|
|
/* Check for compressed instructions */
|
|
|
|
switch (((insn >> 13) & 0b111)) {
|
|
|
|
case 7:
|
|
|
|
switch (insn & 0b11) {
|
|
|
|
case 0: /*c.sd */
|
|
|
|
case 2: /* c.sdsp */
|
|
|
|
is_write = 1;
|
|
|
|
break;
|
|
|
|
default:
|
|
|
|
break;
|
|
|
|
}
|
|
|
|
break;
|
|
|
|
case 6:
|
|
|
|
switch (insn & 0b11) {
|
|
|
|
case 0: /* c.sw */
|
|
|
|
case 3: /* c.swsp */
|
|
|
|
is_write = 1;
|
|
|
|
break;
|
|
|
|
default:
|
|
|
|
break;
|
|
|
|
}
|
|
|
|
break;
|
|
|
|
default:
|
|
|
|
break;
|
|
|
|
}
|
|
|
|
|
|
|
|
return handle_cpu_signal(pc, info, is_write, &uc->uc_sigmask);
|
|
|
|
}
|
|
|
|
|
2011-05-08 13:22:38 +02:00
|
|
|
#else
|
|
|
|
|
|
|
|
#error host CPU specific signal handler needed
|
|
|
|
|
|
|
|
#endif
|
2017-09-12 23:19:34 +02:00
|
|
|
|
|
|
|
/* The softmmu versions of these helpers are in cputlb.c. */
|
|
|
|
|
|
|
|
/* Do not allow unaligned operations to proceed. Return the host address. */
|
|
|
|
static void *atomic_mmu_lookup(CPUArchState *env, target_ulong addr,
|
|
|
|
int size, uintptr_t retaddr)
|
|
|
|
{
|
|
|
|
/* Enforce qemu required alignment. */
|
|
|
|
if (unlikely(addr & (size - 1))) {
|
2019-03-23 00:07:18 +01:00
|
|
|
cpu_loop_exit_atomic(env_cpu(env), retaddr);
|
2017-09-12 23:19:34 +02:00
|
|
|
}
|
2017-11-14 10:34:20 +01:00
|
|
|
helper_retaddr = retaddr;
|
2017-09-12 23:19:34 +02:00
|
|
|
return g2h(addr);
|
|
|
|
}
|
|
|
|
|
|
|
|
/* Macro to call the above, with local variables from the use context. */
|
2017-11-20 19:08:28 +01:00
|
|
|
#define ATOMIC_MMU_DECLS do {} while (0)
|
2017-09-12 23:19:34 +02:00
|
|
|
#define ATOMIC_MMU_LOOKUP atomic_mmu_lookup(env, addr, DATA_SIZE, GETPC())
|
2017-11-14 10:34:20 +01:00
|
|
|
#define ATOMIC_MMU_CLEANUP do { helper_retaddr = 0; } while (0)
|
2017-09-12 23:19:34 +02:00
|
|
|
|
|
|
|
#define ATOMIC_NAME(X) HELPER(glue(glue(atomic_ ## X, SUFFIX), END))
|
|
|
|
#define EXTRA_ARGS
|
|
|
|
|
|
|
|
#define DATA_SIZE 1
|
|
|
|
#include "atomic_template.h"
|
|
|
|
|
|
|
|
#define DATA_SIZE 2
|
|
|
|
#include "atomic_template.h"
|
|
|
|
|
|
|
|
#define DATA_SIZE 4
|
|
|
|
#include "atomic_template.h"
|
|
|
|
|
|
|
|
#ifdef CONFIG_ATOMIC64
|
|
|
|
#define DATA_SIZE 8
|
|
|
|
#include "atomic_template.h"
|
|
|
|
#endif
|
|
|
|
|
|
|
|
/* The following is only callable from other helpers, and matches up
|
|
|
|
with the softmmu version. */
|
|
|
|
|
2018-08-16 01:31:47 +02:00
|
|
|
#if HAVE_ATOMIC128 || HAVE_CMPXCHG128
|
2017-09-12 23:19:34 +02:00
|
|
|
|
|
|
|
#undef EXTRA_ARGS
|
|
|
|
#undef ATOMIC_NAME
|
|
|
|
#undef ATOMIC_MMU_LOOKUP
|
|
|
|
|
|
|
|
#define EXTRA_ARGS , TCGMemOpIdx oi, uintptr_t retaddr
|
|
|
|
#define ATOMIC_NAME(X) \
|
|
|
|
HELPER(glue(glue(glue(atomic_ ## X, SUFFIX), END), _mmu))
|
|
|
|
#define ATOMIC_MMU_LOOKUP atomic_mmu_lookup(env, addr, DATA_SIZE, retaddr)
|
|
|
|
|
|
|
|
#define DATA_SIZE 16
|
|
|
|
#include "atomic_template.h"
|
2018-08-16 01:31:47 +02:00
|
|
|
#endif
|