2017-02-07 19:29:59 +01:00
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/*
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* ASPEED Watchdog Controller
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*
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* Copyright (C) 2016-2017 IBM Corp.
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*
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* This code is licensed under the GPL version 2 or later. See the
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* COPYING file in the top-level directory.
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*/
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2019-03-15 15:51:20 +01:00
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#ifndef WDT_ASPEED_H
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#define WDT_ASPEED_H
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2017-02-07 19:29:59 +01:00
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2019-08-12 07:23:31 +02:00
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#include "hw/misc/aspeed_scu.h"
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2017-02-07 19:29:59 +01:00
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#include "hw/sysbus.h"
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2020-09-03 22:43:22 +02:00
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#include "qom/object.h"
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2017-02-07 19:29:59 +01:00
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#define TYPE_ASPEED_WDT "aspeed.wdt"
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2020-09-16 20:25:18 +02:00
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OBJECT_DECLARE_TYPE(AspeedWDTState, AspeedWDTClass, ASPEED_WDT)
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2019-09-25 16:32:35 +02:00
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#define TYPE_ASPEED_2400_WDT TYPE_ASPEED_WDT "-ast2400"
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#define TYPE_ASPEED_2500_WDT TYPE_ASPEED_WDT "-ast2500"
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2019-09-25 16:32:36 +02:00
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#define TYPE_ASPEED_2600_WDT TYPE_ASPEED_WDT "-ast2600"
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2022-05-02 17:03:03 +02:00
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#define TYPE_ASPEED_1030_WDT TYPE_ASPEED_WDT "-ast1030"
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2017-02-07 19:29:59 +01:00
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#define ASPEED_WDT_REGS_MAX (0x20 / 4)
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2020-09-03 22:43:22 +02:00
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struct AspeedWDTState {
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2017-02-07 19:29:59 +01:00
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/*< private >*/
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SysBusDevice parent_obj;
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QEMUTimer *timer;
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/*< public >*/
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MemoryRegion iomem;
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uint32_t regs[ASPEED_WDT_REGS_MAX];
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2019-07-01 18:26:18 +02:00
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AspeedSCUState *scu;
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2017-02-07 19:29:59 +01:00
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uint32_t pclk_freq;
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2020-09-03 22:43:22 +02:00
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};
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2017-02-07 19:29:59 +01:00
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2019-09-25 16:32:35 +02:00
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2020-09-03 22:43:22 +02:00
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struct AspeedWDTClass {
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2019-09-25 16:32:35 +02:00
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SysBusDeviceClass parent_class;
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2023-02-07 09:02:05 +01:00
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uint32_t iosize;
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2019-09-25 16:32:35 +02:00
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uint32_t ext_pulse_width_mask;
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uint32_t reset_ctrl_reg;
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void (*reset_pulse)(AspeedWDTState *s, uint32_t property);
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2019-11-19 15:12:03 +01:00
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void (*wdt_reload)(AspeedWDTState *s);
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2021-09-20 08:50:59 +02:00
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uint64_t (*sanitize_ctrl)(uint64_t data);
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2022-05-02 17:03:03 +02:00
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uint32_t default_status;
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uint32_t default_reload_value;
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2020-09-03 22:43:22 +02:00
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};
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2019-09-25 16:32:35 +02:00
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2019-03-15 15:51:20 +01:00
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#endif /* WDT_ASPEED_H */
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