2016-07-04 14:06:37 +02:00
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/*
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* QEMU model of the Xilinx Devcfg Interface
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*
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* (C) 2011 PetaLogix Pty Ltd
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* (C) 2014 Xilinx Inc.
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* Written by Peter Crosthwaite <peter.crosthwaite@xilinx.com>
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*
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* Permission is hereby granted, free of charge, to any person obtaining a copy
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* of this software and associated documentation files (the "Software"), to deal
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* in the Software without restriction, including without limitation the rights
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* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
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* copies of the Software, and to permit persons to whom the Software is
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* furnished to do so, subject to the following conditions:
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*
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* The above copyright notice and this permission notice shall be included in
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* all copies or substantial portions of the Software.
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*
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* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
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* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
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* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
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* THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
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* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
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* OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
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* THE SOFTWARE.
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*/
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#ifndef XLNX_ZYNQ_DEVCFG_H
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2019-06-04 20:16:15 +02:00
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#define XLNX_ZYNQ_DEVCFG_H
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2016-07-04 14:06:37 +02:00
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#include "hw/register.h"
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#include "hw/sysbus.h"
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2020-09-03 22:43:22 +02:00
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#include "qom/object.h"
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2016-07-04 14:06:37 +02:00
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#define TYPE_XLNX_ZYNQ_DEVCFG "xlnx.ps7-dev-cfg"
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2020-09-16 20:25:19 +02:00
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OBJECT_DECLARE_SIMPLE_TYPE(XlnxZynqDevcfg, XLNX_ZYNQ_DEVCFG)
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2016-07-04 14:06:37 +02:00
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2016-09-22 19:13:08 +02:00
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#define XLNX_ZYNQ_DEVCFG_R_MAX (0x100 / 4)
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2016-07-04 14:06:37 +02:00
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#define XLNX_ZYNQ_DEVCFG_DMA_CMD_FIFO_LEN 10
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typedef struct XlnxZynqDevcfgDMACmd {
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uint32_t src_addr;
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uint32_t dest_addr;
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uint32_t src_len;
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uint32_t dest_len;
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} XlnxZynqDevcfgDMACmd;
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2020-09-03 22:43:22 +02:00
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struct XlnxZynqDevcfg {
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2016-07-04 14:06:37 +02:00
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SysBusDevice parent_obj;
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MemoryRegion iomem;
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qemu_irq irq;
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XlnxZynqDevcfgDMACmd dma_cmd_fifo[XLNX_ZYNQ_DEVCFG_DMA_CMD_FIFO_LEN];
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uint8_t dma_cmd_fifo_num;
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uint32_t regs[XLNX_ZYNQ_DEVCFG_R_MAX];
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RegisterInfo regs_info[XLNX_ZYNQ_DEVCFG_R_MAX];
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2020-09-03 22:43:22 +02:00
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};
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2016-07-04 14:06:37 +02:00
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#endif
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