2018-01-22 22:07:48 +01:00
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/*
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* QEMU Windows Hypervisor Platform accelerator (WHPX)
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*
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* Copyright Microsoft Corp. 2017
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*
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* This work is licensed under the terms of the GNU GPL, version 2 or later.
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* See the COPYING file in the top-level directory.
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*
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*/
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#include "qemu/osdep.h"
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#include "cpu.h"
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#include "exec/address-spaces.h"
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#include "exec/ioport.h"
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2022-03-03 02:28:33 +01:00
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#include "exec/gdbstub.h"
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2021-02-04 17:39:24 +01:00
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#include "qemu/accel.h"
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2018-01-22 22:07:48 +01:00
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#include "sysemu/whpx.h"
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#include "sysemu/cpus.h"
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2019-08-12 07:23:59 +02:00
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#include "sysemu/runstate.h"
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2018-01-22 22:07:48 +01:00
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#include "qemu/main-loop.h"
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2019-09-20 13:33:27 +02:00
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#include "hw/boards.h"
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2020-10-28 03:23:19 +01:00
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#include "hw/i386/ioapic.h"
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#include "hw/i386/apic_internal.h"
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2018-01-22 22:07:48 +01:00
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#include "qemu/error-report.h"
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#include "qapi/error.h"
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2020-10-28 03:23:19 +01:00
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#include "qapi/qapi-types-common.h"
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#include "qapi/qapi-visit-common.h"
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2018-01-22 22:07:48 +01:00
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#include "migration/blocker.h"
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2020-10-28 03:23:19 +01:00
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#include <winerror.h>
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2018-01-22 22:07:48 +01:00
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2020-12-19 10:06:36 +01:00
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#include "whpx-internal.h"
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2021-02-04 17:39:25 +01:00
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#include "whpx-accel-ops.h"
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#include <WinHvPlatform.h>
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#include <WinHvEmulation.h>
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2018-01-22 22:07:48 +01:00
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2020-07-31 00:11:26 +02:00
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#define HYPERV_APIC_BUS_FREQUENCY (200000000ULL)
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2018-01-22 22:07:48 +01:00
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static const WHV_REGISTER_NAME whpx_register_names[] = {
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/* X64 General purpose registers */
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WHvX64RegisterRax,
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WHvX64RegisterRcx,
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WHvX64RegisterRdx,
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WHvX64RegisterRbx,
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WHvX64RegisterRsp,
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WHvX64RegisterRbp,
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WHvX64RegisterRsi,
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WHvX64RegisterRdi,
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WHvX64RegisterR8,
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WHvX64RegisterR9,
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WHvX64RegisterR10,
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WHvX64RegisterR11,
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WHvX64RegisterR12,
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WHvX64RegisterR13,
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WHvX64RegisterR14,
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WHvX64RegisterR15,
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WHvX64RegisterRip,
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WHvX64RegisterRflags,
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/* X64 Segment registers */
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WHvX64RegisterEs,
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WHvX64RegisterCs,
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WHvX64RegisterSs,
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WHvX64RegisterDs,
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WHvX64RegisterFs,
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WHvX64RegisterGs,
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WHvX64RegisterLdtr,
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WHvX64RegisterTr,
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/* X64 Table registers */
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WHvX64RegisterIdtr,
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WHvX64RegisterGdtr,
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/* X64 Control Registers */
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WHvX64RegisterCr0,
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WHvX64RegisterCr2,
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WHvX64RegisterCr3,
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WHvX64RegisterCr4,
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WHvX64RegisterCr8,
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/* X64 Debug Registers */
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/*
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* WHvX64RegisterDr0,
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* WHvX64RegisterDr1,
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* WHvX64RegisterDr2,
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* WHvX64RegisterDr3,
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* WHvX64RegisterDr6,
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* WHvX64RegisterDr7,
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*/
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/* X64 Floating Point and Vector Registers */
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WHvX64RegisterXmm0,
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WHvX64RegisterXmm1,
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WHvX64RegisterXmm2,
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WHvX64RegisterXmm3,
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WHvX64RegisterXmm4,
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WHvX64RegisterXmm5,
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WHvX64RegisterXmm6,
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WHvX64RegisterXmm7,
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WHvX64RegisterXmm8,
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WHvX64RegisterXmm9,
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WHvX64RegisterXmm10,
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WHvX64RegisterXmm11,
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WHvX64RegisterXmm12,
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WHvX64RegisterXmm13,
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WHvX64RegisterXmm14,
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WHvX64RegisterXmm15,
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WHvX64RegisterFpMmx0,
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WHvX64RegisterFpMmx1,
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WHvX64RegisterFpMmx2,
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WHvX64RegisterFpMmx3,
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WHvX64RegisterFpMmx4,
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WHvX64RegisterFpMmx5,
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WHvX64RegisterFpMmx6,
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WHvX64RegisterFpMmx7,
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WHvX64RegisterFpControlStatus,
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WHvX64RegisterXmmControlStatus,
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/* X64 MSRs */
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WHvX64RegisterEfer,
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#ifdef TARGET_X86_64
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WHvX64RegisterKernelGsBase,
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#endif
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WHvX64RegisterApicBase,
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/* WHvX64RegisterPat, */
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WHvX64RegisterSysenterCs,
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WHvX64RegisterSysenterEip,
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WHvX64RegisterSysenterEsp,
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WHvX64RegisterStar,
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#ifdef TARGET_X86_64
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WHvX64RegisterLstar,
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WHvX64RegisterCstar,
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WHvX64RegisterSfmask,
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#endif
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/* Interrupt / Event Registers */
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/*
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* WHvRegisterPendingInterruption,
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* WHvRegisterInterruptState,
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* WHvRegisterPendingEvent0,
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* WHvRegisterPendingEvent1
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* WHvX64RegisterDeliverabilityNotifications,
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*/
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};
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struct whpx_register_set {
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WHV_REGISTER_VALUE values[RTL_NUMBER_OF(whpx_register_names)];
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};
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2022-03-03 02:28:33 +01:00
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/*
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* The current implementation of instruction stepping sets the TF flag
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* in RFLAGS, causing the CPU to raise an INT1 after each instruction.
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* This corresponds to the WHvX64ExceptionTypeDebugTrapOrFault exception.
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*
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* This approach has a few limitations:
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* 1. Stepping over a PUSHF/SAHF instruction will save the TF flag
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* along with the other flags, possibly restoring it later. It would
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* result in another INT1 when the flags are restored, triggering
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* a stop in gdb that could be cleared by doing another step.
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*
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* Stepping over a POPF/LAHF instruction will let it overwrite the
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* TF flags, ending the stepping mode.
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*
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* 2. Stepping over an instruction raising an exception (e.g. INT, DIV,
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* or anything that could result in a page fault) will save the flags
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* to the stack, clear the TF flag, and let the guest execute the
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* handler. Normally, the guest will restore the original flags,
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* that will continue single-stepping.
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*
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* 3. Debuggers running on the guest may wish to set TF to do instruction
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* stepping. INT1 events generated by it would be intercepted by us,
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* as long as the gdb is connected to QEMU.
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*
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* In practice this means that:
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* 1. Stepping through flags-modifying instructions may cause gdb to
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* continue or stop in unexpected places. This will be fully recoverable
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* and will not crash the target.
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*
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* 2. Stepping over an instruction that triggers an exception will step
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* over the exception handler, not into it.
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*
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* 3. Debugging the guest via gdb, while running debugger on the guest
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* at the same time may lead to unexpected effects. Removing all
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* breakpoints set via QEMU will prevent any further interference
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* with the guest-level debuggers.
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*
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* The limitations can be addressed as shown below:
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* 1. PUSHF/SAHF/POPF/LAHF/IRET instructions can be emulated instead of
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* stepping through them. The exact semantics of the instructions is
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* defined in the "Combined Volume Set of Intel 64 and IA-32
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* Architectures Software Developer's Manuals", however it involves a
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* fair amount of corner cases due to compatibility with real mode,
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* virtual 8086 mode, and differences between 64-bit and 32-bit modes.
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*
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* 2. We could step into the guest's exception handlers using the following
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* sequence:
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* a. Temporarily enable catching of all exception types via
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* whpx_set_exception_exit_bitmap().
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* b. Once an exception is intercepted, read the IDT/GDT and locate
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* the original handler.
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* c. Patch the original handler, injecting an INT3 at the beginning.
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* d. Update the exception exit bitmap to only catch the
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* WHvX64ExceptionTypeBreakpointTrap exception.
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* e. Let the affected CPU run in the exclusive mode.
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* f. Restore the original handler and the exception exit bitmap.
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* Note that handling all corner cases related to IDT/GDT is harder
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* than it may seem. See x86_cpu_get_phys_page_attrs_debug() for a
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* rough idea.
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*
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* 3. In order to properly support guest-level debugging in parallel with
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* the QEMU-level debugging, we would need to be able to pass some INT1
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* events to the guest. This could be done via the following methods:
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* a. Using the WHvRegisterPendingEvent register. As of Windows 21H1,
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* it seems to only work for interrupts and not software
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* exceptions.
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* b. Locating and patching the original handler by parsing IDT/GDT.
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* This involves relatively complex logic outlined in the previous
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* paragraph.
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* c. Emulating the exception invocation (i.e. manually updating RIP,
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* RFLAGS, and pushing the old values to stack). This is even more
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* complicated than the previous option, since it involves checking
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* CPL, gate attributes, and doing various adjustments depending
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* on the current CPU mode, whether the CPL is changing, etc.
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*/
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typedef enum WhpxStepMode {
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WHPX_STEP_NONE = 0,
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/* Halt other VCPUs */
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WHPX_STEP_EXCLUSIVE,
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} WhpxStepMode;
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2018-01-22 22:07:48 +01:00
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struct whpx_vcpu {
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WHV_EMULATOR_HANDLE emulator;
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bool window_registered;
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bool interruptable;
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2020-10-28 03:23:19 +01:00
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bool ready_for_pic_interrupt;
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2018-01-22 22:07:48 +01:00
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uint64_t tpr;
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uint64_t apic_base;
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2018-03-14 15:52:43 +01:00
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bool interruption_pending;
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2018-01-22 22:07:48 +01:00
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/* Must be the last field as it may have a tail */
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WHV_RUN_VP_EXIT_CONTEXT exit_ctx;
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};
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static bool whpx_allowed;
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2018-05-15 19:35:21 +02:00
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static bool whp_dispatch_initialized;
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static HMODULE hWinHvPlatform, hWinHvEmulation;
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2020-10-28 03:23:19 +01:00
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static uint32_t max_vcpu_index;
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2019-11-07 20:48:32 +01:00
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static WHV_PROCESSOR_XSAVE_FEATURES whpx_xsave_cap;
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2018-01-22 22:07:48 +01:00
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struct whpx_state whpx_global;
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2018-05-15 19:35:21 +02:00
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struct WHPDispatch whp_dispatch;
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2018-01-22 22:07:48 +01:00
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2019-11-07 20:48:32 +01:00
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static bool whpx_has_xsave(void)
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{
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return whpx_xsave_cap.XsaveSupport;
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}
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2018-01-22 22:07:48 +01:00
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/*
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* VP support
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*/
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static struct whpx_vcpu *get_whpx_vcpu(CPUState *cpu)
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{
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return (struct whpx_vcpu *)cpu->hax_vcpu;
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}
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static WHV_X64_SEGMENT_REGISTER whpx_seg_q2h(const SegmentCache *qs, int v86,
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int r86)
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{
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WHV_X64_SEGMENT_REGISTER hs;
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unsigned flags = qs->flags;
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hs.Base = qs->base;
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hs.Limit = qs->limit;
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hs.Selector = qs->selector;
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if (v86) {
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hs.Attributes = 0;
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hs.SegmentType = 3;
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hs.Present = 1;
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hs.DescriptorPrivilegeLevel = 3;
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hs.NonSystemSegment = 1;
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} else {
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hs.Attributes = (flags >> DESC_TYPE_SHIFT);
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if (r86) {
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/* hs.Base &= 0xfffff; */
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}
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}
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return hs;
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}
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static SegmentCache whpx_seg_h2q(const WHV_X64_SEGMENT_REGISTER *hs)
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{
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SegmentCache qs;
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qs.base = hs->Base;
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qs.limit = hs->Limit;
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qs.selector = hs->Selector;
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qs.flags = ((uint32_t)hs->Attributes) << DESC_TYPE_SHIFT;
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return qs;
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}
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2019-11-07 20:48:32 +01:00
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/* X64 Extended Control Registers */
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static void whpx_set_xcrs(CPUState *cpu)
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{
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CPUX86State *env = cpu->env_ptr;
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HRESULT hr;
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struct whpx_state *whpx = &whpx_global;
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WHV_REGISTER_VALUE xcr0;
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WHV_REGISTER_NAME xcr0_name = WHvX64RegisterXCr0;
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if (!whpx_has_xsave()) {
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return;
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}
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/* Only xcr0 is supported by the hypervisor currently */
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xcr0.Reg64 = env->xcr0;
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hr = whp_dispatch.WHvSetVirtualProcessorRegisters(
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whpx->partition, cpu->cpu_index, &xcr0_name, 1, &xcr0);
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if (FAILED(hr)) {
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error_report("WHPX: Failed to set register xcr0, hr=%08lx", hr);
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}
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}
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2020-02-26 21:54:39 +01:00
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static int whpx_set_tsc(CPUState *cpu)
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{
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2022-03-05 23:35:19 +01:00
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CPUX86State *env = cpu->env_ptr;
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2020-02-26 21:54:39 +01:00
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WHV_REGISTER_NAME tsc_reg = WHvX64RegisterTsc;
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WHV_REGISTER_VALUE tsc_val;
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HRESULT hr;
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struct whpx_state *whpx = &whpx_global;
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/*
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* Suspend the partition prior to setting the TSC to reduce the variance
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* in TSC across vCPUs. When the first vCPU runs post suspend, the
|
|
|
|
* partition is automatically resumed.
|
|
|
|
*/
|
|
|
|
if (whp_dispatch.WHvSuspendPartitionTime) {
|
|
|
|
|
|
|
|
/*
|
|
|
|
* Unable to suspend partition while setting TSC is not a fatal
|
|
|
|
* error. It just increases the likelihood of TSC variance between
|
|
|
|
* vCPUs and some guest OS are able to handle that just fine.
|
|
|
|
*/
|
|
|
|
hr = whp_dispatch.WHvSuspendPartitionTime(whpx->partition);
|
|
|
|
if (FAILED(hr)) {
|
|
|
|
warn_report("WHPX: Failed to suspend partition, hr=%08lx", hr);
|
|
|
|
}
|
|
|
|
}
|
|
|
|
|
|
|
|
tsc_val.Reg64 = env->tsc;
|
|
|
|
hr = whp_dispatch.WHvSetVirtualProcessorRegisters(
|
|
|
|
whpx->partition, cpu->cpu_index, &tsc_reg, 1, &tsc_val);
|
|
|
|
if (FAILED(hr)) {
|
|
|
|
error_report("WHPX: Failed to set TSC, hr=%08lx", hr);
|
|
|
|
return -1;
|
|
|
|
}
|
|
|
|
|
|
|
|
return 0;
|
|
|
|
}
|
|
|
|
|
2022-02-23 06:18:00 +01:00
|
|
|
/*
|
|
|
|
* The CR8 register in the CPU is mapped to the TPR register of the APIC,
|
|
|
|
* however, they use a slightly different encoding. Specifically:
|
|
|
|
*
|
|
|
|
* APIC.TPR[bits 7:4] = CR8[bits 3:0]
|
|
|
|
*
|
|
|
|
* This mechanism is described in section 10.8.6.1 of Volume 3 of Intel 64
|
|
|
|
* and IA-32 Architectures Software Developer's Manual.
|
2022-05-14 07:50:21 +02:00
|
|
|
*
|
|
|
|
* The functions below translate the value of CR8 to TPR and vice versa.
|
2022-02-23 06:18:00 +01:00
|
|
|
*/
|
|
|
|
|
|
|
|
static uint64_t whpx_apic_tpr_to_cr8(uint64_t tpr)
|
|
|
|
{
|
|
|
|
return tpr >> 4;
|
|
|
|
}
|
|
|
|
|
2022-05-14 07:50:21 +02:00
|
|
|
static uint64_t whpx_cr8_to_apic_tpr(uint64_t cr8)
|
|
|
|
{
|
|
|
|
return cr8 << 4;
|
|
|
|
}
|
|
|
|
|
2020-02-26 21:54:39 +01:00
|
|
|
static void whpx_set_registers(CPUState *cpu, int level)
|
2018-01-22 22:07:48 +01:00
|
|
|
{
|
|
|
|
struct whpx_state *whpx = &whpx_global;
|
|
|
|
struct whpx_vcpu *vcpu = get_whpx_vcpu(cpu);
|
2022-03-05 23:35:19 +01:00
|
|
|
CPUX86State *env = cpu->env_ptr;
|
2018-01-22 22:07:48 +01:00
|
|
|
X86CPU *x86_cpu = X86_CPU(cpu);
|
2018-05-15 19:35:22 +02:00
|
|
|
struct whpx_register_set vcxt;
|
2018-01-22 22:07:48 +01:00
|
|
|
HRESULT hr;
|
2018-05-15 19:35:22 +02:00
|
|
|
int idx;
|
|
|
|
int idx_next;
|
2018-01-22 22:07:48 +01:00
|
|
|
int i;
|
|
|
|
int v86, r86;
|
|
|
|
|
|
|
|
assert(cpu_is_stopped(cpu) || qemu_cpu_is_self(cpu));
|
|
|
|
|
2020-02-26 21:54:39 +01:00
|
|
|
/*
|
|
|
|
* Following MSRs have side effects on the guest or are too heavy for
|
|
|
|
* runtime. Limit them to full state update.
|
|
|
|
*/
|
|
|
|
if (level >= WHPX_SET_RESET_STATE) {
|
|
|
|
whpx_set_tsc(cpu);
|
|
|
|
}
|
|
|
|
|
2018-05-15 19:35:22 +02:00
|
|
|
memset(&vcxt, 0, sizeof(struct whpx_register_set));
|
|
|
|
|
2018-01-22 22:07:48 +01:00
|
|
|
v86 = (env->eflags & VM_MASK);
|
|
|
|
r86 = !(env->cr[0] & CR0_PE_MASK);
|
|
|
|
|
2022-02-23 06:18:00 +01:00
|
|
|
vcpu->tpr = whpx_apic_tpr_to_cr8(cpu_get_apic_tpr(x86_cpu->apic_state));
|
2018-01-22 22:07:48 +01:00
|
|
|
vcpu->apic_base = cpu_get_apic_base(x86_cpu->apic_state);
|
|
|
|
|
2018-05-15 19:35:22 +02:00
|
|
|
idx = 0;
|
|
|
|
|
2018-01-22 22:07:48 +01:00
|
|
|
/* Indexes for first 16 registers match between HV and QEMU definitions */
|
2018-05-15 19:35:22 +02:00
|
|
|
idx_next = 16;
|
|
|
|
for (idx = 0; idx < CPU_NB_REGS; idx += 1) {
|
|
|
|
vcxt.values[idx].Reg64 = (uint64_t)env->regs[idx];
|
2018-01-22 22:07:48 +01:00
|
|
|
}
|
2018-05-15 19:35:22 +02:00
|
|
|
idx = idx_next;
|
2018-01-22 22:07:48 +01:00
|
|
|
|
|
|
|
/* Same goes for RIP and RFLAGS */
|
|
|
|
assert(whpx_register_names[idx] == WHvX64RegisterRip);
|
|
|
|
vcxt.values[idx++].Reg64 = env->eip;
|
|
|
|
|
|
|
|
assert(whpx_register_names[idx] == WHvX64RegisterRflags);
|
|
|
|
vcxt.values[idx++].Reg64 = env->eflags;
|
|
|
|
|
|
|
|
/* Translate 6+4 segment registers. HV and QEMU order matches */
|
|
|
|
assert(idx == WHvX64RegisterEs);
|
|
|
|
for (i = 0; i < 6; i += 1, idx += 1) {
|
|
|
|
vcxt.values[idx].Segment = whpx_seg_q2h(&env->segs[i], v86, r86);
|
|
|
|
}
|
|
|
|
|
|
|
|
assert(idx == WHvX64RegisterLdtr);
|
|
|
|
vcxt.values[idx++].Segment = whpx_seg_q2h(&env->ldt, 0, 0);
|
|
|
|
|
|
|
|
assert(idx == WHvX64RegisterTr);
|
|
|
|
vcxt.values[idx++].Segment = whpx_seg_q2h(&env->tr, 0, 0);
|
|
|
|
|
|
|
|
assert(idx == WHvX64RegisterIdtr);
|
|
|
|
vcxt.values[idx].Table.Base = env->idt.base;
|
|
|
|
vcxt.values[idx].Table.Limit = env->idt.limit;
|
|
|
|
idx += 1;
|
|
|
|
|
|
|
|
assert(idx == WHvX64RegisterGdtr);
|
|
|
|
vcxt.values[idx].Table.Base = env->gdt.base;
|
|
|
|
vcxt.values[idx].Table.Limit = env->gdt.limit;
|
|
|
|
idx += 1;
|
|
|
|
|
|
|
|
/* CR0, 2, 3, 4, 8 */
|
|
|
|
assert(whpx_register_names[idx] == WHvX64RegisterCr0);
|
|
|
|
vcxt.values[idx++].Reg64 = env->cr[0];
|
|
|
|
assert(whpx_register_names[idx] == WHvX64RegisterCr2);
|
|
|
|
vcxt.values[idx++].Reg64 = env->cr[2];
|
|
|
|
assert(whpx_register_names[idx] == WHvX64RegisterCr3);
|
|
|
|
vcxt.values[idx++].Reg64 = env->cr[3];
|
|
|
|
assert(whpx_register_names[idx] == WHvX64RegisterCr4);
|
|
|
|
vcxt.values[idx++].Reg64 = env->cr[4];
|
|
|
|
assert(whpx_register_names[idx] == WHvX64RegisterCr8);
|
|
|
|
vcxt.values[idx++].Reg64 = vcpu->tpr;
|
|
|
|
|
|
|
|
/* 8 Debug Registers - Skipped */
|
|
|
|
|
2019-11-07 20:48:32 +01:00
|
|
|
/*
|
|
|
|
* Extended control registers needs to be handled separately depending
|
|
|
|
* on whether xsave is supported/enabled or not.
|
|
|
|
*/
|
|
|
|
whpx_set_xcrs(cpu);
|
|
|
|
|
2018-01-22 22:07:48 +01:00
|
|
|
/* 16 XMM registers */
|
|
|
|
assert(whpx_register_names[idx] == WHvX64RegisterXmm0);
|
2018-05-15 19:35:22 +02:00
|
|
|
idx_next = idx + 16;
|
|
|
|
for (i = 0; i < sizeof(env->xmm_regs) / sizeof(ZMMReg); i += 1, idx += 1) {
|
2018-01-22 22:07:48 +01:00
|
|
|
vcxt.values[idx].Reg128.Low64 = env->xmm_regs[i].ZMM_Q(0);
|
|
|
|
vcxt.values[idx].Reg128.High64 = env->xmm_regs[i].ZMM_Q(1);
|
|
|
|
}
|
2018-05-15 19:35:22 +02:00
|
|
|
idx = idx_next;
|
2018-01-22 22:07:48 +01:00
|
|
|
|
|
|
|
/* 8 FP registers */
|
|
|
|
assert(whpx_register_names[idx] == WHvX64RegisterFpMmx0);
|
|
|
|
for (i = 0; i < 8; i += 1, idx += 1) {
|
|
|
|
vcxt.values[idx].Fp.AsUINT128.Low64 = env->fpregs[i].mmx.MMX_Q(0);
|
|
|
|
/* vcxt.values[idx].Fp.AsUINT128.High64 =
|
|
|
|
env->fpregs[i].mmx.MMX_Q(1);
|
|
|
|
*/
|
|
|
|
}
|
|
|
|
|
|
|
|
/* FP control status register */
|
|
|
|
assert(whpx_register_names[idx] == WHvX64RegisterFpControlStatus);
|
|
|
|
vcxt.values[idx].FpControlStatus.FpControl = env->fpuc;
|
|
|
|
vcxt.values[idx].FpControlStatus.FpStatus =
|
|
|
|
(env->fpus & ~0x3800) | (env->fpstt & 0x7) << 11;
|
|
|
|
vcxt.values[idx].FpControlStatus.FpTag = 0;
|
|
|
|
for (i = 0; i < 8; ++i) {
|
|
|
|
vcxt.values[idx].FpControlStatus.FpTag |= (!env->fptags[i]) << i;
|
|
|
|
}
|
|
|
|
vcxt.values[idx].FpControlStatus.Reserved = 0;
|
|
|
|
vcxt.values[idx].FpControlStatus.LastFpOp = env->fpop;
|
|
|
|
vcxt.values[idx].FpControlStatus.LastFpRip = env->fpip;
|
|
|
|
idx += 1;
|
|
|
|
|
|
|
|
/* XMM control status register */
|
|
|
|
assert(whpx_register_names[idx] == WHvX64RegisterXmmControlStatus);
|
|
|
|
vcxt.values[idx].XmmControlStatus.LastFpRdp = 0;
|
|
|
|
vcxt.values[idx].XmmControlStatus.XmmStatusControl = env->mxcsr;
|
|
|
|
vcxt.values[idx].XmmControlStatus.XmmStatusControlMask = 0x0000ffff;
|
|
|
|
idx += 1;
|
|
|
|
|
|
|
|
/* MSRs */
|
|
|
|
assert(whpx_register_names[idx] == WHvX64RegisterEfer);
|
|
|
|
vcxt.values[idx++].Reg64 = env->efer;
|
|
|
|
#ifdef TARGET_X86_64
|
|
|
|
assert(whpx_register_names[idx] == WHvX64RegisterKernelGsBase);
|
|
|
|
vcxt.values[idx++].Reg64 = env->kernelgsbase;
|
|
|
|
#endif
|
|
|
|
|
|
|
|
assert(whpx_register_names[idx] == WHvX64RegisterApicBase);
|
|
|
|
vcxt.values[idx++].Reg64 = vcpu->apic_base;
|
|
|
|
|
|
|
|
/* WHvX64RegisterPat - Skipped */
|
|
|
|
|
|
|
|
assert(whpx_register_names[idx] == WHvX64RegisterSysenterCs);
|
|
|
|
vcxt.values[idx++].Reg64 = env->sysenter_cs;
|
|
|
|
assert(whpx_register_names[idx] == WHvX64RegisterSysenterEip);
|
|
|
|
vcxt.values[idx++].Reg64 = env->sysenter_eip;
|
|
|
|
assert(whpx_register_names[idx] == WHvX64RegisterSysenterEsp);
|
|
|
|
vcxt.values[idx++].Reg64 = env->sysenter_esp;
|
|
|
|
assert(whpx_register_names[idx] == WHvX64RegisterStar);
|
|
|
|
vcxt.values[idx++].Reg64 = env->star;
|
|
|
|
#ifdef TARGET_X86_64
|
|
|
|
assert(whpx_register_names[idx] == WHvX64RegisterLstar);
|
|
|
|
vcxt.values[idx++].Reg64 = env->lstar;
|
|
|
|
assert(whpx_register_names[idx] == WHvX64RegisterCstar);
|
|
|
|
vcxt.values[idx++].Reg64 = env->cstar;
|
|
|
|
assert(whpx_register_names[idx] == WHvX64RegisterSfmask);
|
|
|
|
vcxt.values[idx++].Reg64 = env->fmask;
|
|
|
|
#endif
|
|
|
|
|
|
|
|
/* Interrupt / Event Registers - Skipped */
|
|
|
|
|
|
|
|
assert(idx == RTL_NUMBER_OF(whpx_register_names));
|
|
|
|
|
2018-05-15 19:35:21 +02:00
|
|
|
hr = whp_dispatch.WHvSetVirtualProcessorRegisters(
|
|
|
|
whpx->partition, cpu->cpu_index,
|
|
|
|
whpx_register_names,
|
|
|
|
RTL_NUMBER_OF(whpx_register_names),
|
|
|
|
&vcxt.values[0]);
|
2018-01-22 22:07:48 +01:00
|
|
|
|
|
|
|
if (FAILED(hr)) {
|
|
|
|
error_report("WHPX: Failed to set virtual processor context, hr=%08lx",
|
|
|
|
hr);
|
|
|
|
}
|
|
|
|
|
|
|
|
return;
|
|
|
|
}
|
|
|
|
|
2020-02-26 21:54:39 +01:00
|
|
|
static int whpx_get_tsc(CPUState *cpu)
|
|
|
|
{
|
2022-03-05 23:35:19 +01:00
|
|
|
CPUX86State *env = cpu->env_ptr;
|
2020-02-26 21:54:39 +01:00
|
|
|
WHV_REGISTER_NAME tsc_reg = WHvX64RegisterTsc;
|
|
|
|
WHV_REGISTER_VALUE tsc_val;
|
|
|
|
HRESULT hr;
|
|
|
|
struct whpx_state *whpx = &whpx_global;
|
|
|
|
|
|
|
|
hr = whp_dispatch.WHvGetVirtualProcessorRegisters(
|
|
|
|
whpx->partition, cpu->cpu_index, &tsc_reg, 1, &tsc_val);
|
|
|
|
if (FAILED(hr)) {
|
|
|
|
error_report("WHPX: Failed to get TSC, hr=%08lx", hr);
|
|
|
|
return -1;
|
|
|
|
}
|
|
|
|
|
|
|
|
env->tsc = tsc_val.Reg64;
|
|
|
|
return 0;
|
|
|
|
}
|
|
|
|
|
2019-11-07 20:48:32 +01:00
|
|
|
/* X64 Extended Control Registers */
|
|
|
|
static void whpx_get_xcrs(CPUState *cpu)
|
|
|
|
{
|
|
|
|
CPUX86State *env = cpu->env_ptr;
|
|
|
|
HRESULT hr;
|
|
|
|
struct whpx_state *whpx = &whpx_global;
|
|
|
|
WHV_REGISTER_VALUE xcr0;
|
|
|
|
WHV_REGISTER_NAME xcr0_name = WHvX64RegisterXCr0;
|
|
|
|
|
|
|
|
if (!whpx_has_xsave()) {
|
|
|
|
return;
|
|
|
|
}
|
|
|
|
|
|
|
|
/* Only xcr0 is supported by the hypervisor currently */
|
|
|
|
hr = whp_dispatch.WHvGetVirtualProcessorRegisters(
|
|
|
|
whpx->partition, cpu->cpu_index, &xcr0_name, 1, &xcr0);
|
|
|
|
if (FAILED(hr)) {
|
|
|
|
error_report("WHPX: Failed to get register xcr0, hr=%08lx", hr);
|
|
|
|
return;
|
|
|
|
}
|
|
|
|
|
|
|
|
env->xcr0 = xcr0.Reg64;
|
|
|
|
}
|
|
|
|
|
2018-01-22 22:07:48 +01:00
|
|
|
static void whpx_get_registers(CPUState *cpu)
|
|
|
|
{
|
|
|
|
struct whpx_state *whpx = &whpx_global;
|
|
|
|
struct whpx_vcpu *vcpu = get_whpx_vcpu(cpu);
|
2022-03-05 23:35:19 +01:00
|
|
|
CPUX86State *env = cpu->env_ptr;
|
2018-01-22 22:07:48 +01:00
|
|
|
X86CPU *x86_cpu = X86_CPU(cpu);
|
|
|
|
struct whpx_register_set vcxt;
|
|
|
|
uint64_t tpr, apic_base;
|
|
|
|
HRESULT hr;
|
2018-05-15 19:35:22 +02:00
|
|
|
int idx;
|
|
|
|
int idx_next;
|
2018-01-22 22:07:48 +01:00
|
|
|
int i;
|
|
|
|
|
|
|
|
assert(cpu_is_stopped(cpu) || qemu_cpu_is_self(cpu));
|
|
|
|
|
2020-02-26 21:54:39 +01:00
|
|
|
if (!env->tsc_valid) {
|
|
|
|
whpx_get_tsc(cpu);
|
|
|
|
env->tsc_valid = !runstate_is_running();
|
|
|
|
}
|
|
|
|
|
2018-05-15 19:35:21 +02:00
|
|
|
hr = whp_dispatch.WHvGetVirtualProcessorRegisters(
|
|
|
|
whpx->partition, cpu->cpu_index,
|
|
|
|
whpx_register_names,
|
|
|
|
RTL_NUMBER_OF(whpx_register_names),
|
|
|
|
&vcxt.values[0]);
|
2018-01-22 22:07:48 +01:00
|
|
|
if (FAILED(hr)) {
|
|
|
|
error_report("WHPX: Failed to get virtual processor context, hr=%08lx",
|
|
|
|
hr);
|
|
|
|
}
|
|
|
|
|
2022-02-23 06:18:00 +01:00
|
|
|
if (whpx_apic_in_platform()) {
|
|
|
|
/*
|
|
|
|
* Fetch the TPR value from the emulated APIC. It may get overwritten
|
|
|
|
* below with the value from CR8 returned by
|
|
|
|
* WHvGetVirtualProcessorRegisters().
|
|
|
|
*/
|
|
|
|
whpx_apic_get(x86_cpu->apic_state);
|
|
|
|
vcpu->tpr = whpx_apic_tpr_to_cr8(
|
|
|
|
cpu_get_apic_tpr(x86_cpu->apic_state));
|
|
|
|
}
|
|
|
|
|
2018-05-15 19:35:22 +02:00
|
|
|
idx = 0;
|
|
|
|
|
2018-01-22 22:07:48 +01:00
|
|
|
/* Indexes for first 16 registers match between HV and QEMU definitions */
|
2018-05-15 19:35:22 +02:00
|
|
|
idx_next = 16;
|
|
|
|
for (idx = 0; idx < CPU_NB_REGS; idx += 1) {
|
2018-01-22 22:07:48 +01:00
|
|
|
env->regs[idx] = vcxt.values[idx].Reg64;
|
|
|
|
}
|
2018-05-15 19:35:22 +02:00
|
|
|
idx = idx_next;
|
2018-01-22 22:07:48 +01:00
|
|
|
|
|
|
|
/* Same goes for RIP and RFLAGS */
|
|
|
|
assert(whpx_register_names[idx] == WHvX64RegisterRip);
|
|
|
|
env->eip = vcxt.values[idx++].Reg64;
|
|
|
|
assert(whpx_register_names[idx] == WHvX64RegisterRflags);
|
|
|
|
env->eflags = vcxt.values[idx++].Reg64;
|
|
|
|
|
|
|
|
/* Translate 6+4 segment registers. HV and QEMU order matches */
|
|
|
|
assert(idx == WHvX64RegisterEs);
|
|
|
|
for (i = 0; i < 6; i += 1, idx += 1) {
|
|
|
|
env->segs[i] = whpx_seg_h2q(&vcxt.values[idx].Segment);
|
|
|
|
}
|
|
|
|
|
|
|
|
assert(idx == WHvX64RegisterLdtr);
|
|
|
|
env->ldt = whpx_seg_h2q(&vcxt.values[idx++].Segment);
|
|
|
|
assert(idx == WHvX64RegisterTr);
|
|
|
|
env->tr = whpx_seg_h2q(&vcxt.values[idx++].Segment);
|
|
|
|
assert(idx == WHvX64RegisterIdtr);
|
|
|
|
env->idt.base = vcxt.values[idx].Table.Base;
|
|
|
|
env->idt.limit = vcxt.values[idx].Table.Limit;
|
|
|
|
idx += 1;
|
|
|
|
assert(idx == WHvX64RegisterGdtr);
|
|
|
|
env->gdt.base = vcxt.values[idx].Table.Base;
|
|
|
|
env->gdt.limit = vcxt.values[idx].Table.Limit;
|
|
|
|
idx += 1;
|
|
|
|
|
|
|
|
/* CR0, 2, 3, 4, 8 */
|
|
|
|
assert(whpx_register_names[idx] == WHvX64RegisterCr0);
|
|
|
|
env->cr[0] = vcxt.values[idx++].Reg64;
|
|
|
|
assert(whpx_register_names[idx] == WHvX64RegisterCr2);
|
|
|
|
env->cr[2] = vcxt.values[idx++].Reg64;
|
|
|
|
assert(whpx_register_names[idx] == WHvX64RegisterCr3);
|
|
|
|
env->cr[3] = vcxt.values[idx++].Reg64;
|
|
|
|
assert(whpx_register_names[idx] == WHvX64RegisterCr4);
|
|
|
|
env->cr[4] = vcxt.values[idx++].Reg64;
|
|
|
|
assert(whpx_register_names[idx] == WHvX64RegisterCr8);
|
|
|
|
tpr = vcxt.values[idx++].Reg64;
|
|
|
|
if (tpr != vcpu->tpr) {
|
|
|
|
vcpu->tpr = tpr;
|
2022-05-14 07:50:21 +02:00
|
|
|
cpu_set_apic_tpr(x86_cpu->apic_state, whpx_cr8_to_apic_tpr(tpr));
|
2018-01-22 22:07:48 +01:00
|
|
|
}
|
|
|
|
|
|
|
|
/* 8 Debug Registers - Skipped */
|
|
|
|
|
2019-11-07 20:48:32 +01:00
|
|
|
/*
|
|
|
|
* Extended control registers needs to be handled separately depending
|
|
|
|
* on whether xsave is supported/enabled or not.
|
|
|
|
*/
|
|
|
|
whpx_get_xcrs(cpu);
|
|
|
|
|
2018-01-22 22:07:48 +01:00
|
|
|
/* 16 XMM registers */
|
|
|
|
assert(whpx_register_names[idx] == WHvX64RegisterXmm0);
|
2018-05-15 19:35:22 +02:00
|
|
|
idx_next = idx + 16;
|
|
|
|
for (i = 0; i < sizeof(env->xmm_regs) / sizeof(ZMMReg); i += 1, idx += 1) {
|
2018-01-22 22:07:48 +01:00
|
|
|
env->xmm_regs[i].ZMM_Q(0) = vcxt.values[idx].Reg128.Low64;
|
|
|
|
env->xmm_regs[i].ZMM_Q(1) = vcxt.values[idx].Reg128.High64;
|
|
|
|
}
|
2018-05-15 19:35:22 +02:00
|
|
|
idx = idx_next;
|
2018-01-22 22:07:48 +01:00
|
|
|
|
|
|
|
/* 8 FP registers */
|
|
|
|
assert(whpx_register_names[idx] == WHvX64RegisterFpMmx0);
|
|
|
|
for (i = 0; i < 8; i += 1, idx += 1) {
|
|
|
|
env->fpregs[i].mmx.MMX_Q(0) = vcxt.values[idx].Fp.AsUINT128.Low64;
|
|
|
|
/* env->fpregs[i].mmx.MMX_Q(1) =
|
|
|
|
vcxt.values[idx].Fp.AsUINT128.High64;
|
|
|
|
*/
|
|
|
|
}
|
|
|
|
|
|
|
|
/* FP control status register */
|
|
|
|
assert(whpx_register_names[idx] == WHvX64RegisterFpControlStatus);
|
|
|
|
env->fpuc = vcxt.values[idx].FpControlStatus.FpControl;
|
|
|
|
env->fpstt = (vcxt.values[idx].FpControlStatus.FpStatus >> 11) & 0x7;
|
|
|
|
env->fpus = vcxt.values[idx].FpControlStatus.FpStatus & ~0x3800;
|
|
|
|
for (i = 0; i < 8; ++i) {
|
|
|
|
env->fptags[i] = !((vcxt.values[idx].FpControlStatus.FpTag >> i) & 1);
|
|
|
|
}
|
|
|
|
env->fpop = vcxt.values[idx].FpControlStatus.LastFpOp;
|
|
|
|
env->fpip = vcxt.values[idx].FpControlStatus.LastFpRip;
|
|
|
|
idx += 1;
|
|
|
|
|
|
|
|
/* XMM control status register */
|
|
|
|
assert(whpx_register_names[idx] == WHvX64RegisterXmmControlStatus);
|
|
|
|
env->mxcsr = vcxt.values[idx].XmmControlStatus.XmmStatusControl;
|
|
|
|
idx += 1;
|
|
|
|
|
|
|
|
/* MSRs */
|
|
|
|
assert(whpx_register_names[idx] == WHvX64RegisterEfer);
|
|
|
|
env->efer = vcxt.values[idx++].Reg64;
|
|
|
|
#ifdef TARGET_X86_64
|
|
|
|
assert(whpx_register_names[idx] == WHvX64RegisterKernelGsBase);
|
|
|
|
env->kernelgsbase = vcxt.values[idx++].Reg64;
|
|
|
|
#endif
|
|
|
|
|
|
|
|
assert(whpx_register_names[idx] == WHvX64RegisterApicBase);
|
|
|
|
apic_base = vcxt.values[idx++].Reg64;
|
|
|
|
if (apic_base != vcpu->apic_base) {
|
|
|
|
vcpu->apic_base = apic_base;
|
|
|
|
cpu_set_apic_base(x86_cpu->apic_state, vcpu->apic_base);
|
|
|
|
}
|
|
|
|
|
|
|
|
/* WHvX64RegisterPat - Skipped */
|
|
|
|
|
|
|
|
assert(whpx_register_names[idx] == WHvX64RegisterSysenterCs);
|
2020-02-18 10:44:00 +01:00
|
|
|
env->sysenter_cs = vcxt.values[idx++].Reg64;
|
2018-01-22 22:07:48 +01:00
|
|
|
assert(whpx_register_names[idx] == WHvX64RegisterSysenterEip);
|
|
|
|
env->sysenter_eip = vcxt.values[idx++].Reg64;
|
|
|
|
assert(whpx_register_names[idx] == WHvX64RegisterSysenterEsp);
|
|
|
|
env->sysenter_esp = vcxt.values[idx++].Reg64;
|
|
|
|
assert(whpx_register_names[idx] == WHvX64RegisterStar);
|
|
|
|
env->star = vcxt.values[idx++].Reg64;
|
|
|
|
#ifdef TARGET_X86_64
|
|
|
|
assert(whpx_register_names[idx] == WHvX64RegisterLstar);
|
|
|
|
env->lstar = vcxt.values[idx++].Reg64;
|
|
|
|
assert(whpx_register_names[idx] == WHvX64RegisterCstar);
|
|
|
|
env->cstar = vcxt.values[idx++].Reg64;
|
|
|
|
assert(whpx_register_names[idx] == WHvX64RegisterSfmask);
|
|
|
|
env->fmask = vcxt.values[idx++].Reg64;
|
|
|
|
#endif
|
|
|
|
|
|
|
|
/* Interrupt / Event Registers - Skipped */
|
|
|
|
|
|
|
|
assert(idx == RTL_NUMBER_OF(whpx_register_names));
|
|
|
|
|
2020-10-28 03:23:19 +01:00
|
|
|
if (whpx_apic_in_platform()) {
|
|
|
|
whpx_apic_get(x86_cpu->apic_state);
|
|
|
|
}
|
|
|
|
|
2022-02-23 06:15:41 +01:00
|
|
|
x86_update_hflags(env);
|
|
|
|
|
2018-01-22 22:07:48 +01:00
|
|
|
return;
|
|
|
|
}
|
|
|
|
|
|
|
|
static HRESULT CALLBACK whpx_emu_ioport_callback(
|
|
|
|
void *ctx,
|
|
|
|
WHV_EMULATOR_IO_ACCESS_INFO *IoAccess)
|
|
|
|
{
|
|
|
|
MemTxAttrs attrs = { 0 };
|
|
|
|
address_space_rw(&address_space_io, IoAccess->Port, attrs,
|
2020-02-19 20:28:22 +01:00
|
|
|
&IoAccess->Data, IoAccess->AccessSize,
|
2018-01-22 22:07:48 +01:00
|
|
|
IoAccess->Direction);
|
|
|
|
return S_OK;
|
|
|
|
}
|
|
|
|
|
2018-02-26 18:13:33 +01:00
|
|
|
static HRESULT CALLBACK whpx_emu_mmio_callback(
|
2018-01-22 22:07:48 +01:00
|
|
|
void *ctx,
|
|
|
|
WHV_EMULATOR_MEMORY_ACCESS_INFO *ma)
|
|
|
|
{
|
|
|
|
cpu_physical_memory_rw(ma->GpaAddress, ma->Data, ma->AccessSize,
|
|
|
|
ma->Direction);
|
|
|
|
return S_OK;
|
|
|
|
}
|
|
|
|
|
|
|
|
static HRESULT CALLBACK whpx_emu_getreg_callback(
|
|
|
|
void *ctx,
|
|
|
|
const WHV_REGISTER_NAME *RegisterNames,
|
|
|
|
UINT32 RegisterCount,
|
|
|
|
WHV_REGISTER_VALUE *RegisterValues)
|
|
|
|
{
|
|
|
|
HRESULT hr;
|
|
|
|
struct whpx_state *whpx = &whpx_global;
|
|
|
|
CPUState *cpu = (CPUState *)ctx;
|
|
|
|
|
2018-05-15 19:35:21 +02:00
|
|
|
hr = whp_dispatch.WHvGetVirtualProcessorRegisters(
|
|
|
|
whpx->partition, cpu->cpu_index,
|
|
|
|
RegisterNames, RegisterCount,
|
|
|
|
RegisterValues);
|
2018-01-22 22:07:48 +01:00
|
|
|
if (FAILED(hr)) {
|
|
|
|
error_report("WHPX: Failed to get virtual processor registers,"
|
|
|
|
" hr=%08lx", hr);
|
|
|
|
}
|
|
|
|
|
|
|
|
return hr;
|
|
|
|
}
|
|
|
|
|
|
|
|
static HRESULT CALLBACK whpx_emu_setreg_callback(
|
|
|
|
void *ctx,
|
|
|
|
const WHV_REGISTER_NAME *RegisterNames,
|
|
|
|
UINT32 RegisterCount,
|
|
|
|
const WHV_REGISTER_VALUE *RegisterValues)
|
|
|
|
{
|
|
|
|
HRESULT hr;
|
|
|
|
struct whpx_state *whpx = &whpx_global;
|
|
|
|
CPUState *cpu = (CPUState *)ctx;
|
|
|
|
|
2018-05-15 19:35:21 +02:00
|
|
|
hr = whp_dispatch.WHvSetVirtualProcessorRegisters(
|
|
|
|
whpx->partition, cpu->cpu_index,
|
|
|
|
RegisterNames, RegisterCount,
|
|
|
|
RegisterValues);
|
2018-01-22 22:07:48 +01:00
|
|
|
if (FAILED(hr)) {
|
|
|
|
error_report("WHPX: Failed to set virtual processor registers,"
|
|
|
|
" hr=%08lx", hr);
|
|
|
|
}
|
|
|
|
|
|
|
|
/*
|
|
|
|
* The emulator just successfully wrote the register state. We clear the
|
|
|
|
* dirty state so we avoid the double write on resume of the VP.
|
|
|
|
*/
|
|
|
|
cpu->vcpu_dirty = false;
|
|
|
|
|
|
|
|
return hr;
|
|
|
|
}
|
|
|
|
|
|
|
|
static HRESULT CALLBACK whpx_emu_translate_callback(
|
|
|
|
void *ctx,
|
|
|
|
WHV_GUEST_VIRTUAL_ADDRESS Gva,
|
|
|
|
WHV_TRANSLATE_GVA_FLAGS TranslateFlags,
|
|
|
|
WHV_TRANSLATE_GVA_RESULT_CODE *TranslationResult,
|
|
|
|
WHV_GUEST_PHYSICAL_ADDRESS *Gpa)
|
|
|
|
{
|
|
|
|
HRESULT hr;
|
|
|
|
struct whpx_state *whpx = &whpx_global;
|
|
|
|
CPUState *cpu = (CPUState *)ctx;
|
|
|
|
WHV_TRANSLATE_GVA_RESULT res;
|
|
|
|
|
2018-05-15 19:35:21 +02:00
|
|
|
hr = whp_dispatch.WHvTranslateGva(whpx->partition, cpu->cpu_index,
|
|
|
|
Gva, TranslateFlags, &res, Gpa);
|
2018-01-22 22:07:48 +01:00
|
|
|
if (FAILED(hr)) {
|
|
|
|
error_report("WHPX: Failed to translate GVA, hr=%08lx", hr);
|
|
|
|
} else {
|
|
|
|
*TranslationResult = res.ResultCode;
|
|
|
|
}
|
|
|
|
|
|
|
|
return hr;
|
|
|
|
}
|
|
|
|
|
|
|
|
static const WHV_EMULATOR_CALLBACKS whpx_emu_callbacks = {
|
2018-02-26 18:13:30 +01:00
|
|
|
.Size = sizeof(WHV_EMULATOR_CALLBACKS),
|
2018-01-22 22:07:48 +01:00
|
|
|
.WHvEmulatorIoPortCallback = whpx_emu_ioport_callback,
|
2018-02-26 18:13:33 +01:00
|
|
|
.WHvEmulatorMemoryCallback = whpx_emu_mmio_callback,
|
2018-01-22 22:07:48 +01:00
|
|
|
.WHvEmulatorGetVirtualProcessorRegisters = whpx_emu_getreg_callback,
|
|
|
|
.WHvEmulatorSetVirtualProcessorRegisters = whpx_emu_setreg_callback,
|
|
|
|
.WHvEmulatorTranslateGvaPage = whpx_emu_translate_callback,
|
|
|
|
};
|
|
|
|
|
|
|
|
static int whpx_handle_mmio(CPUState *cpu, WHV_MEMORY_ACCESS_CONTEXT *ctx)
|
|
|
|
{
|
|
|
|
HRESULT hr;
|
|
|
|
struct whpx_vcpu *vcpu = get_whpx_vcpu(cpu);
|
|
|
|
WHV_EMULATOR_STATUS emu_status;
|
|
|
|
|
2018-05-15 19:35:21 +02:00
|
|
|
hr = whp_dispatch.WHvEmulatorTryMmioEmulation(
|
|
|
|
vcpu->emulator, cpu,
|
|
|
|
&vcpu->exit_ctx.VpContext, ctx,
|
|
|
|
&emu_status);
|
2018-01-22 22:07:48 +01:00
|
|
|
if (FAILED(hr)) {
|
|
|
|
error_report("WHPX: Failed to parse MMIO access, hr=%08lx", hr);
|
|
|
|
return -1;
|
|
|
|
}
|
|
|
|
|
|
|
|
if (!emu_status.EmulationSuccessful) {
|
2018-05-15 19:35:21 +02:00
|
|
|
error_report("WHPX: Failed to emulate MMIO access with"
|
|
|
|
" EmulatorReturnStatus: %u", emu_status.AsUINT32);
|
2018-01-22 22:07:48 +01:00
|
|
|
return -1;
|
|
|
|
}
|
|
|
|
|
|
|
|
return 0;
|
|
|
|
}
|
|
|
|
|
|
|
|
static int whpx_handle_portio(CPUState *cpu,
|
|
|
|
WHV_X64_IO_PORT_ACCESS_CONTEXT *ctx)
|
|
|
|
{
|
|
|
|
HRESULT hr;
|
|
|
|
struct whpx_vcpu *vcpu = get_whpx_vcpu(cpu);
|
|
|
|
WHV_EMULATOR_STATUS emu_status;
|
|
|
|
|
2018-05-15 19:35:21 +02:00
|
|
|
hr = whp_dispatch.WHvEmulatorTryIoEmulation(
|
|
|
|
vcpu->emulator, cpu,
|
|
|
|
&vcpu->exit_ctx.VpContext, ctx,
|
|
|
|
&emu_status);
|
2018-01-22 22:07:48 +01:00
|
|
|
if (FAILED(hr)) {
|
|
|
|
error_report("WHPX: Failed to parse PortIO access, hr=%08lx", hr);
|
|
|
|
return -1;
|
|
|
|
}
|
|
|
|
|
|
|
|
if (!emu_status.EmulationSuccessful) {
|
2018-05-15 19:35:21 +02:00
|
|
|
error_report("WHPX: Failed to emulate PortIO access with"
|
|
|
|
" EmulatorReturnStatus: %u", emu_status.AsUINT32);
|
2018-01-22 22:07:48 +01:00
|
|
|
return -1;
|
|
|
|
}
|
|
|
|
|
|
|
|
return 0;
|
|
|
|
}
|
|
|
|
|
2022-03-03 02:28:33 +01:00
|
|
|
/*
|
|
|
|
* Controls whether we should intercept various exceptions on the guest,
|
|
|
|
* namely breakpoint/single-step events.
|
|
|
|
*
|
|
|
|
* The 'exceptions' argument accepts a bitmask, e.g:
|
|
|
|
* (1 << WHvX64ExceptionTypeDebugTrapOrFault) | (...)
|
|
|
|
*/
|
|
|
|
static HRESULT whpx_set_exception_exit_bitmap(UINT64 exceptions)
|
|
|
|
{
|
|
|
|
struct whpx_state *whpx = &whpx_global;
|
|
|
|
WHV_PARTITION_PROPERTY prop = { 0, };
|
|
|
|
HRESULT hr;
|
|
|
|
|
|
|
|
if (exceptions == whpx->exception_exit_bitmap) {
|
|
|
|
return S_OK;
|
|
|
|
}
|
|
|
|
|
|
|
|
prop.ExceptionExitBitmap = exceptions;
|
|
|
|
|
|
|
|
hr = whp_dispatch.WHvSetPartitionProperty(
|
|
|
|
whpx->partition,
|
|
|
|
WHvPartitionPropertyCodeExceptionExitBitmap,
|
|
|
|
&prop,
|
|
|
|
sizeof(WHV_PARTITION_PROPERTY));
|
|
|
|
|
|
|
|
if (SUCCEEDED(hr)) {
|
|
|
|
whpx->exception_exit_bitmap = exceptions;
|
|
|
|
}
|
|
|
|
|
|
|
|
return hr;
|
|
|
|
}
|
|
|
|
|
|
|
|
|
|
|
|
/*
|
|
|
|
* This function is called before/after stepping over a single instruction.
|
|
|
|
* It will update the CPU registers to arm/disarm the instruction stepping
|
|
|
|
* accordingly.
|
|
|
|
*/
|
|
|
|
static HRESULT whpx_vcpu_configure_single_stepping(CPUState *cpu,
|
|
|
|
bool set,
|
|
|
|
uint64_t *exit_context_rflags)
|
|
|
|
{
|
|
|
|
WHV_REGISTER_NAME reg_name;
|
|
|
|
WHV_REGISTER_VALUE reg_value;
|
|
|
|
HRESULT hr;
|
|
|
|
struct whpx_state *whpx = &whpx_global;
|
|
|
|
|
|
|
|
/*
|
|
|
|
* If we are trying to step over a single instruction, we need to set the
|
|
|
|
* TF bit in rflags. Otherwise, clear it.
|
|
|
|
*/
|
|
|
|
reg_name = WHvX64RegisterRflags;
|
|
|
|
hr = whp_dispatch.WHvGetVirtualProcessorRegisters(
|
|
|
|
whpx->partition,
|
|
|
|
cpu->cpu_index,
|
|
|
|
®_name,
|
|
|
|
1,
|
|
|
|
®_value);
|
|
|
|
|
|
|
|
if (FAILED(hr)) {
|
|
|
|
error_report("WHPX: Failed to get rflags, hr=%08lx", hr);
|
|
|
|
return hr;
|
|
|
|
}
|
|
|
|
|
|
|
|
if (exit_context_rflags) {
|
|
|
|
assert(*exit_context_rflags == reg_value.Reg64);
|
|
|
|
}
|
|
|
|
|
|
|
|
if (set) {
|
|
|
|
/* Raise WHvX64ExceptionTypeDebugTrapOrFault after each instruction */
|
|
|
|
reg_value.Reg64 |= TF_MASK;
|
|
|
|
} else {
|
|
|
|
reg_value.Reg64 &= ~TF_MASK;
|
|
|
|
}
|
|
|
|
|
|
|
|
if (exit_context_rflags) {
|
|
|
|
*exit_context_rflags = reg_value.Reg64;
|
|
|
|
}
|
|
|
|
|
|
|
|
hr = whp_dispatch.WHvSetVirtualProcessorRegisters(
|
|
|
|
whpx->partition,
|
|
|
|
cpu->cpu_index,
|
|
|
|
®_name,
|
|
|
|
1,
|
|
|
|
®_value);
|
|
|
|
|
|
|
|
if (FAILED(hr)) {
|
|
|
|
error_report("WHPX: Failed to set rflags,"
|
|
|
|
" hr=%08lx",
|
|
|
|
hr);
|
|
|
|
return hr;
|
|
|
|
}
|
|
|
|
|
|
|
|
reg_name = WHvRegisterInterruptState;
|
|
|
|
reg_value.Reg64 = 0;
|
|
|
|
|
|
|
|
/* Suspend delivery of hardware interrupts during single-stepping. */
|
|
|
|
reg_value.InterruptState.InterruptShadow = set != 0;
|
|
|
|
|
|
|
|
hr = whp_dispatch.WHvSetVirtualProcessorRegisters(
|
|
|
|
whpx->partition,
|
|
|
|
cpu->cpu_index,
|
|
|
|
®_name,
|
|
|
|
1,
|
|
|
|
®_value);
|
|
|
|
|
|
|
|
if (FAILED(hr)) {
|
|
|
|
error_report("WHPX: Failed to set InterruptState,"
|
|
|
|
" hr=%08lx",
|
|
|
|
hr);
|
|
|
|
return hr;
|
|
|
|
}
|
|
|
|
|
|
|
|
if (!set) {
|
|
|
|
/*
|
|
|
|
* We have just finished stepping over a single instruction,
|
|
|
|
* and intercepted the INT1 generated by it.
|
|
|
|
* We need to now hide the INT1 from the guest,
|
|
|
|
* as it would not be expecting it.
|
|
|
|
*/
|
|
|
|
|
|
|
|
reg_name = WHvX64RegisterPendingDebugException;
|
|
|
|
hr = whp_dispatch.WHvGetVirtualProcessorRegisters(
|
|
|
|
whpx->partition,
|
|
|
|
cpu->cpu_index,
|
|
|
|
®_name,
|
|
|
|
1,
|
|
|
|
®_value);
|
|
|
|
|
|
|
|
if (FAILED(hr)) {
|
|
|
|
error_report("WHPX: Failed to get pending debug exceptions,"
|
|
|
|
"hr=%08lx", hr);
|
|
|
|
return hr;
|
|
|
|
}
|
|
|
|
|
|
|
|
if (reg_value.PendingDebugException.SingleStep) {
|
|
|
|
reg_value.PendingDebugException.SingleStep = 0;
|
|
|
|
|
|
|
|
hr = whp_dispatch.WHvSetVirtualProcessorRegisters(
|
|
|
|
whpx->partition,
|
|
|
|
cpu->cpu_index,
|
|
|
|
®_name,
|
|
|
|
1,
|
|
|
|
®_value);
|
|
|
|
|
|
|
|
if (FAILED(hr)) {
|
|
|
|
error_report("WHPX: Failed to clear pending debug exceptions,"
|
|
|
|
"hr=%08lx", hr);
|
|
|
|
return hr;
|
|
|
|
}
|
|
|
|
}
|
|
|
|
|
|
|
|
}
|
|
|
|
|
|
|
|
return S_OK;
|
|
|
|
}
|
|
|
|
|
|
|
|
/* Tries to find a breakpoint at the specified address. */
|
|
|
|
static struct whpx_breakpoint *whpx_lookup_breakpoint_by_addr(uint64_t address)
|
|
|
|
{
|
|
|
|
struct whpx_state *whpx = &whpx_global;
|
|
|
|
int i;
|
|
|
|
|
|
|
|
if (whpx->breakpoints.breakpoints) {
|
|
|
|
for (i = 0; i < whpx->breakpoints.breakpoints->used; i++) {
|
|
|
|
if (address == whpx->breakpoints.breakpoints->data[i].address) {
|
|
|
|
return &whpx->breakpoints.breakpoints->data[i];
|
|
|
|
}
|
|
|
|
}
|
|
|
|
}
|
|
|
|
|
|
|
|
return NULL;
|
|
|
|
}
|
|
|
|
|
|
|
|
/*
|
|
|
|
* Linux uses int3 (0xCC) during startup (see int3_selftest()) and for
|
|
|
|
* debugging user-mode applications. Since the WHPX API does not offer
|
|
|
|
* an easy way to pass the intercepted exception back to the guest, we
|
|
|
|
* resort to using INT1 instead, and let the guest always handle INT3.
|
|
|
|
*/
|
|
|
|
static const uint8_t whpx_breakpoint_instruction = 0xF1;
|
|
|
|
|
|
|
|
/*
|
|
|
|
* The WHPX QEMU backend implements breakpoints by writing the INT1
|
|
|
|
* instruction into memory (ignoring the DRx registers). This raises a few
|
|
|
|
* issues that need to be carefully handled:
|
|
|
|
*
|
|
|
|
* 1. Although unlikely, other parts of QEMU may set multiple breakpoints
|
|
|
|
* at the same location, and later remove them in arbitrary order.
|
|
|
|
* This should not cause memory corruption, and should only remove the
|
|
|
|
* physical breakpoint instruction when the last QEMU breakpoint is gone.
|
|
|
|
*
|
|
|
|
* 2. Writing arbitrary virtual memory may fail if it's not mapped to a valid
|
|
|
|
* physical location. Hence, physically adding/removing a breakpoint can
|
|
|
|
* theoretically fail at any time. We need to keep track of it.
|
|
|
|
*
|
|
|
|
* The function below rebuilds a list of low-level breakpoints (one per
|
|
|
|
* address, tracking the original instruction and any errors) from the list of
|
|
|
|
* high-level breakpoints (set via cpu_breakpoint_insert()).
|
|
|
|
*
|
|
|
|
* In order to optimize performance, this function stores the list of
|
|
|
|
* high-level breakpoints (a.k.a. CPU breakpoints) used to compute the
|
|
|
|
* low-level ones, so that it won't be re-invoked until these breakpoints
|
|
|
|
* change.
|
|
|
|
*
|
|
|
|
* Note that this function decides which breakpoints should be inserted into,
|
|
|
|
* memory, but doesn't actually do it. The memory accessing is done in
|
|
|
|
* whpx_apply_breakpoints().
|
|
|
|
*/
|
|
|
|
static void whpx_translate_cpu_breakpoints(
|
|
|
|
struct whpx_breakpoints *breakpoints,
|
|
|
|
CPUState *cpu,
|
|
|
|
int cpu_breakpoint_count)
|
|
|
|
{
|
|
|
|
CPUBreakpoint *bp;
|
|
|
|
int cpu_bp_index = 0;
|
|
|
|
|
|
|
|
breakpoints->original_addresses =
|
|
|
|
g_renew(vaddr, breakpoints->original_addresses, cpu_breakpoint_count);
|
|
|
|
|
|
|
|
breakpoints->original_address_count = cpu_breakpoint_count;
|
|
|
|
|
|
|
|
int max_breakpoints = cpu_breakpoint_count +
|
|
|
|
(breakpoints->breakpoints ? breakpoints->breakpoints->used : 0);
|
|
|
|
|
|
|
|
struct whpx_breakpoint_collection *new_breakpoints =
|
|
|
|
(struct whpx_breakpoint_collection *)g_malloc0(
|
|
|
|
sizeof(struct whpx_breakpoint_collection) +
|
|
|
|
max_breakpoints * sizeof(struct whpx_breakpoint));
|
|
|
|
|
|
|
|
new_breakpoints->allocated = max_breakpoints;
|
|
|
|
new_breakpoints->used = 0;
|
|
|
|
|
|
|
|
/*
|
|
|
|
* 1. Preserve all old breakpoints that could not be automatically
|
|
|
|
* cleared when the CPU got stopped.
|
|
|
|
*/
|
|
|
|
if (breakpoints->breakpoints) {
|
|
|
|
int i;
|
|
|
|
for (i = 0; i < breakpoints->breakpoints->used; i++) {
|
|
|
|
if (breakpoints->breakpoints->data[i].state != WHPX_BP_CLEARED) {
|
|
|
|
new_breakpoints->data[new_breakpoints->used++] =
|
|
|
|
breakpoints->breakpoints->data[i];
|
|
|
|
}
|
|
|
|
}
|
|
|
|
}
|
|
|
|
|
|
|
|
/* 2. Map all CPU breakpoints to WHPX breakpoints */
|
|
|
|
QTAILQ_FOREACH(bp, &cpu->breakpoints, entry) {
|
|
|
|
int i;
|
|
|
|
bool found = false;
|
|
|
|
|
|
|
|
/* This will be used to detect changed CPU breakpoints later. */
|
|
|
|
breakpoints->original_addresses[cpu_bp_index++] = bp->pc;
|
|
|
|
|
|
|
|
for (i = 0; i < new_breakpoints->used; i++) {
|
|
|
|
/*
|
|
|
|
* WARNING: This loop has O(N^2) complexity, where N is the
|
|
|
|
* number of breakpoints. It should not be a bottleneck in
|
|
|
|
* real-world scenarios, since it only needs to run once after
|
|
|
|
* the breakpoints have been modified.
|
|
|
|
* If this ever becomes a concern, it can be optimized by storing
|
|
|
|
* high-level breakpoint objects in a tree or hash map.
|
|
|
|
*/
|
|
|
|
|
|
|
|
if (new_breakpoints->data[i].address == bp->pc) {
|
|
|
|
/* There was already a breakpoint at this address. */
|
|
|
|
if (new_breakpoints->data[i].state == WHPX_BP_CLEAR_PENDING) {
|
|
|
|
new_breakpoints->data[i].state = WHPX_BP_SET;
|
|
|
|
} else if (new_breakpoints->data[i].state == WHPX_BP_SET) {
|
|
|
|
new_breakpoints->data[i].state = WHPX_BP_SET_PENDING;
|
|
|
|
}
|
|
|
|
|
|
|
|
found = true;
|
|
|
|
break;
|
|
|
|
}
|
|
|
|
}
|
|
|
|
|
|
|
|
if (!found && new_breakpoints->used < new_breakpoints->allocated) {
|
|
|
|
/* No WHPX breakpoint at this address. Create one. */
|
|
|
|
new_breakpoints->data[new_breakpoints->used].address = bp->pc;
|
|
|
|
new_breakpoints->data[new_breakpoints->used].state =
|
|
|
|
WHPX_BP_SET_PENDING;
|
|
|
|
new_breakpoints->used++;
|
|
|
|
}
|
|
|
|
}
|
|
|
|
|
|
|
|
if (breakpoints->breakpoints) {
|
|
|
|
/*
|
|
|
|
* Free the previous breakpoint list. This can be optimized by keeping
|
|
|
|
* it as shadow buffer for the next computation instead of freeing
|
|
|
|
* it immediately.
|
|
|
|
*/
|
|
|
|
g_free(breakpoints->breakpoints);
|
|
|
|
}
|
|
|
|
|
|
|
|
breakpoints->breakpoints = new_breakpoints;
|
|
|
|
}
|
|
|
|
|
|
|
|
/*
|
|
|
|
* Physically inserts/removes the breakpoints by reading and writing the
|
|
|
|
* physical memory, keeping a track of the failed attempts.
|
|
|
|
*
|
|
|
|
* Passing resuming=true will try to set all previously unset breakpoints.
|
|
|
|
* Passing resuming=false will remove all inserted ones.
|
|
|
|
*/
|
|
|
|
static void whpx_apply_breakpoints(
|
|
|
|
struct whpx_breakpoint_collection *breakpoints,
|
|
|
|
CPUState *cpu,
|
|
|
|
bool resuming)
|
|
|
|
{
|
|
|
|
int i, rc;
|
|
|
|
if (!breakpoints) {
|
|
|
|
return;
|
|
|
|
}
|
|
|
|
|
|
|
|
for (i = 0; i < breakpoints->used; i++) {
|
|
|
|
/* Decide what to do right now based on the last known state. */
|
|
|
|
WhpxBreakpointState state = breakpoints->data[i].state;
|
|
|
|
switch (state) {
|
|
|
|
case WHPX_BP_CLEARED:
|
|
|
|
if (resuming) {
|
|
|
|
state = WHPX_BP_SET_PENDING;
|
|
|
|
}
|
|
|
|
break;
|
|
|
|
case WHPX_BP_SET_PENDING:
|
|
|
|
if (!resuming) {
|
|
|
|
state = WHPX_BP_CLEARED;
|
|
|
|
}
|
|
|
|
break;
|
|
|
|
case WHPX_BP_SET:
|
|
|
|
if (!resuming) {
|
|
|
|
state = WHPX_BP_CLEAR_PENDING;
|
|
|
|
}
|
|
|
|
break;
|
|
|
|
case WHPX_BP_CLEAR_PENDING:
|
|
|
|
if (resuming) {
|
|
|
|
state = WHPX_BP_SET;
|
|
|
|
}
|
|
|
|
break;
|
|
|
|
}
|
|
|
|
|
|
|
|
if (state == WHPX_BP_SET_PENDING) {
|
|
|
|
/* Remember the original instruction. */
|
|
|
|
rc = cpu_memory_rw_debug(cpu,
|
|
|
|
breakpoints->data[i].address,
|
|
|
|
&breakpoints->data[i].original_instruction,
|
|
|
|
1,
|
|
|
|
false);
|
|
|
|
|
|
|
|
if (!rc) {
|
|
|
|
/* Write the breakpoint instruction. */
|
|
|
|
rc = cpu_memory_rw_debug(cpu,
|
|
|
|
breakpoints->data[i].address,
|
|
|
|
(void *)&whpx_breakpoint_instruction,
|
|
|
|
1,
|
|
|
|
true);
|
|
|
|
}
|
|
|
|
|
|
|
|
if (!rc) {
|
|
|
|
state = WHPX_BP_SET;
|
|
|
|
}
|
|
|
|
|
|
|
|
}
|
|
|
|
|
|
|
|
if (state == WHPX_BP_CLEAR_PENDING) {
|
|
|
|
/* Restore the original instruction. */
|
|
|
|
rc = cpu_memory_rw_debug(cpu,
|
|
|
|
breakpoints->data[i].address,
|
|
|
|
&breakpoints->data[i].original_instruction,
|
|
|
|
1,
|
|
|
|
true);
|
|
|
|
|
|
|
|
if (!rc) {
|
|
|
|
state = WHPX_BP_CLEARED;
|
|
|
|
}
|
|
|
|
}
|
|
|
|
|
|
|
|
breakpoints->data[i].state = state;
|
|
|
|
}
|
|
|
|
}
|
|
|
|
|
|
|
|
/*
|
|
|
|
* This function is called when the a VCPU is about to start and no other
|
|
|
|
* VCPUs have been started so far. Since the VCPU start order could be
|
|
|
|
* arbitrary, it doesn't have to be VCPU#0.
|
|
|
|
*
|
|
|
|
* It is used to commit the breakpoints into memory, and configure WHPX
|
|
|
|
* to intercept debug exceptions.
|
|
|
|
*
|
|
|
|
* Note that whpx_set_exception_exit_bitmap() cannot be called if one or
|
|
|
|
* more VCPUs are already running, so this is the best place to do it.
|
|
|
|
*/
|
|
|
|
static int whpx_first_vcpu_starting(CPUState *cpu)
|
|
|
|
{
|
|
|
|
struct whpx_state *whpx = &whpx_global;
|
|
|
|
HRESULT hr;
|
|
|
|
|
|
|
|
g_assert(qemu_mutex_iothread_locked());
|
|
|
|
|
|
|
|
if (!QTAILQ_EMPTY(&cpu->breakpoints) ||
|
|
|
|
(whpx->breakpoints.breakpoints &&
|
|
|
|
whpx->breakpoints.breakpoints->used)) {
|
|
|
|
CPUBreakpoint *bp;
|
|
|
|
int i = 0;
|
|
|
|
bool update_pending = false;
|
|
|
|
|
|
|
|
QTAILQ_FOREACH(bp, &cpu->breakpoints, entry) {
|
|
|
|
if (i >= whpx->breakpoints.original_address_count ||
|
|
|
|
bp->pc != whpx->breakpoints.original_addresses[i]) {
|
|
|
|
update_pending = true;
|
|
|
|
}
|
|
|
|
|
|
|
|
i++;
|
|
|
|
}
|
|
|
|
|
|
|
|
if (i != whpx->breakpoints.original_address_count) {
|
|
|
|
update_pending = true;
|
|
|
|
}
|
|
|
|
|
|
|
|
if (update_pending) {
|
|
|
|
/*
|
|
|
|
* The CPU breakpoints have changed since the last call to
|
|
|
|
* whpx_translate_cpu_breakpoints(). WHPX breakpoints must
|
|
|
|
* now be recomputed.
|
|
|
|
*/
|
|
|
|
whpx_translate_cpu_breakpoints(&whpx->breakpoints, cpu, i);
|
|
|
|
}
|
|
|
|
|
|
|
|
/* Actually insert the breakpoints into the memory. */
|
|
|
|
whpx_apply_breakpoints(whpx->breakpoints.breakpoints, cpu, true);
|
|
|
|
}
|
|
|
|
|
|
|
|
uint64_t exception_mask;
|
|
|
|
if (whpx->step_pending ||
|
|
|
|
(whpx->breakpoints.breakpoints &&
|
|
|
|
whpx->breakpoints.breakpoints->used)) {
|
|
|
|
/*
|
|
|
|
* We are either attempting to single-step one or more CPUs, or
|
|
|
|
* have one or more breakpoints enabled. Both require intercepting
|
|
|
|
* the WHvX64ExceptionTypeBreakpointTrap exception.
|
|
|
|
*/
|
|
|
|
|
|
|
|
exception_mask = 1UL << WHvX64ExceptionTypeDebugTrapOrFault;
|
|
|
|
} else {
|
|
|
|
/* Let the guest handle all exceptions. */
|
|
|
|
exception_mask = 0;
|
|
|
|
}
|
|
|
|
|
|
|
|
hr = whpx_set_exception_exit_bitmap(exception_mask);
|
|
|
|
if (!SUCCEEDED(hr)) {
|
|
|
|
error_report("WHPX: Failed to update exception exit mask,"
|
|
|
|
"hr=%08lx.", hr);
|
|
|
|
return 1;
|
|
|
|
}
|
|
|
|
|
|
|
|
return 0;
|
|
|
|
}
|
|
|
|
|
|
|
|
/*
|
|
|
|
* This function is called when the last VCPU has finished running.
|
|
|
|
* It is used to remove any previously set breakpoints from memory.
|
|
|
|
*/
|
|
|
|
static int whpx_last_vcpu_stopping(CPUState *cpu)
|
|
|
|
{
|
|
|
|
whpx_apply_breakpoints(whpx_global.breakpoints.breakpoints, cpu, false);
|
|
|
|
return 0;
|
|
|
|
}
|
|
|
|
|
|
|
|
/* Returns the address of the next instruction that is about to be executed. */
|
|
|
|
static vaddr whpx_vcpu_get_pc(CPUState *cpu, bool exit_context_valid)
|
|
|
|
{
|
|
|
|
if (cpu->vcpu_dirty) {
|
|
|
|
/* The CPU registers have been modified by other parts of QEMU. */
|
|
|
|
CPUArchState *env = (CPUArchState *)(cpu->env_ptr);
|
|
|
|
return env->eip;
|
|
|
|
} else if (exit_context_valid) {
|
|
|
|
/*
|
|
|
|
* The CPU registers have not been modified by neither other parts
|
|
|
|
* of QEMU, nor this port by calling WHvSetVirtualProcessorRegisters().
|
|
|
|
* This is the most common case.
|
|
|
|
*/
|
|
|
|
struct whpx_vcpu *vcpu = get_whpx_vcpu(cpu);
|
|
|
|
return vcpu->exit_ctx.VpContext.Rip;
|
|
|
|
} else {
|
|
|
|
/*
|
|
|
|
* The CPU registers have been modified by a call to
|
|
|
|
* WHvSetVirtualProcessorRegisters() and must be re-queried from
|
|
|
|
* the target.
|
|
|
|
*/
|
|
|
|
WHV_REGISTER_VALUE reg_value;
|
|
|
|
WHV_REGISTER_NAME reg_name = WHvX64RegisterRip;
|
|
|
|
HRESULT hr;
|
|
|
|
struct whpx_state *whpx = &whpx_global;
|
|
|
|
|
|
|
|
hr = whp_dispatch.WHvGetVirtualProcessorRegisters(
|
|
|
|
whpx->partition,
|
|
|
|
cpu->cpu_index,
|
|
|
|
®_name,
|
|
|
|
1,
|
|
|
|
®_value);
|
|
|
|
|
|
|
|
if (FAILED(hr)) {
|
|
|
|
error_report("WHPX: Failed to get PC, hr=%08lx", hr);
|
|
|
|
return 0;
|
|
|
|
}
|
|
|
|
|
|
|
|
return reg_value.Reg64;
|
|
|
|
}
|
|
|
|
}
|
|
|
|
|
2018-01-22 22:07:48 +01:00
|
|
|
static int whpx_handle_halt(CPUState *cpu)
|
|
|
|
{
|
2022-03-05 23:35:19 +01:00
|
|
|
CPUX86State *env = cpu->env_ptr;
|
2018-01-22 22:07:48 +01:00
|
|
|
int ret = 0;
|
|
|
|
|
|
|
|
qemu_mutex_lock_iothread();
|
|
|
|
if (!((cpu->interrupt_request & CPU_INTERRUPT_HARD) &&
|
|
|
|
(env->eflags & IF_MASK)) &&
|
|
|
|
!(cpu->interrupt_request & CPU_INTERRUPT_NMI)) {
|
|
|
|
cpu->exception_index = EXCP_HLT;
|
|
|
|
cpu->halted = true;
|
|
|
|
ret = 1;
|
|
|
|
}
|
|
|
|
qemu_mutex_unlock_iothread();
|
|
|
|
|
|
|
|
return ret;
|
|
|
|
}
|
|
|
|
|
|
|
|
static void whpx_vcpu_pre_run(CPUState *cpu)
|
|
|
|
{
|
|
|
|
HRESULT hr;
|
|
|
|
struct whpx_state *whpx = &whpx_global;
|
|
|
|
struct whpx_vcpu *vcpu = get_whpx_vcpu(cpu);
|
2022-03-05 23:35:19 +01:00
|
|
|
CPUX86State *env = cpu->env_ptr;
|
2018-01-22 22:07:48 +01:00
|
|
|
X86CPU *x86_cpu = X86_CPU(cpu);
|
|
|
|
int irq;
|
2018-02-26 18:13:34 +01:00
|
|
|
uint8_t tpr;
|
2018-05-15 19:35:22 +02:00
|
|
|
WHV_X64_PENDING_INTERRUPTION_REGISTER new_int;
|
2018-01-22 22:07:48 +01:00
|
|
|
UINT32 reg_count = 0;
|
2018-05-15 19:35:22 +02:00
|
|
|
WHV_REGISTER_VALUE reg_values[3];
|
2018-01-22 22:07:48 +01:00
|
|
|
WHV_REGISTER_NAME reg_names[3];
|
|
|
|
|
2018-05-15 19:35:22 +02:00
|
|
|
memset(&new_int, 0, sizeof(new_int));
|
|
|
|
memset(reg_values, 0, sizeof(reg_values));
|
|
|
|
|
2018-01-22 22:07:48 +01:00
|
|
|
qemu_mutex_lock_iothread();
|
|
|
|
|
|
|
|
/* Inject NMI */
|
2018-03-14 15:52:43 +01:00
|
|
|
if (!vcpu->interruption_pending &&
|
2018-01-22 22:07:48 +01:00
|
|
|
cpu->interrupt_request & (CPU_INTERRUPT_NMI | CPU_INTERRUPT_SMI)) {
|
|
|
|
if (cpu->interrupt_request & CPU_INTERRUPT_NMI) {
|
|
|
|
cpu->interrupt_request &= ~CPU_INTERRUPT_NMI;
|
|
|
|
vcpu->interruptable = false;
|
|
|
|
new_int.InterruptionType = WHvX64PendingNmi;
|
|
|
|
new_int.InterruptionPending = 1;
|
|
|
|
new_int.InterruptionVector = 2;
|
|
|
|
}
|
|
|
|
if (cpu->interrupt_request & CPU_INTERRUPT_SMI) {
|
|
|
|
cpu->interrupt_request &= ~CPU_INTERRUPT_SMI;
|
|
|
|
}
|
|
|
|
}
|
|
|
|
|
|
|
|
/*
|
|
|
|
* Force the VCPU out of its inner loop to process any INIT requests or
|
|
|
|
* commit pending TPR access.
|
|
|
|
*/
|
|
|
|
if (cpu->interrupt_request & (CPU_INTERRUPT_INIT | CPU_INTERRUPT_TPR)) {
|
|
|
|
if ((cpu->interrupt_request & CPU_INTERRUPT_INIT) &&
|
|
|
|
!(env->hflags & HF_SMM_MASK)) {
|
|
|
|
cpu->exit_request = 1;
|
|
|
|
}
|
|
|
|
if (cpu->interrupt_request & CPU_INTERRUPT_TPR) {
|
|
|
|
cpu->exit_request = 1;
|
|
|
|
}
|
|
|
|
}
|
|
|
|
|
|
|
|
/* Get pending hard interruption or replay one that was overwritten */
|
2020-10-28 03:23:19 +01:00
|
|
|
if (!whpx_apic_in_platform()) {
|
|
|
|
if (!vcpu->interruption_pending &&
|
|
|
|
vcpu->interruptable && (env->eflags & IF_MASK)) {
|
|
|
|
assert(!new_int.InterruptionPending);
|
|
|
|
if (cpu->interrupt_request & CPU_INTERRUPT_HARD) {
|
|
|
|
cpu->interrupt_request &= ~CPU_INTERRUPT_HARD;
|
|
|
|
irq = cpu_get_pic_interrupt(env);
|
|
|
|
if (irq >= 0) {
|
|
|
|
new_int.InterruptionType = WHvX64PendingInterrupt;
|
|
|
|
new_int.InterruptionPending = 1;
|
|
|
|
new_int.InterruptionVector = irq;
|
|
|
|
}
|
2018-01-22 22:07:48 +01:00
|
|
|
}
|
|
|
|
}
|
|
|
|
|
2020-10-28 03:23:19 +01:00
|
|
|
/* Setup interrupt state if new one was prepared */
|
|
|
|
if (new_int.InterruptionPending) {
|
|
|
|
reg_values[reg_count].PendingInterruption = new_int;
|
|
|
|
reg_names[reg_count] = WHvRegisterPendingInterruption;
|
|
|
|
reg_count += 1;
|
|
|
|
}
|
|
|
|
} else if (vcpu->ready_for_pic_interrupt &&
|
|
|
|
(cpu->interrupt_request & CPU_INTERRUPT_HARD)) {
|
|
|
|
cpu->interrupt_request &= ~CPU_INTERRUPT_HARD;
|
|
|
|
irq = cpu_get_pic_interrupt(env);
|
|
|
|
if (irq >= 0) {
|
|
|
|
reg_names[reg_count] = WHvRegisterPendingEvent;
|
|
|
|
reg_values[reg_count].ExtIntEvent = (WHV_X64_PENDING_EXT_INT_EVENT)
|
|
|
|
{
|
|
|
|
.EventPending = 1,
|
|
|
|
.EventType = WHvX64PendingEventExtInt,
|
|
|
|
.Vector = irq,
|
|
|
|
};
|
|
|
|
reg_count += 1;
|
|
|
|
}
|
|
|
|
}
|
2018-01-22 22:07:48 +01:00
|
|
|
|
|
|
|
/* Sync the TPR to the CR8 if was modified during the intercept */
|
2022-05-14 07:50:21 +02:00
|
|
|
tpr = whpx_apic_tpr_to_cr8(cpu_get_apic_tpr(x86_cpu->apic_state));
|
2018-02-26 18:13:34 +01:00
|
|
|
if (tpr != vcpu->tpr) {
|
|
|
|
vcpu->tpr = tpr;
|
|
|
|
reg_values[reg_count].Reg64 = tpr;
|
2018-01-22 22:07:48 +01:00
|
|
|
cpu->exit_request = 1;
|
|
|
|
reg_names[reg_count] = WHvX64RegisterCr8;
|
|
|
|
reg_count += 1;
|
|
|
|
}
|
|
|
|
|
|
|
|
/* Update the state of the interrupt delivery notification */
|
2018-02-26 18:13:36 +01:00
|
|
|
if (!vcpu->window_registered &&
|
|
|
|
cpu->interrupt_request & CPU_INTERRUPT_HARD) {
|
2020-10-28 03:23:19 +01:00
|
|
|
reg_values[reg_count].DeliverabilityNotifications =
|
|
|
|
(WHV_X64_DELIVERABILITY_NOTIFICATIONS_REGISTER) {
|
|
|
|
.InterruptNotification = 1
|
|
|
|
};
|
2018-02-26 18:13:36 +01:00
|
|
|
vcpu->window_registered = 1;
|
2018-01-22 22:07:48 +01:00
|
|
|
reg_names[reg_count] = WHvX64RegisterDeliverabilityNotifications;
|
|
|
|
reg_count += 1;
|
|
|
|
}
|
|
|
|
|
|
|
|
qemu_mutex_unlock_iothread();
|
2020-10-28 03:23:19 +01:00
|
|
|
vcpu->ready_for_pic_interrupt = false;
|
2018-01-22 22:07:48 +01:00
|
|
|
|
|
|
|
if (reg_count) {
|
2018-05-15 19:35:21 +02:00
|
|
|
hr = whp_dispatch.WHvSetVirtualProcessorRegisters(
|
|
|
|
whpx->partition, cpu->cpu_index,
|
|
|
|
reg_names, reg_count, reg_values);
|
2018-01-22 22:07:48 +01:00
|
|
|
if (FAILED(hr)) {
|
|
|
|
error_report("WHPX: Failed to set interrupt state registers,"
|
|
|
|
" hr=%08lx", hr);
|
|
|
|
}
|
|
|
|
}
|
|
|
|
|
|
|
|
return;
|
|
|
|
}
|
|
|
|
|
|
|
|
static void whpx_vcpu_post_run(CPUState *cpu)
|
|
|
|
{
|
|
|
|
struct whpx_vcpu *vcpu = get_whpx_vcpu(cpu);
|
2022-03-05 23:35:19 +01:00
|
|
|
CPUX86State *env = cpu->env_ptr;
|
2018-01-22 22:07:48 +01:00
|
|
|
X86CPU *x86_cpu = X86_CPU(cpu);
|
|
|
|
|
2018-03-14 15:52:43 +01:00
|
|
|
env->eflags = vcpu->exit_ctx.VpContext.Rflags;
|
2018-01-22 22:07:48 +01:00
|
|
|
|
2018-03-14 15:52:43 +01:00
|
|
|
uint64_t tpr = vcpu->exit_ctx.VpContext.Cr8;
|
|
|
|
if (vcpu->tpr != tpr) {
|
|
|
|
vcpu->tpr = tpr;
|
2018-01-22 22:07:48 +01:00
|
|
|
qemu_mutex_lock_iothread();
|
2022-05-14 07:50:21 +02:00
|
|
|
cpu_set_apic_tpr(x86_cpu->apic_state, whpx_cr8_to_apic_tpr(vcpu->tpr));
|
2018-01-22 22:07:48 +01:00
|
|
|
qemu_mutex_unlock_iothread();
|
|
|
|
}
|
|
|
|
|
2018-03-14 15:52:43 +01:00
|
|
|
vcpu->interruption_pending =
|
|
|
|
vcpu->exit_ctx.VpContext.ExecutionState.InterruptionPending;
|
2018-01-22 22:07:48 +01:00
|
|
|
|
2018-03-14 15:52:43 +01:00
|
|
|
vcpu->interruptable =
|
|
|
|
!vcpu->exit_ctx.VpContext.ExecutionState.InterruptShadow;
|
2018-01-22 22:07:48 +01:00
|
|
|
|
|
|
|
return;
|
|
|
|
}
|
|
|
|
|
|
|
|
static void whpx_vcpu_process_async_events(CPUState *cpu)
|
|
|
|
{
|
2022-03-05 23:35:19 +01:00
|
|
|
CPUX86State *env = cpu->env_ptr;
|
2018-01-22 22:07:48 +01:00
|
|
|
X86CPU *x86_cpu = X86_CPU(cpu);
|
|
|
|
struct whpx_vcpu *vcpu = get_whpx_vcpu(cpu);
|
|
|
|
|
|
|
|
if ((cpu->interrupt_request & CPU_INTERRUPT_INIT) &&
|
|
|
|
!(env->hflags & HF_SMM_MASK)) {
|
2020-02-24 20:27:38 +01:00
|
|
|
whpx_cpu_synchronize_state(cpu);
|
2018-01-22 22:07:48 +01:00
|
|
|
do_cpu_init(x86_cpu);
|
|
|
|
vcpu->interruptable = true;
|
|
|
|
}
|
|
|
|
|
|
|
|
if (cpu->interrupt_request & CPU_INTERRUPT_POLL) {
|
|
|
|
cpu->interrupt_request &= ~CPU_INTERRUPT_POLL;
|
|
|
|
apic_poll_irq(x86_cpu->apic_state);
|
|
|
|
}
|
|
|
|
|
|
|
|
if (((cpu->interrupt_request & CPU_INTERRUPT_HARD) &&
|
|
|
|
(env->eflags & IF_MASK)) ||
|
|
|
|
(cpu->interrupt_request & CPU_INTERRUPT_NMI)) {
|
|
|
|
cpu->halted = false;
|
|
|
|
}
|
|
|
|
|
|
|
|
if (cpu->interrupt_request & CPU_INTERRUPT_SIPI) {
|
2020-02-24 20:27:38 +01:00
|
|
|
whpx_cpu_synchronize_state(cpu);
|
2018-01-22 22:07:48 +01:00
|
|
|
do_cpu_sipi(x86_cpu);
|
|
|
|
}
|
|
|
|
|
|
|
|
if (cpu->interrupt_request & CPU_INTERRUPT_TPR) {
|
|
|
|
cpu->interrupt_request &= ~CPU_INTERRUPT_TPR;
|
2020-02-24 20:27:38 +01:00
|
|
|
whpx_cpu_synchronize_state(cpu);
|
2018-01-22 22:07:48 +01:00
|
|
|
apic_handle_tpr_access_report(x86_cpu->apic_state, env->eip,
|
|
|
|
env->tpr_access_type);
|
|
|
|
}
|
|
|
|
|
|
|
|
return;
|
|
|
|
}
|
|
|
|
|
|
|
|
static int whpx_vcpu_run(CPUState *cpu)
|
|
|
|
{
|
|
|
|
HRESULT hr;
|
|
|
|
struct whpx_state *whpx = &whpx_global;
|
|
|
|
struct whpx_vcpu *vcpu = get_whpx_vcpu(cpu);
|
2022-03-03 02:28:33 +01:00
|
|
|
struct whpx_breakpoint *stepped_over_bp = NULL;
|
|
|
|
WhpxStepMode exclusive_step_mode = WHPX_STEP_NONE;
|
2018-01-22 22:07:48 +01:00
|
|
|
int ret;
|
|
|
|
|
2022-03-03 02:28:33 +01:00
|
|
|
g_assert(qemu_mutex_iothread_locked());
|
|
|
|
|
|
|
|
if (whpx->running_cpus++ == 0) {
|
|
|
|
/* Insert breakpoints into memory, update exception exit bitmap. */
|
|
|
|
ret = whpx_first_vcpu_starting(cpu);
|
|
|
|
if (ret != 0) {
|
|
|
|
return ret;
|
|
|
|
}
|
|
|
|
}
|
|
|
|
|
|
|
|
if (whpx->breakpoints.breakpoints &&
|
|
|
|
whpx->breakpoints.breakpoints->used > 0)
|
|
|
|
{
|
|
|
|
uint64_t pc = whpx_vcpu_get_pc(cpu, true);
|
|
|
|
stepped_over_bp = whpx_lookup_breakpoint_by_addr(pc);
|
|
|
|
if (stepped_over_bp && stepped_over_bp->state != WHPX_BP_SET) {
|
|
|
|
stepped_over_bp = NULL;
|
|
|
|
}
|
|
|
|
|
|
|
|
if (stepped_over_bp) {
|
|
|
|
/*
|
|
|
|
* We are trying to run the instruction overwritten by an active
|
|
|
|
* breakpoint. We will temporarily disable the breakpoint, suspend
|
|
|
|
* other CPUs, and step over the instruction.
|
|
|
|
*/
|
|
|
|
exclusive_step_mode = WHPX_STEP_EXCLUSIVE;
|
|
|
|
}
|
|
|
|
}
|
|
|
|
|
|
|
|
if (exclusive_step_mode == WHPX_STEP_NONE) {
|
|
|
|
whpx_vcpu_process_async_events(cpu);
|
|
|
|
if (cpu->halted && !whpx_apic_in_platform()) {
|
|
|
|
cpu->exception_index = EXCP_HLT;
|
|
|
|
qatomic_set(&cpu->exit_request, false);
|
|
|
|
return 0;
|
|
|
|
}
|
2018-01-22 22:07:48 +01:00
|
|
|
}
|
|
|
|
|
|
|
|
qemu_mutex_unlock_iothread();
|
2022-03-03 02:28:33 +01:00
|
|
|
|
|
|
|
if (exclusive_step_mode != WHPX_STEP_NONE) {
|
|
|
|
start_exclusive();
|
|
|
|
g_assert(cpu == current_cpu);
|
|
|
|
g_assert(!cpu->running);
|
|
|
|
cpu->running = true;
|
|
|
|
|
|
|
|
hr = whpx_set_exception_exit_bitmap(
|
|
|
|
1UL << WHvX64ExceptionTypeDebugTrapOrFault);
|
|
|
|
if (!SUCCEEDED(hr)) {
|
|
|
|
error_report("WHPX: Failed to update exception exit mask, "
|
|
|
|
"hr=%08lx.", hr);
|
|
|
|
return 1;
|
|
|
|
}
|
|
|
|
|
|
|
|
if (stepped_over_bp) {
|
|
|
|
/* Temporarily disable the triggered breakpoint. */
|
|
|
|
cpu_memory_rw_debug(cpu,
|
|
|
|
stepped_over_bp->address,
|
|
|
|
&stepped_over_bp->original_instruction,
|
|
|
|
1,
|
|
|
|
true);
|
|
|
|
}
|
|
|
|
} else {
|
|
|
|
cpu_exec_start(cpu);
|
|
|
|
}
|
2018-01-22 22:07:48 +01:00
|
|
|
|
|
|
|
do {
|
|
|
|
if (cpu->vcpu_dirty) {
|
2020-02-26 21:54:39 +01:00
|
|
|
whpx_set_registers(cpu, WHPX_SET_RUNTIME_STATE);
|
2018-01-22 22:07:48 +01:00
|
|
|
cpu->vcpu_dirty = false;
|
|
|
|
}
|
|
|
|
|
2022-03-03 02:28:33 +01:00
|
|
|
if (exclusive_step_mode == WHPX_STEP_NONE) {
|
|
|
|
whpx_vcpu_pre_run(cpu);
|
|
|
|
|
|
|
|
if (qatomic_read(&cpu->exit_request)) {
|
|
|
|
whpx_vcpu_kick(cpu);
|
|
|
|
}
|
|
|
|
}
|
2018-01-22 22:07:48 +01:00
|
|
|
|
2022-03-03 02:28:33 +01:00
|
|
|
if (exclusive_step_mode != WHPX_STEP_NONE || cpu->singlestep_enabled) {
|
|
|
|
whpx_vcpu_configure_single_stepping(cpu, true, NULL);
|
2018-01-22 22:07:48 +01:00
|
|
|
}
|
|
|
|
|
2018-05-15 19:35:21 +02:00
|
|
|
hr = whp_dispatch.WHvRunVirtualProcessor(
|
|
|
|
whpx->partition, cpu->cpu_index,
|
|
|
|
&vcpu->exit_ctx, sizeof(vcpu->exit_ctx));
|
2018-01-22 22:07:48 +01:00
|
|
|
|
|
|
|
if (FAILED(hr)) {
|
|
|
|
error_report("WHPX: Failed to exec a virtual processor,"
|
|
|
|
" hr=%08lx", hr);
|
|
|
|
ret = -1;
|
|
|
|
break;
|
|
|
|
}
|
|
|
|
|
2022-03-03 02:28:33 +01:00
|
|
|
if (exclusive_step_mode != WHPX_STEP_NONE || cpu->singlestep_enabled) {
|
|
|
|
whpx_vcpu_configure_single_stepping(cpu,
|
|
|
|
false,
|
|
|
|
&vcpu->exit_ctx.VpContext.Rflags);
|
|
|
|
}
|
|
|
|
|
2018-01-22 22:07:48 +01:00
|
|
|
whpx_vcpu_post_run(cpu);
|
|
|
|
|
|
|
|
switch (vcpu->exit_ctx.ExitReason) {
|
|
|
|
case WHvRunVpExitReasonMemoryAccess:
|
|
|
|
ret = whpx_handle_mmio(cpu, &vcpu->exit_ctx.MemoryAccess);
|
|
|
|
break;
|
|
|
|
|
|
|
|
case WHvRunVpExitReasonX64IoPortAccess:
|
|
|
|
ret = whpx_handle_portio(cpu, &vcpu->exit_ctx.IoPortAccess);
|
|
|
|
break;
|
|
|
|
|
|
|
|
case WHvRunVpExitReasonX64InterruptWindow:
|
2020-10-28 03:23:19 +01:00
|
|
|
vcpu->ready_for_pic_interrupt = 1;
|
2018-01-22 22:07:48 +01:00
|
|
|
vcpu->window_registered = 0;
|
2018-06-06 00:15:28 +02:00
|
|
|
ret = 0;
|
2018-01-22 22:07:48 +01:00
|
|
|
break;
|
|
|
|
|
2020-10-28 03:23:19 +01:00
|
|
|
case WHvRunVpExitReasonX64ApicEoi:
|
|
|
|
assert(whpx_apic_in_platform());
|
|
|
|
ioapic_eoi_broadcast(vcpu->exit_ctx.ApicEoi.InterruptVector);
|
|
|
|
break;
|
|
|
|
|
2018-01-22 22:07:48 +01:00
|
|
|
case WHvRunVpExitReasonX64Halt:
|
2022-03-03 02:28:33 +01:00
|
|
|
/*
|
|
|
|
* WARNING: as of build 19043.1526 (21H1), this exit reason is no
|
|
|
|
* longer used.
|
|
|
|
*/
|
2018-01-22 22:07:48 +01:00
|
|
|
ret = whpx_handle_halt(cpu);
|
|
|
|
break;
|
|
|
|
|
2020-10-28 03:23:19 +01:00
|
|
|
case WHvRunVpExitReasonX64ApicInitSipiTrap: {
|
|
|
|
WHV_INTERRUPT_CONTROL ipi = {0};
|
|
|
|
uint64_t icr = vcpu->exit_ctx.ApicInitSipi.ApicIcr;
|
|
|
|
uint32_t delivery_mode =
|
|
|
|
(icr & APIC_ICR_DELIV_MOD) >> APIC_ICR_DELIV_MOD_SHIFT;
|
|
|
|
int dest_shorthand =
|
|
|
|
(icr & APIC_ICR_DEST_SHORT) >> APIC_ICR_DEST_SHORT_SHIFT;
|
|
|
|
bool broadcast = false;
|
|
|
|
bool include_self = false;
|
|
|
|
uint32_t i;
|
|
|
|
|
|
|
|
/* We only registered for INIT and SIPI exits. */
|
|
|
|
if ((delivery_mode != APIC_DM_INIT) &&
|
|
|
|
(delivery_mode != APIC_DM_SIPI)) {
|
|
|
|
error_report(
|
|
|
|
"WHPX: Unexpected APIC exit that is not a INIT or SIPI");
|
|
|
|
break;
|
|
|
|
}
|
|
|
|
|
|
|
|
if (delivery_mode == APIC_DM_INIT) {
|
|
|
|
ipi.Type = WHvX64InterruptTypeInit;
|
|
|
|
} else {
|
|
|
|
ipi.Type = WHvX64InterruptTypeSipi;
|
|
|
|
}
|
|
|
|
|
|
|
|
ipi.DestinationMode =
|
|
|
|
((icr & APIC_ICR_DEST_MOD) >> APIC_ICR_DEST_MOD_SHIFT) ?
|
|
|
|
WHvX64InterruptDestinationModeLogical :
|
|
|
|
WHvX64InterruptDestinationModePhysical;
|
|
|
|
|
|
|
|
ipi.TriggerMode =
|
|
|
|
((icr & APIC_ICR_TRIGGER_MOD) >> APIC_ICR_TRIGGER_MOD_SHIFT) ?
|
|
|
|
WHvX64InterruptTriggerModeLevel :
|
|
|
|
WHvX64InterruptTriggerModeEdge;
|
|
|
|
|
|
|
|
ipi.Vector = icr & APIC_VECTOR_MASK;
|
|
|
|
switch (dest_shorthand) {
|
|
|
|
/* no shorthand. Bits 56-63 contain the destination. */
|
|
|
|
case 0:
|
|
|
|
ipi.Destination = (icr >> 56) & APIC_VECTOR_MASK;
|
|
|
|
hr = whp_dispatch.WHvRequestInterrupt(whpx->partition,
|
|
|
|
&ipi, sizeof(ipi));
|
|
|
|
if (FAILED(hr)) {
|
|
|
|
error_report("WHPX: Failed to request interrupt hr=%08lx",
|
|
|
|
hr);
|
|
|
|
}
|
|
|
|
|
|
|
|
break;
|
|
|
|
|
|
|
|
/* self */
|
|
|
|
case 1:
|
|
|
|
include_self = true;
|
|
|
|
break;
|
|
|
|
|
|
|
|
/* broadcast, including self */
|
|
|
|
case 2:
|
|
|
|
broadcast = true;
|
|
|
|
include_self = true;
|
|
|
|
break;
|
|
|
|
|
|
|
|
/* broadcast, excluding self */
|
|
|
|
case 3:
|
|
|
|
broadcast = true;
|
|
|
|
break;
|
|
|
|
}
|
|
|
|
|
|
|
|
if (!broadcast && !include_self) {
|
|
|
|
break;
|
|
|
|
}
|
|
|
|
|
|
|
|
for (i = 0; i <= max_vcpu_index; i++) {
|
|
|
|
if (i == cpu->cpu_index && !include_self) {
|
|
|
|
continue;
|
|
|
|
}
|
|
|
|
|
|
|
|
/*
|
|
|
|
* Assuming that APIC Ids are identity mapped since
|
|
|
|
* WHvX64RegisterApicId & WHvX64RegisterInitialApicId registers
|
|
|
|
* are not handled yet and the hypervisor doesn't allow the
|
|
|
|
* guest to modify the APIC ID.
|
|
|
|
*/
|
|
|
|
ipi.Destination = i;
|
|
|
|
hr = whp_dispatch.WHvRequestInterrupt(whpx->partition,
|
|
|
|
&ipi, sizeof(ipi));
|
|
|
|
if (FAILED(hr)) {
|
|
|
|
error_report(
|
|
|
|
"WHPX: Failed to request SIPI for %d, hr=%08lx",
|
|
|
|
i, hr);
|
|
|
|
}
|
|
|
|
}
|
|
|
|
|
|
|
|
break;
|
|
|
|
}
|
|
|
|
|
2018-01-22 22:07:48 +01:00
|
|
|
case WHvRunVpExitReasonCanceled:
|
2022-03-03 02:28:33 +01:00
|
|
|
if (exclusive_step_mode != WHPX_STEP_NONE) {
|
|
|
|
/*
|
|
|
|
* We are trying to step over a single instruction, and
|
|
|
|
* likely got a request to stop from another thread.
|
|
|
|
* Delay it until we are done stepping
|
|
|
|
* over.
|
|
|
|
*/
|
|
|
|
ret = 0;
|
|
|
|
} else {
|
|
|
|
cpu->exception_index = EXCP_INTERRUPT;
|
|
|
|
ret = 1;
|
|
|
|
}
|
2018-01-22 22:07:48 +01:00
|
|
|
break;
|
2018-06-06 00:15:28 +02:00
|
|
|
case WHvRunVpExitReasonX64MsrAccess: {
|
|
|
|
WHV_REGISTER_VALUE reg_values[3] = {0};
|
|
|
|
WHV_REGISTER_NAME reg_names[3];
|
|
|
|
UINT32 reg_count;
|
|
|
|
|
|
|
|
reg_names[0] = WHvX64RegisterRip;
|
|
|
|
reg_names[1] = WHvX64RegisterRax;
|
|
|
|
reg_names[2] = WHvX64RegisterRdx;
|
|
|
|
|
|
|
|
reg_values[0].Reg64 =
|
|
|
|
vcpu->exit_ctx.VpContext.Rip +
|
|
|
|
vcpu->exit_ctx.VpContext.InstructionLength;
|
|
|
|
|
|
|
|
/*
|
|
|
|
* For all unsupported MSR access we:
|
|
|
|
* ignore writes
|
|
|
|
* return 0 on read.
|
|
|
|
*/
|
|
|
|
reg_count = vcpu->exit_ctx.MsrAccess.AccessInfo.IsWrite ?
|
|
|
|
1 : 3;
|
|
|
|
|
|
|
|
hr = whp_dispatch.WHvSetVirtualProcessorRegisters(
|
|
|
|
whpx->partition,
|
|
|
|
cpu->cpu_index,
|
|
|
|
reg_names, reg_count,
|
|
|
|
reg_values);
|
|
|
|
|
|
|
|
if (FAILED(hr)) {
|
|
|
|
error_report("WHPX: Failed to set MsrAccess state "
|
|
|
|
" registers, hr=%08lx", hr);
|
|
|
|
}
|
|
|
|
ret = 0;
|
|
|
|
break;
|
|
|
|
}
|
2018-03-26 19:06:58 +02:00
|
|
|
case WHvRunVpExitReasonX64Cpuid: {
|
2018-05-15 19:35:22 +02:00
|
|
|
WHV_REGISTER_VALUE reg_values[5];
|
2018-03-26 19:06:58 +02:00
|
|
|
WHV_REGISTER_NAME reg_names[5];
|
|
|
|
UINT32 reg_count = 5;
|
2020-02-27 22:01:04 +01:00
|
|
|
UINT64 cpuid_fn, rip = 0, rax = 0, rcx = 0, rdx = 0, rbx = 0;
|
|
|
|
X86CPU *x86_cpu = X86_CPU(cpu);
|
|
|
|
CPUX86State *env = &x86_cpu->env;
|
2018-03-26 19:06:58 +02:00
|
|
|
|
2018-05-15 19:35:22 +02:00
|
|
|
memset(reg_values, 0, sizeof(reg_values));
|
|
|
|
|
2018-03-26 19:06:58 +02:00
|
|
|
rip = vcpu->exit_ctx.VpContext.Rip +
|
|
|
|
vcpu->exit_ctx.VpContext.InstructionLength;
|
2020-02-27 22:01:04 +01:00
|
|
|
cpuid_fn = vcpu->exit_ctx.CpuidAccess.Rax;
|
|
|
|
|
|
|
|
/*
|
|
|
|
* Ideally, these should be supplied to the hypervisor during VCPU
|
|
|
|
* initialization and it should be able to satisfy this request.
|
|
|
|
* But, currently, WHPX doesn't support setting CPUID values in the
|
|
|
|
* hypervisor once the partition has been setup, which is too late
|
|
|
|
* since VCPUs are realized later. For now, use the values from
|
|
|
|
* QEMU to satisfy these requests, until WHPX adds support for
|
|
|
|
* being able to set these values in the hypervisor at runtime.
|
|
|
|
*/
|
|
|
|
cpu_x86_cpuid(env, cpuid_fn, 0, (UINT32 *)&rax, (UINT32 *)&rbx,
|
|
|
|
(UINT32 *)&rcx, (UINT32 *)&rdx);
|
|
|
|
switch (cpuid_fn) {
|
2020-07-31 00:11:26 +02:00
|
|
|
case 0x40000000:
|
|
|
|
/* Expose the vmware cpu frequency cpuid leaf */
|
|
|
|
rax = 0x40000010;
|
|
|
|
rbx = rcx = rdx = 0;
|
|
|
|
break;
|
|
|
|
|
|
|
|
case 0x40000010:
|
|
|
|
rax = env->tsc_khz;
|
|
|
|
rbx = env->apic_bus_freq / 1000; /* Hz to KHz */
|
|
|
|
rcx = rdx = 0;
|
|
|
|
break;
|
|
|
|
|
2018-06-06 00:15:27 +02:00
|
|
|
case 0x80000001:
|
|
|
|
/* Remove any support of OSVW */
|
2020-02-27 22:01:04 +01:00
|
|
|
rcx &= ~CPUID_EXT3_OSVW;
|
2018-03-26 19:06:58 +02:00
|
|
|
break;
|
|
|
|
}
|
|
|
|
|
|
|
|
reg_names[0] = WHvX64RegisterRip;
|
|
|
|
reg_names[1] = WHvX64RegisterRax;
|
|
|
|
reg_names[2] = WHvX64RegisterRcx;
|
|
|
|
reg_names[3] = WHvX64RegisterRdx;
|
|
|
|
reg_names[4] = WHvX64RegisterRbx;
|
|
|
|
|
|
|
|
reg_values[0].Reg64 = rip;
|
|
|
|
reg_values[1].Reg64 = rax;
|
|
|
|
reg_values[2].Reg64 = rcx;
|
|
|
|
reg_values[3].Reg64 = rdx;
|
|
|
|
reg_values[4].Reg64 = rbx;
|
|
|
|
|
2018-05-15 19:35:21 +02:00
|
|
|
hr = whp_dispatch.WHvSetVirtualProcessorRegisters(
|
|
|
|
whpx->partition, cpu->cpu_index,
|
|
|
|
reg_names,
|
|
|
|
reg_count,
|
|
|
|
reg_values);
|
2018-03-26 19:06:58 +02:00
|
|
|
|
|
|
|
if (FAILED(hr)) {
|
|
|
|
error_report("WHPX: Failed to set CpuidAccess state registers,"
|
|
|
|
" hr=%08lx", hr);
|
|
|
|
}
|
|
|
|
ret = 0;
|
|
|
|
break;
|
|
|
|
}
|
2022-03-03 02:28:33 +01:00
|
|
|
case WHvRunVpExitReasonException:
|
|
|
|
whpx_get_registers(cpu);
|
|
|
|
|
|
|
|
if ((vcpu->exit_ctx.VpException.ExceptionType ==
|
|
|
|
WHvX64ExceptionTypeDebugTrapOrFault) &&
|
|
|
|
(vcpu->exit_ctx.VpException.InstructionByteCount >= 1) &&
|
|
|
|
(vcpu->exit_ctx.VpException.InstructionBytes[0] ==
|
|
|
|
whpx_breakpoint_instruction)) {
|
|
|
|
/* Stopped at a software breakpoint. */
|
|
|
|
cpu->exception_index = EXCP_DEBUG;
|
|
|
|
} else if ((vcpu->exit_ctx.VpException.ExceptionType ==
|
|
|
|
WHvX64ExceptionTypeDebugTrapOrFault) &&
|
|
|
|
!cpu->singlestep_enabled) {
|
|
|
|
/*
|
|
|
|
* Just finished stepping over a breakpoint, but the
|
|
|
|
* gdb does not expect us to do single-stepping.
|
|
|
|
* Don't do anything special.
|
|
|
|
*/
|
|
|
|
cpu->exception_index = EXCP_INTERRUPT;
|
|
|
|
} else {
|
|
|
|
/* Another exception or debug event. Report it to GDB. */
|
|
|
|
cpu->exception_index = EXCP_DEBUG;
|
|
|
|
}
|
|
|
|
|
|
|
|
ret = 1;
|
|
|
|
break;
|
2018-01-22 22:07:48 +01:00
|
|
|
case WHvRunVpExitReasonNone:
|
|
|
|
case WHvRunVpExitReasonUnrecoverableException:
|
|
|
|
case WHvRunVpExitReasonInvalidVpRegisterValue:
|
|
|
|
case WHvRunVpExitReasonUnsupportedFeature:
|
|
|
|
default:
|
|
|
|
error_report("WHPX: Unexpected VP exit code %d",
|
|
|
|
vcpu->exit_ctx.ExitReason);
|
|
|
|
whpx_get_registers(cpu);
|
|
|
|
qemu_mutex_lock_iothread();
|
|
|
|
qemu_system_guest_panicked(cpu_get_crash_info(cpu));
|
|
|
|
qemu_mutex_unlock_iothread();
|
|
|
|
break;
|
|
|
|
}
|
|
|
|
|
|
|
|
} while (!ret);
|
|
|
|
|
2022-03-03 02:28:33 +01:00
|
|
|
if (stepped_over_bp) {
|
|
|
|
/* Restore the breakpoint we stepped over */
|
|
|
|
cpu_memory_rw_debug(cpu,
|
|
|
|
stepped_over_bp->address,
|
|
|
|
(void *)&whpx_breakpoint_instruction,
|
|
|
|
1,
|
|
|
|
true);
|
|
|
|
}
|
|
|
|
|
|
|
|
if (exclusive_step_mode != WHPX_STEP_NONE) {
|
|
|
|
g_assert(cpu_in_exclusive_context(cpu));
|
|
|
|
cpu->running = false;
|
|
|
|
end_exclusive();
|
|
|
|
|
|
|
|
exclusive_step_mode = WHPX_STEP_NONE;
|
|
|
|
} else {
|
|
|
|
cpu_exec_end(cpu);
|
|
|
|
}
|
|
|
|
|
2018-01-22 22:07:48 +01:00
|
|
|
qemu_mutex_lock_iothread();
|
|
|
|
current_cpu = cpu;
|
|
|
|
|
2022-03-03 02:28:33 +01:00
|
|
|
if (--whpx->running_cpus == 0) {
|
|
|
|
whpx_last_vcpu_stopping(cpu);
|
|
|
|
}
|
|
|
|
|
2020-09-23 12:56:46 +02:00
|
|
|
qatomic_set(&cpu->exit_request, false);
|
2018-01-22 22:07:48 +01:00
|
|
|
|
|
|
|
return ret < 0;
|
|
|
|
}
|
|
|
|
|
|
|
|
static void do_whpx_cpu_synchronize_state(CPUState *cpu, run_on_cpu_data arg)
|
|
|
|
{
|
2020-02-24 20:27:38 +01:00
|
|
|
if (!cpu->vcpu_dirty) {
|
|
|
|
whpx_get_registers(cpu);
|
|
|
|
cpu->vcpu_dirty = true;
|
|
|
|
}
|
2018-01-22 22:07:48 +01:00
|
|
|
}
|
|
|
|
|
|
|
|
static void do_whpx_cpu_synchronize_post_reset(CPUState *cpu,
|
|
|
|
run_on_cpu_data arg)
|
|
|
|
{
|
2020-02-26 21:54:39 +01:00
|
|
|
whpx_set_registers(cpu, WHPX_SET_RESET_STATE);
|
2018-01-22 22:07:48 +01:00
|
|
|
cpu->vcpu_dirty = false;
|
|
|
|
}
|
|
|
|
|
|
|
|
static void do_whpx_cpu_synchronize_post_init(CPUState *cpu,
|
|
|
|
run_on_cpu_data arg)
|
|
|
|
{
|
2020-02-26 21:54:39 +01:00
|
|
|
whpx_set_registers(cpu, WHPX_SET_FULL_STATE);
|
2018-01-22 22:07:48 +01:00
|
|
|
cpu->vcpu_dirty = false;
|
|
|
|
}
|
|
|
|
|
|
|
|
static void do_whpx_cpu_synchronize_pre_loadvm(CPUState *cpu,
|
|
|
|
run_on_cpu_data arg)
|
|
|
|
{
|
|
|
|
cpu->vcpu_dirty = true;
|
|
|
|
}
|
|
|
|
|
|
|
|
/*
|
|
|
|
* CPU support.
|
|
|
|
*/
|
|
|
|
|
|
|
|
void whpx_cpu_synchronize_state(CPUState *cpu)
|
|
|
|
{
|
|
|
|
if (!cpu->vcpu_dirty) {
|
|
|
|
run_on_cpu(cpu, do_whpx_cpu_synchronize_state, RUN_ON_CPU_NULL);
|
|
|
|
}
|
|
|
|
}
|
|
|
|
|
|
|
|
void whpx_cpu_synchronize_post_reset(CPUState *cpu)
|
|
|
|
{
|
|
|
|
run_on_cpu(cpu, do_whpx_cpu_synchronize_post_reset, RUN_ON_CPU_NULL);
|
|
|
|
}
|
|
|
|
|
|
|
|
void whpx_cpu_synchronize_post_init(CPUState *cpu)
|
|
|
|
{
|
|
|
|
run_on_cpu(cpu, do_whpx_cpu_synchronize_post_init, RUN_ON_CPU_NULL);
|
|
|
|
}
|
|
|
|
|
|
|
|
void whpx_cpu_synchronize_pre_loadvm(CPUState *cpu)
|
|
|
|
{
|
|
|
|
run_on_cpu(cpu, do_whpx_cpu_synchronize_pre_loadvm, RUN_ON_CPU_NULL);
|
|
|
|
}
|
|
|
|
|
2022-03-03 02:28:33 +01:00
|
|
|
void whpx_cpu_synchronize_pre_resume(bool step_pending)
|
|
|
|
{
|
|
|
|
whpx_global.step_pending = step_pending;
|
|
|
|
}
|
|
|
|
|
2018-01-22 22:07:48 +01:00
|
|
|
/*
|
|
|
|
* Vcpu support.
|
|
|
|
*/
|
|
|
|
|
|
|
|
static Error *whpx_migration_blocker;
|
|
|
|
|
2021-01-11 16:20:20 +01:00
|
|
|
static void whpx_cpu_update_state(void *opaque, bool running, RunState state)
|
2020-02-26 21:54:39 +01:00
|
|
|
{
|
|
|
|
CPUX86State *env = opaque;
|
|
|
|
|
|
|
|
if (running) {
|
|
|
|
env->tsc_valid = false;
|
|
|
|
}
|
|
|
|
}
|
|
|
|
|
2018-01-22 22:07:48 +01:00
|
|
|
int whpx_init_vcpu(CPUState *cpu)
|
|
|
|
{
|
|
|
|
HRESULT hr;
|
|
|
|
struct whpx_state *whpx = &whpx_global;
|
2020-07-31 00:11:26 +02:00
|
|
|
struct whpx_vcpu *vcpu = NULL;
|
2018-01-22 22:07:48 +01:00
|
|
|
Error *local_error = NULL;
|
2022-03-05 23:35:19 +01:00
|
|
|
CPUX86State *env = cpu->env_ptr;
|
2020-07-31 00:11:26 +02:00
|
|
|
X86CPU *x86_cpu = X86_CPU(cpu);
|
|
|
|
UINT64 freq = 0;
|
|
|
|
int ret;
|
2018-01-22 22:07:48 +01:00
|
|
|
|
|
|
|
/* Add migration blockers for all unsupported features of the
|
|
|
|
* Windows Hypervisor Platform
|
|
|
|
*/
|
|
|
|
if (whpx_migration_blocker == NULL) {
|
|
|
|
error_setg(&whpx_migration_blocker,
|
|
|
|
"State blocked due to non-migratable CPUID feature support,"
|
|
|
|
"dirty memory tracking support, and XSAVE/XRSTOR support");
|
|
|
|
|
2021-07-20 14:54:01 +02:00
|
|
|
if (migrate_add_blocker(whpx_migration_blocker, &local_error) < 0) {
|
2018-01-22 22:07:48 +01:00
|
|
|
error_report_err(local_error);
|
2018-05-15 19:35:21 +02:00
|
|
|
error_free(whpx_migration_blocker);
|
2020-07-31 00:11:26 +02:00
|
|
|
ret = -EINVAL;
|
|
|
|
goto error;
|
2018-01-22 22:07:48 +01:00
|
|
|
}
|
|
|
|
}
|
|
|
|
|
2022-03-15 15:41:56 +01:00
|
|
|
vcpu = g_new0(struct whpx_vcpu, 1);
|
2018-01-22 22:07:48 +01:00
|
|
|
|
|
|
|
if (!vcpu) {
|
|
|
|
error_report("WHPX: Failed to allocte VCPU context.");
|
2020-07-31 00:11:26 +02:00
|
|
|
ret = -ENOMEM;
|
|
|
|
goto error;
|
2018-01-22 22:07:48 +01:00
|
|
|
}
|
|
|
|
|
2018-05-15 19:35:21 +02:00
|
|
|
hr = whp_dispatch.WHvEmulatorCreateEmulator(
|
|
|
|
&whpx_emu_callbacks,
|
|
|
|
&vcpu->emulator);
|
2018-01-22 22:07:48 +01:00
|
|
|
if (FAILED(hr)) {
|
|
|
|
error_report("WHPX: Failed to setup instruction completion support,"
|
|
|
|
" hr=%08lx", hr);
|
2020-07-31 00:11:26 +02:00
|
|
|
ret = -EINVAL;
|
|
|
|
goto error;
|
2018-01-22 22:07:48 +01:00
|
|
|
}
|
|
|
|
|
2018-05-15 19:35:21 +02:00
|
|
|
hr = whp_dispatch.WHvCreateVirtualProcessor(
|
|
|
|
whpx->partition, cpu->cpu_index, 0);
|
2018-01-22 22:07:48 +01:00
|
|
|
if (FAILED(hr)) {
|
|
|
|
error_report("WHPX: Failed to create a virtual processor,"
|
|
|
|
" hr=%08lx", hr);
|
2018-05-15 19:35:21 +02:00
|
|
|
whp_dispatch.WHvEmulatorDestroyEmulator(vcpu->emulator);
|
2020-07-31 00:11:26 +02:00
|
|
|
ret = -EINVAL;
|
|
|
|
goto error;
|
2018-01-22 22:07:48 +01:00
|
|
|
}
|
|
|
|
|
2020-07-31 00:11:26 +02:00
|
|
|
/*
|
|
|
|
* vcpu's TSC frequency is either specified by user, or use the value
|
|
|
|
* provided by Hyper-V if the former is not present. In the latter case, we
|
|
|
|
* query it from Hyper-V and record in env->tsc_khz, so that vcpu's TSC
|
|
|
|
* frequency can be migrated later via this field.
|
|
|
|
*/
|
|
|
|
if (!env->tsc_khz) {
|
|
|
|
hr = whp_dispatch.WHvGetCapability(
|
|
|
|
WHvCapabilityCodeProcessorClockFrequency, &freq, sizeof(freq),
|
|
|
|
NULL);
|
|
|
|
if (hr != WHV_E_UNKNOWN_CAPABILITY) {
|
|
|
|
if (FAILED(hr)) {
|
|
|
|
printf("WHPX: Failed to query tsc frequency, hr=0x%08lx\n", hr);
|
|
|
|
} else {
|
|
|
|
env->tsc_khz = freq / 1000; /* Hz to KHz */
|
|
|
|
}
|
|
|
|
}
|
|
|
|
}
|
2018-01-22 22:07:48 +01:00
|
|
|
|
2020-07-31 00:11:26 +02:00
|
|
|
env->apic_bus_freq = HYPERV_APIC_BUS_FREQUENCY;
|
|
|
|
hr = whp_dispatch.WHvGetCapability(
|
|
|
|
WHvCapabilityCodeInterruptClockFrequency, &freq, sizeof(freq), NULL);
|
|
|
|
if (hr != WHV_E_UNKNOWN_CAPABILITY) {
|
|
|
|
if (FAILED(hr)) {
|
|
|
|
printf("WHPX: Failed to query apic bus frequency hr=0x%08lx\n", hr);
|
|
|
|
} else {
|
|
|
|
env->apic_bus_freq = freq;
|
|
|
|
}
|
|
|
|
}
|
|
|
|
|
|
|
|
/*
|
|
|
|
* If the vmware cpuid frequency leaf option is set, and we have a valid
|
|
|
|
* tsc value, trap the corresponding cpuid's.
|
|
|
|
*/
|
|
|
|
if (x86_cpu->vmware_cpuid_freq && env->tsc_khz) {
|
|
|
|
UINT32 cpuidExitList[] = {1, 0x80000001, 0x40000000, 0x40000010};
|
|
|
|
|
|
|
|
hr = whp_dispatch.WHvSetPartitionProperty(
|
|
|
|
whpx->partition,
|
|
|
|
WHvPartitionPropertyCodeCpuidExitList,
|
|
|
|
cpuidExitList,
|
|
|
|
RTL_NUMBER_OF(cpuidExitList) * sizeof(UINT32));
|
|
|
|
|
|
|
|
if (FAILED(hr)) {
|
|
|
|
error_report("WHPX: Failed to set partition CpuidExitList hr=%08lx",
|
|
|
|
hr);
|
|
|
|
ret = -EINVAL;
|
|
|
|
goto error;
|
|
|
|
}
|
|
|
|
}
|
|
|
|
|
|
|
|
vcpu->interruptable = true;
|
2018-01-22 22:07:48 +01:00
|
|
|
cpu->vcpu_dirty = true;
|
|
|
|
cpu->hax_vcpu = (struct hax_vcpu_state *)vcpu;
|
2020-10-28 03:23:19 +01:00
|
|
|
max_vcpu_index = max(max_vcpu_index, cpu->cpu_index);
|
2020-02-26 21:54:39 +01:00
|
|
|
qemu_add_vm_change_state_handler(whpx_cpu_update_state, cpu->env_ptr);
|
2018-01-22 22:07:48 +01:00
|
|
|
|
|
|
|
return 0;
|
2020-07-31 00:11:26 +02:00
|
|
|
|
|
|
|
error:
|
|
|
|
g_free(vcpu);
|
|
|
|
|
|
|
|
return ret;
|
2018-01-22 22:07:48 +01:00
|
|
|
}
|
|
|
|
|
|
|
|
int whpx_vcpu_exec(CPUState *cpu)
|
|
|
|
{
|
|
|
|
int ret;
|
|
|
|
int fatal;
|
|
|
|
|
|
|
|
for (;;) {
|
|
|
|
if (cpu->exception_index >= EXCP_INTERRUPT) {
|
|
|
|
ret = cpu->exception_index;
|
|
|
|
cpu->exception_index = -1;
|
|
|
|
break;
|
|
|
|
}
|
|
|
|
|
|
|
|
fatal = whpx_vcpu_run(cpu);
|
|
|
|
|
|
|
|
if (fatal) {
|
|
|
|
error_report("WHPX: Failed to exec a virtual processor");
|
|
|
|
abort();
|
|
|
|
}
|
|
|
|
}
|
|
|
|
|
|
|
|
return ret;
|
|
|
|
}
|
|
|
|
|
|
|
|
void whpx_destroy_vcpu(CPUState *cpu)
|
|
|
|
{
|
|
|
|
struct whpx_state *whpx = &whpx_global;
|
|
|
|
struct whpx_vcpu *vcpu = get_whpx_vcpu(cpu);
|
|
|
|
|
2018-05-15 19:35:21 +02:00
|
|
|
whp_dispatch.WHvDeleteVirtualProcessor(whpx->partition, cpu->cpu_index);
|
|
|
|
whp_dispatch.WHvEmulatorDestroyEmulator(vcpu->emulator);
|
2018-01-22 22:07:48 +01:00
|
|
|
g_free(cpu->hax_vcpu);
|
|
|
|
return;
|
|
|
|
}
|
|
|
|
|
|
|
|
void whpx_vcpu_kick(CPUState *cpu)
|
|
|
|
{
|
|
|
|
struct whpx_state *whpx = &whpx_global;
|
2018-05-15 19:35:21 +02:00
|
|
|
whp_dispatch.WHvCancelRunVirtualProcessor(
|
|
|
|
whpx->partition, cpu->cpu_index, 0);
|
2018-01-22 22:07:48 +01:00
|
|
|
}
|
|
|
|
|
|
|
|
/*
|
|
|
|
* Memory support.
|
|
|
|
*/
|
|
|
|
|
|
|
|
static void whpx_update_mapping(hwaddr start_pa, ram_addr_t size,
|
|
|
|
void *host_va, int add, int rom,
|
|
|
|
const char *name)
|
|
|
|
{
|
|
|
|
struct whpx_state *whpx = &whpx_global;
|
|
|
|
HRESULT hr;
|
|
|
|
|
|
|
|
/*
|
|
|
|
if (add) {
|
|
|
|
printf("WHPX: ADD PA:%p Size:%p, Host:%p, %s, '%s'\n",
|
|
|
|
(void*)start_pa, (void*)size, host_va,
|
|
|
|
(rom ? "ROM" : "RAM"), name);
|
|
|
|
} else {
|
|
|
|
printf("WHPX: DEL PA:%p Size:%p, Host:%p, '%s'\n",
|
|
|
|
(void*)start_pa, (void*)size, host_va, name);
|
|
|
|
}
|
|
|
|
*/
|
|
|
|
|
|
|
|
if (add) {
|
2018-05-15 19:35:21 +02:00
|
|
|
hr = whp_dispatch.WHvMapGpaRange(whpx->partition,
|
|
|
|
host_va,
|
|
|
|
start_pa,
|
|
|
|
size,
|
|
|
|
(WHvMapGpaRangeFlagRead |
|
|
|
|
WHvMapGpaRangeFlagExecute |
|
|
|
|
(rom ? 0 : WHvMapGpaRangeFlagWrite)));
|
2018-01-22 22:07:48 +01:00
|
|
|
} else {
|
2018-05-15 19:35:21 +02:00
|
|
|
hr = whp_dispatch.WHvUnmapGpaRange(whpx->partition,
|
|
|
|
start_pa,
|
|
|
|
size);
|
2018-01-22 22:07:48 +01:00
|
|
|
}
|
|
|
|
|
|
|
|
if (FAILED(hr)) {
|
|
|
|
error_report("WHPX: Failed to %s GPA range '%s' PA:%p, Size:%p bytes,"
|
|
|
|
" Host:%p, hr=%08lx",
|
|
|
|
(add ? "MAP" : "UNMAP"), name,
|
2018-05-15 19:35:22 +02:00
|
|
|
(void *)(uintptr_t)start_pa, (void *)size, host_va, hr);
|
2018-01-22 22:07:48 +01:00
|
|
|
}
|
|
|
|
}
|
|
|
|
|
|
|
|
static void whpx_process_section(MemoryRegionSection *section, int add)
|
|
|
|
{
|
|
|
|
MemoryRegion *mr = section->mr;
|
|
|
|
hwaddr start_pa = section->offset_within_address_space;
|
|
|
|
ram_addr_t size = int128_get64(section->size);
|
|
|
|
unsigned int delta;
|
|
|
|
uint64_t host_va;
|
|
|
|
|
|
|
|
if (!memory_region_is_ram(mr)) {
|
|
|
|
return;
|
|
|
|
}
|
|
|
|
|
2022-03-23 16:57:22 +01:00
|
|
|
delta = qemu_real_host_page_size() - (start_pa & ~qemu_real_host_page_mask());
|
|
|
|
delta &= ~qemu_real_host_page_mask();
|
2018-01-22 22:07:48 +01:00
|
|
|
if (delta > size) {
|
|
|
|
return;
|
|
|
|
}
|
|
|
|
start_pa += delta;
|
|
|
|
size -= delta;
|
2022-03-23 16:57:22 +01:00
|
|
|
size &= qemu_real_host_page_mask();
|
|
|
|
if (!size || (start_pa & ~qemu_real_host_page_mask())) {
|
2018-01-22 22:07:48 +01:00
|
|
|
return;
|
|
|
|
}
|
|
|
|
|
|
|
|
host_va = (uintptr_t)memory_region_get_ram_ptr(mr)
|
|
|
|
+ section->offset_within_region + delta;
|
|
|
|
|
2018-05-15 19:35:22 +02:00
|
|
|
whpx_update_mapping(start_pa, size, (void *)(uintptr_t)host_va, add,
|
|
|
|
memory_region_is_rom(mr), mr->name);
|
2018-01-22 22:07:48 +01:00
|
|
|
}
|
|
|
|
|
|
|
|
static void whpx_region_add(MemoryListener *listener,
|
|
|
|
MemoryRegionSection *section)
|
|
|
|
{
|
|
|
|
memory_region_ref(section->mr);
|
|
|
|
whpx_process_section(section, 1);
|
|
|
|
}
|
|
|
|
|
|
|
|
static void whpx_region_del(MemoryListener *listener,
|
|
|
|
MemoryRegionSection *section)
|
|
|
|
{
|
|
|
|
whpx_process_section(section, 0);
|
|
|
|
memory_region_unref(section->mr);
|
|
|
|
}
|
|
|
|
|
|
|
|
static void whpx_transaction_begin(MemoryListener *listener)
|
|
|
|
{
|
|
|
|
}
|
|
|
|
|
|
|
|
static void whpx_transaction_commit(MemoryListener *listener)
|
|
|
|
{
|
|
|
|
}
|
|
|
|
|
|
|
|
static void whpx_log_sync(MemoryListener *listener,
|
|
|
|
MemoryRegionSection *section)
|
|
|
|
{
|
|
|
|
MemoryRegion *mr = section->mr;
|
|
|
|
|
|
|
|
if (!memory_region_is_ram(mr)) {
|
|
|
|
return;
|
|
|
|
}
|
|
|
|
|
|
|
|
memory_region_set_dirty(mr, 0, int128_get64(section->size));
|
|
|
|
}
|
|
|
|
|
|
|
|
static MemoryListener whpx_memory_listener = {
|
2021-08-17 03:35:52 +02:00
|
|
|
.name = "whpx",
|
2018-01-22 22:07:48 +01:00
|
|
|
.begin = whpx_transaction_begin,
|
|
|
|
.commit = whpx_transaction_commit,
|
|
|
|
.region_add = whpx_region_add,
|
|
|
|
.region_del = whpx_region_del,
|
|
|
|
.log_sync = whpx_log_sync,
|
|
|
|
.priority = 10,
|
|
|
|
};
|
|
|
|
|
|
|
|
static void whpx_memory_init(void)
|
|
|
|
{
|
|
|
|
memory_listener_register(&whpx_memory_listener, &address_space_memory);
|
|
|
|
}
|
|
|
|
|
2019-11-13 19:54:39 +01:00
|
|
|
/*
|
|
|
|
* Load the functions from the given library, using the given handle. If a
|
|
|
|
* handle is provided, it is used, otherwise the library is opened. The
|
|
|
|
* handle will be updated on return with the opened one.
|
|
|
|
*/
|
|
|
|
static bool load_whp_dispatch_fns(HMODULE *handle,
|
|
|
|
WHPFunctionList function_list)
|
|
|
|
{
|
|
|
|
HMODULE hLib = *handle;
|
|
|
|
|
|
|
|
#define WINHV_PLATFORM_DLL "WinHvPlatform.dll"
|
|
|
|
#define WINHV_EMULATION_DLL "WinHvEmulation.dll"
|
2020-02-26 21:54:39 +01:00
|
|
|
#define WHP_LOAD_FIELD_OPTIONAL(return_type, function_name, signature) \
|
|
|
|
whp_dispatch.function_name = \
|
|
|
|
(function_name ## _t)GetProcAddress(hLib, #function_name); \
|
|
|
|
|
2019-11-13 19:54:39 +01:00
|
|
|
#define WHP_LOAD_FIELD(return_type, function_name, signature) \
|
|
|
|
whp_dispatch.function_name = \
|
|
|
|
(function_name ## _t)GetProcAddress(hLib, #function_name); \
|
|
|
|
if (!whp_dispatch.function_name) { \
|
|
|
|
error_report("Could not load function %s", #function_name); \
|
|
|
|
goto error; \
|
|
|
|
} \
|
|
|
|
|
|
|
|
#define WHP_LOAD_LIB(lib_name, handle_lib) \
|
|
|
|
if (!handle_lib) { \
|
|
|
|
handle_lib = LoadLibrary(lib_name); \
|
|
|
|
if (!handle_lib) { \
|
|
|
|
error_report("Could not load library %s.", lib_name); \
|
|
|
|
goto error; \
|
|
|
|
} \
|
|
|
|
} \
|
|
|
|
|
|
|
|
switch (function_list) {
|
|
|
|
case WINHV_PLATFORM_FNS_DEFAULT:
|
|
|
|
WHP_LOAD_LIB(WINHV_PLATFORM_DLL, hLib)
|
|
|
|
LIST_WINHVPLATFORM_FUNCTIONS(WHP_LOAD_FIELD)
|
|
|
|
break;
|
|
|
|
|
|
|
|
case WINHV_EMULATION_FNS_DEFAULT:
|
|
|
|
WHP_LOAD_LIB(WINHV_EMULATION_DLL, hLib)
|
|
|
|
LIST_WINHVEMULATION_FUNCTIONS(WHP_LOAD_FIELD)
|
|
|
|
break;
|
2020-02-26 21:54:39 +01:00
|
|
|
|
|
|
|
case WINHV_PLATFORM_FNS_SUPPLEMENTAL:
|
|
|
|
WHP_LOAD_LIB(WINHV_PLATFORM_DLL, hLib)
|
|
|
|
LIST_WINHVPLATFORM_FUNCTIONS_SUPPLEMENTAL(WHP_LOAD_FIELD_OPTIONAL)
|
|
|
|
break;
|
2019-11-13 19:54:39 +01:00
|
|
|
}
|
|
|
|
|
|
|
|
*handle = hLib;
|
|
|
|
return true;
|
|
|
|
|
|
|
|
error:
|
|
|
|
if (hLib) {
|
|
|
|
FreeLibrary(hLib);
|
|
|
|
}
|
|
|
|
|
|
|
|
return false;
|
|
|
|
}
|
|
|
|
|
2020-10-28 03:23:19 +01:00
|
|
|
static void whpx_set_kernel_irqchip(Object *obj, Visitor *v,
|
|
|
|
const char *name, void *opaque,
|
|
|
|
Error **errp)
|
|
|
|
{
|
|
|
|
struct whpx_state *whpx = &whpx_global;
|
|
|
|
OnOffSplit mode;
|
|
|
|
|
|
|
|
if (!visit_type_OnOffSplit(v, name, &mode, errp)) {
|
|
|
|
return;
|
|
|
|
}
|
|
|
|
|
|
|
|
switch (mode) {
|
|
|
|
case ON_OFF_SPLIT_ON:
|
|
|
|
whpx->kernel_irqchip_allowed = true;
|
|
|
|
whpx->kernel_irqchip_required = true;
|
|
|
|
break;
|
|
|
|
|
|
|
|
case ON_OFF_SPLIT_OFF:
|
|
|
|
whpx->kernel_irqchip_allowed = false;
|
|
|
|
whpx->kernel_irqchip_required = false;
|
|
|
|
break;
|
|
|
|
|
|
|
|
case ON_OFF_SPLIT_SPLIT:
|
|
|
|
error_setg(errp, "WHPX: split irqchip currently not supported");
|
|
|
|
error_append_hint(errp,
|
|
|
|
"Try without kernel-irqchip or with kernel-irqchip=on|off");
|
|
|
|
break;
|
|
|
|
|
|
|
|
default:
|
|
|
|
/*
|
|
|
|
* The value was checked in visit_type_OnOffSplit() above. If
|
|
|
|
* we get here, then something is wrong in QEMU.
|
|
|
|
*/
|
|
|
|
abort();
|
|
|
|
}
|
|
|
|
}
|
|
|
|
|
2018-01-22 22:07:48 +01:00
|
|
|
/*
|
|
|
|
* Partition support
|
|
|
|
*/
|
|
|
|
|
|
|
|
static int whpx_accel_init(MachineState *ms)
|
|
|
|
{
|
|
|
|
struct whpx_state *whpx;
|
|
|
|
int ret;
|
|
|
|
HRESULT hr;
|
|
|
|
WHV_CAPABILITY whpx_cap;
|
2018-03-14 15:52:41 +01:00
|
|
|
UINT32 whpx_cap_size;
|
2018-01-22 22:07:48 +01:00
|
|
|
WHV_PARTITION_PROPERTY prop;
|
2020-07-31 00:11:26 +02:00
|
|
|
UINT32 cpuidExitList[] = {1, 0x80000001};
|
2020-10-28 03:23:19 +01:00
|
|
|
WHV_CAPABILITY_FEATURES features = {0};
|
2018-01-22 22:07:48 +01:00
|
|
|
|
|
|
|
whpx = &whpx_global;
|
|
|
|
|
2018-05-15 19:35:21 +02:00
|
|
|
if (!init_whp_dispatch()) {
|
|
|
|
ret = -ENOSYS;
|
|
|
|
goto error;
|
|
|
|
}
|
|
|
|
|
2018-01-22 22:07:48 +01:00
|
|
|
whpx->mem_quota = ms->ram_size;
|
|
|
|
|
2018-05-15 19:35:21 +02:00
|
|
|
hr = whp_dispatch.WHvGetCapability(
|
|
|
|
WHvCapabilityCodeHypervisorPresent, &whpx_cap,
|
|
|
|
sizeof(whpx_cap), &whpx_cap_size);
|
2018-01-22 22:07:48 +01:00
|
|
|
if (FAILED(hr) || !whpx_cap.HypervisorPresent) {
|
|
|
|
error_report("WHPX: No accelerator found, hr=%08lx", hr);
|
|
|
|
ret = -ENOSPC;
|
|
|
|
goto error;
|
|
|
|
}
|
|
|
|
|
2020-10-28 03:23:19 +01:00
|
|
|
hr = whp_dispatch.WHvGetCapability(
|
|
|
|
WHvCapabilityCodeFeatures, &features, sizeof(features), NULL);
|
|
|
|
if (FAILED(hr)) {
|
|
|
|
error_report("WHPX: Failed to query capabilities, hr=%08lx", hr);
|
|
|
|
ret = -EINVAL;
|
|
|
|
goto error;
|
|
|
|
}
|
|
|
|
|
2018-05-15 19:35:21 +02:00
|
|
|
hr = whp_dispatch.WHvCreatePartition(&whpx->partition);
|
2018-01-22 22:07:48 +01:00
|
|
|
if (FAILED(hr)) {
|
|
|
|
error_report("WHPX: Failed to create partition, hr=%08lx", hr);
|
|
|
|
ret = -EINVAL;
|
|
|
|
goto error;
|
|
|
|
}
|
|
|
|
|
2019-11-07 20:48:32 +01:00
|
|
|
/*
|
|
|
|
* Query the XSAVE capability of the partition. Any error here is not
|
|
|
|
* considered fatal.
|
|
|
|
*/
|
|
|
|
hr = whp_dispatch.WHvGetPartitionProperty(
|
|
|
|
whpx->partition,
|
|
|
|
WHvPartitionPropertyCodeProcessorXsaveFeatures,
|
|
|
|
&whpx_xsave_cap,
|
|
|
|
sizeof(whpx_xsave_cap),
|
|
|
|
&whpx_cap_size);
|
|
|
|
|
|
|
|
/*
|
|
|
|
* Windows version which don't support this property will return with the
|
|
|
|
* specific error code.
|
|
|
|
*/
|
|
|
|
if (FAILED(hr) && hr != WHV_E_UNKNOWN_PROPERTY) {
|
|
|
|
error_report("WHPX: Failed to query XSAVE capability, hr=%08lx", hr);
|
|
|
|
}
|
|
|
|
|
|
|
|
if (!whpx_has_xsave()) {
|
|
|
|
printf("WHPX: Partition is not XSAVE capable\n");
|
|
|
|
}
|
|
|
|
|
2018-01-22 22:07:48 +01:00
|
|
|
memset(&prop, 0, sizeof(WHV_PARTITION_PROPERTY));
|
2019-07-12 15:26:11 +02:00
|
|
|
prop.ProcessorCount = ms->smp.cpus;
|
2018-05-15 19:35:21 +02:00
|
|
|
hr = whp_dispatch.WHvSetPartitionProperty(
|
|
|
|
whpx->partition,
|
|
|
|
WHvPartitionPropertyCodeProcessorCount,
|
|
|
|
&prop,
|
|
|
|
sizeof(WHV_PARTITION_PROPERTY));
|
2018-01-22 22:07:48 +01:00
|
|
|
|
|
|
|
if (FAILED(hr)) {
|
|
|
|
error_report("WHPX: Failed to set partition core count to %d,"
|
2019-07-12 15:26:11 +02:00
|
|
|
" hr=%08lx", ms->smp.cores, hr);
|
2018-01-22 22:07:48 +01:00
|
|
|
ret = -EINVAL;
|
|
|
|
goto error;
|
2018-03-26 19:06:58 +02:00
|
|
|
}
|
|
|
|
|
2020-10-28 03:23:19 +01:00
|
|
|
/*
|
|
|
|
* Error out if WHP doesn't support apic emulation and user is requiring
|
|
|
|
* it.
|
|
|
|
*/
|
|
|
|
if (whpx->kernel_irqchip_required && (!features.LocalApicEmulation ||
|
|
|
|
!whp_dispatch.WHvSetVirtualProcessorInterruptControllerState2)) {
|
|
|
|
error_report("WHPX: kernel irqchip requested, but unavailable. "
|
|
|
|
"Try without kernel-irqchip or with kernel-irqchip=off");
|
|
|
|
ret = -EINVAL;
|
|
|
|
goto error;
|
|
|
|
}
|
|
|
|
|
|
|
|
if (whpx->kernel_irqchip_allowed && features.LocalApicEmulation &&
|
|
|
|
whp_dispatch.WHvSetVirtualProcessorInterruptControllerState2) {
|
|
|
|
WHV_X64_LOCAL_APIC_EMULATION_MODE mode =
|
|
|
|
WHvX64LocalApicEmulationModeXApic;
|
|
|
|
printf("WHPX: setting APIC emulation mode in the hypervisor\n");
|
|
|
|
hr = whp_dispatch.WHvSetPartitionProperty(
|
|
|
|
whpx->partition,
|
|
|
|
WHvPartitionPropertyCodeLocalApicEmulationMode,
|
|
|
|
&mode,
|
|
|
|
sizeof(mode));
|
|
|
|
if (FAILED(hr)) {
|
|
|
|
error_report("WHPX: Failed to enable kernel irqchip hr=%08lx", hr);
|
|
|
|
if (whpx->kernel_irqchip_required) {
|
|
|
|
error_report("WHPX: kernel irqchip requested, but unavailable");
|
|
|
|
ret = -EINVAL;
|
|
|
|
goto error;
|
|
|
|
}
|
|
|
|
} else {
|
|
|
|
whpx->apic_in_platform = true;
|
|
|
|
}
|
|
|
|
}
|
|
|
|
|
|
|
|
/* Register for MSR and CPUID exits */
|
2018-03-26 19:06:58 +02:00
|
|
|
memset(&prop, 0, sizeof(WHV_PARTITION_PROPERTY));
|
2018-06-06 00:15:28 +02:00
|
|
|
prop.ExtendedVmExits.X64MsrExit = 1;
|
2018-03-26 19:06:58 +02:00
|
|
|
prop.ExtendedVmExits.X64CpuidExit = 1;
|
2022-03-03 02:28:33 +01:00
|
|
|
prop.ExtendedVmExits.ExceptionExit = 1;
|
2020-10-28 03:23:19 +01:00
|
|
|
if (whpx_apic_in_platform()) {
|
|
|
|
prop.ExtendedVmExits.X64ApicInitSipiExitTrap = 1;
|
|
|
|
}
|
2018-03-26 19:06:58 +02:00
|
|
|
|
2020-10-28 03:23:19 +01:00
|
|
|
hr = whp_dispatch.WHvSetPartitionProperty(
|
|
|
|
whpx->partition,
|
|
|
|
WHvPartitionPropertyCodeExtendedVmExits,
|
|
|
|
&prop,
|
|
|
|
sizeof(WHV_PARTITION_PROPERTY));
|
2018-03-26 19:06:58 +02:00
|
|
|
if (FAILED(hr)) {
|
2020-10-28 03:23:19 +01:00
|
|
|
error_report("WHPX: Failed to enable MSR & CPUIDexit, hr=%08lx", hr);
|
2018-03-26 19:06:58 +02:00
|
|
|
ret = -EINVAL;
|
|
|
|
goto error;
|
|
|
|
}
|
|
|
|
|
2018-05-15 19:35:21 +02:00
|
|
|
hr = whp_dispatch.WHvSetPartitionProperty(
|
|
|
|
whpx->partition,
|
|
|
|
WHvPartitionPropertyCodeCpuidExitList,
|
|
|
|
cpuidExitList,
|
|
|
|
RTL_NUMBER_OF(cpuidExitList) * sizeof(UINT32));
|
2018-06-06 00:15:27 +02:00
|
|
|
|
2018-03-26 19:06:58 +02:00
|
|
|
if (FAILED(hr)) {
|
|
|
|
error_report("WHPX: Failed to set partition CpuidExitList hr=%08lx",
|
|
|
|
hr);
|
|
|
|
ret = -EINVAL;
|
|
|
|
goto error;
|
2018-01-22 22:07:48 +01:00
|
|
|
}
|
|
|
|
|
2022-03-03 02:28:33 +01:00
|
|
|
/*
|
|
|
|
* We do not want to intercept any exceptions from the guest,
|
|
|
|
* until we actually start debugging with gdb.
|
|
|
|
*/
|
|
|
|
whpx->exception_exit_bitmap = -1;
|
|
|
|
hr = whpx_set_exception_exit_bitmap(0);
|
|
|
|
|
|
|
|
if (FAILED(hr)) {
|
|
|
|
error_report("WHPX: Failed to set exception exit bitmap, hr=%08lx", hr);
|
|
|
|
ret = -EINVAL;
|
|
|
|
goto error;
|
|
|
|
}
|
|
|
|
|
2018-05-15 19:35:21 +02:00
|
|
|
hr = whp_dispatch.WHvSetupPartition(whpx->partition);
|
2018-01-22 22:07:48 +01:00
|
|
|
if (FAILED(hr)) {
|
|
|
|
error_report("WHPX: Failed to setup partition, hr=%08lx", hr);
|
|
|
|
ret = -EINVAL;
|
|
|
|
goto error;
|
|
|
|
}
|
|
|
|
|
|
|
|
whpx_memory_init();
|
|
|
|
|
|
|
|
printf("Windows Hypervisor Platform accelerator is operational\n");
|
|
|
|
return 0;
|
|
|
|
|
2020-07-31 00:11:26 +02:00
|
|
|
error:
|
2018-01-22 22:07:48 +01:00
|
|
|
|
|
|
|
if (NULL != whpx->partition) {
|
2018-05-15 19:35:21 +02:00
|
|
|
whp_dispatch.WHvDeletePartition(whpx->partition);
|
2018-01-22 22:07:48 +01:00
|
|
|
whpx->partition = NULL;
|
|
|
|
}
|
|
|
|
|
|
|
|
return ret;
|
|
|
|
}
|
|
|
|
|
|
|
|
int whpx_enabled(void)
|
|
|
|
{
|
|
|
|
return whpx_allowed;
|
|
|
|
}
|
|
|
|
|
2020-12-19 10:06:37 +01:00
|
|
|
bool whpx_apic_in_platform(void) {
|
|
|
|
return whpx_global.apic_in_platform;
|
|
|
|
}
|
|
|
|
|
2018-01-22 22:07:48 +01:00
|
|
|
static void whpx_accel_class_init(ObjectClass *oc, void *data)
|
|
|
|
{
|
|
|
|
AccelClass *ac = ACCEL_CLASS(oc);
|
|
|
|
ac->name = "WHPX";
|
|
|
|
ac->init_machine = whpx_accel_init;
|
|
|
|
ac->allowed = &whpx_allowed;
|
2020-10-28 03:23:19 +01:00
|
|
|
|
|
|
|
object_class_property_add(oc, "kernel-irqchip", "on|off|split",
|
|
|
|
NULL, whpx_set_kernel_irqchip,
|
|
|
|
NULL, NULL);
|
|
|
|
object_class_property_set_description(oc, "kernel-irqchip",
|
|
|
|
"Configure WHPX in-kernel irqchip");
|
|
|
|
}
|
|
|
|
|
|
|
|
static void whpx_accel_instance_init(Object *obj)
|
|
|
|
{
|
|
|
|
struct whpx_state *whpx = &whpx_global;
|
|
|
|
|
|
|
|
memset(whpx, 0, sizeof(struct whpx_state));
|
|
|
|
/* Turn on kernel-irqchip, by default */
|
|
|
|
whpx->kernel_irqchip_allowed = true;
|
2018-01-22 22:07:48 +01:00
|
|
|
}
|
|
|
|
|
|
|
|
static const TypeInfo whpx_accel_type = {
|
|
|
|
.name = ACCEL_CLASS_NAME("whpx"),
|
|
|
|
.parent = TYPE_ACCEL,
|
2020-10-28 03:23:19 +01:00
|
|
|
.instance_init = whpx_accel_instance_init,
|
2018-01-22 22:07:48 +01:00
|
|
|
.class_init = whpx_accel_class_init,
|
|
|
|
};
|
|
|
|
|
|
|
|
static void whpx_type_init(void)
|
|
|
|
{
|
|
|
|
type_register_static(&whpx_accel_type);
|
|
|
|
}
|
|
|
|
|
2018-05-15 19:35:21 +02:00
|
|
|
bool init_whp_dispatch(void)
|
|
|
|
{
|
|
|
|
if (whp_dispatch_initialized) {
|
|
|
|
return true;
|
|
|
|
}
|
|
|
|
|
2019-11-13 19:54:39 +01:00
|
|
|
if (!load_whp_dispatch_fns(&hWinHvPlatform, WINHV_PLATFORM_FNS_DEFAULT)) {
|
2018-05-15 19:35:21 +02:00
|
|
|
goto error;
|
|
|
|
}
|
|
|
|
|
2019-11-13 19:54:39 +01:00
|
|
|
if (!load_whp_dispatch_fns(&hWinHvEmulation, WINHV_EMULATION_FNS_DEFAULT)) {
|
2018-05-15 19:35:21 +02:00
|
|
|
goto error;
|
|
|
|
}
|
|
|
|
|
2020-02-26 21:54:39 +01:00
|
|
|
assert(load_whp_dispatch_fns(&hWinHvPlatform,
|
|
|
|
WINHV_PLATFORM_FNS_SUPPLEMENTAL));
|
2018-05-15 19:35:21 +02:00
|
|
|
whp_dispatch_initialized = true;
|
|
|
|
|
2019-11-13 19:54:39 +01:00
|
|
|
return true;
|
|
|
|
error:
|
2018-05-15 19:35:21 +02:00
|
|
|
if (hWinHvPlatform) {
|
|
|
|
FreeLibrary(hWinHvPlatform);
|
|
|
|
}
|
2019-11-13 19:54:39 +01:00
|
|
|
|
2018-05-15 19:35:21 +02:00
|
|
|
if (hWinHvEmulation) {
|
|
|
|
FreeLibrary(hWinHvEmulation);
|
|
|
|
}
|
2019-11-13 19:54:39 +01:00
|
|
|
|
2018-05-15 19:35:21 +02:00
|
|
|
return false;
|
|
|
|
}
|
|
|
|
|
2018-01-22 22:07:48 +01:00
|
|
|
type_init(whpx_type_init);
|