2016-10-22 11:46:42 +02:00
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/*
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* QEMU PowerPC PowerNV LPC controller
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*
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* Copyright (c) 2016, IBM Corporation.
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*
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* This library is free software; you can redistribute it and/or
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* modify it under the terms of the GNU Lesser General Public
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* License as published by the Free Software Foundation; either
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2020-10-16 16:53:46 +02:00
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* version 2.1 of the License, or (at your option) any later version.
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2016-10-22 11:46:42 +02:00
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*
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* This library is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
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* Lesser General Public License for more details.
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*
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* You should have received a copy of the GNU Lesser General Public
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* License along with this library; if not, see <http://www.gnu.org/licenses/>.
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*/
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#include "qemu/osdep.h"
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2016-10-11 08:56:52 +02:00
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#include "target/ppc/cpu.h"
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2016-10-22 11:46:42 +02:00
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#include "qapi/error.h"
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#include "qemu/log.h"
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2019-05-23 16:35:07 +02:00
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#include "qemu/module.h"
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2019-08-12 07:23:42 +02:00
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#include "hw/irq.h"
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2018-06-15 17:25:34 +02:00
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#include "hw/isa/isa.h"
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2019-11-15 16:55:43 +01:00
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#include "hw/qdev-properties.h"
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2016-10-22 11:46:42 +02:00
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#include "hw/ppc/pnv.h"
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2016-11-07 19:03:02 +01:00
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#include "hw/ppc/pnv_lpc.h"
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#include "hw/ppc/pnv_xscom.h"
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2016-10-22 11:46:42 +02:00
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#include "hw/ppc/fdt.h"
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#include <libfdt.h>
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enum {
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ECCB_CTL = 0,
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ECCB_RESET = 1,
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ECCB_STAT = 2,
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ECCB_DATA = 3,
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};
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/* OPB Master LS registers */
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2019-03-07 23:35:40 +01:00
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#define OPB_MASTER_LS_ROUTE0 0x8
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#define OPB_MASTER_LS_ROUTE1 0xC
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2016-10-22 11:46:42 +02:00
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#define OPB_MASTER_LS_IRQ_STAT 0x50
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#define OPB_MASTER_IRQ_LPC 0x00000800
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#define OPB_MASTER_LS_IRQ_MASK 0x54
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#define OPB_MASTER_LS_IRQ_POL 0x58
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#define OPB_MASTER_LS_IRQ_INPUT 0x5c
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/* LPC HC registers */
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#define LPC_HC_FW_SEG_IDSEL 0x24
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#define LPC_HC_FW_RD_ACC_SIZE 0x28
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#define LPC_HC_FW_RD_1B 0x00000000
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#define LPC_HC_FW_RD_2B 0x01000000
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#define LPC_HC_FW_RD_4B 0x02000000
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#define LPC_HC_FW_RD_16B 0x04000000
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#define LPC_HC_FW_RD_128B 0x07000000
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#define LPC_HC_IRQSER_CTRL 0x30
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#define LPC_HC_IRQSER_EN 0x80000000
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#define LPC_HC_IRQSER_QMODE 0x40000000
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#define LPC_HC_IRQSER_START_MASK 0x03000000
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#define LPC_HC_IRQSER_START_4CLK 0x00000000
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#define LPC_HC_IRQSER_START_6CLK 0x01000000
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#define LPC_HC_IRQSER_START_8CLK 0x02000000
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#define LPC_HC_IRQMASK 0x34 /* same bit defs as LPC_HC_IRQSTAT */
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#define LPC_HC_IRQSTAT 0x38
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#define LPC_HC_IRQ_SERIRQ0 0x80000000 /* all bits down to ... */
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#define LPC_HC_IRQ_SERIRQ16 0x00008000 /* IRQ16=IOCHK#, IRQ2=SMI# */
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#define LPC_HC_IRQ_SERIRQ_ALL 0xffff8000
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#define LPC_HC_IRQ_LRESET 0x00000400
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#define LPC_HC_IRQ_SYNC_ABNORM_ERR 0x00000080
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#define LPC_HC_IRQ_SYNC_NORESP_ERR 0x00000040
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#define LPC_HC_IRQ_SYNC_NORM_ERR 0x00000020
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#define LPC_HC_IRQ_SYNC_TIMEOUT_ERR 0x00000010
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#define LPC_HC_IRQ_SYNC_TARG_TAR_ERR 0x00000008
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#define LPC_HC_IRQ_SYNC_BM_TAR_ERR 0x00000004
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#define LPC_HC_IRQ_SYNC_BM0_REQ 0x00000002
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#define LPC_HC_IRQ_SYNC_BM1_REQ 0x00000001
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#define LPC_HC_ERROR_ADDRESS 0x40
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#define LPC_OPB_SIZE 0x100000000ull
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#define ISA_IO_SIZE 0x00010000
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#define ISA_MEM_SIZE 0x10000000
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2018-06-11 19:12:10 +02:00
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#define ISA_FW_SIZE 0x10000000
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2016-10-22 11:46:42 +02:00
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#define LPC_IO_OPB_ADDR 0xd0010000
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#define LPC_IO_OPB_SIZE 0x00010000
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2019-11-18 10:19:08 +01:00
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#define LPC_MEM_OPB_ADDR 0xe0000000
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2016-10-22 11:46:42 +02:00
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#define LPC_MEM_OPB_SIZE 0x10000000
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#define LPC_FW_OPB_ADDR 0xf0000000
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#define LPC_FW_OPB_SIZE 0x10000000
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#define LPC_OPB_REGS_OPB_ADDR 0xc0010000
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2019-03-07 23:35:36 +01:00
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#define LPC_OPB_REGS_OPB_SIZE 0x00000060
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#define LPC_OPB_REGS_OPBA_ADDR 0xc0011000
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#define LPC_OPB_REGS_OPBA_SIZE 0x00000008
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2016-10-22 11:46:42 +02:00
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#define LPC_HC_REGS_OPB_ADDR 0xc0012000
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2019-03-07 23:35:36 +01:00
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#define LPC_HC_REGS_OPB_SIZE 0x00000100
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2016-10-22 11:46:42 +02:00
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2017-12-15 14:56:01 +01:00
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static int pnv_lpc_dt_xscom(PnvXScomInterface *dev, void *fdt, int xscom_offset)
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2016-10-22 11:46:42 +02:00
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{
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const char compat[] = "ibm,power8-lpc\0ibm,lpc";
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char *name;
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int offset;
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uint32_t lpc_pcba = PNV_XSCOM_LPC_BASE;
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uint32_t reg[] = {
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cpu_to_be32(lpc_pcba),
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cpu_to_be32(PNV_XSCOM_LPC_SIZE)
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};
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name = g_strdup_printf("isa@%x", lpc_pcba);
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offset = fdt_add_subnode(fdt, xscom_offset, name);
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_FDT(offset);
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g_free(name);
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_FDT((fdt_setprop(fdt, offset, "reg", reg, sizeof(reg))));
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_FDT((fdt_setprop_cell(fdt, offset, "#address-cells", 2)));
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_FDT((fdt_setprop_cell(fdt, offset, "#size-cells", 1)));
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_FDT((fdt_setprop(fdt, offset, "compatible", compat, sizeof(compat))));
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return 0;
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}
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2019-03-07 23:35:39 +01:00
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/* POWER9 only */
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2019-12-05 19:44:54 +01:00
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int pnv_dt_lpc(PnvChip *chip, void *fdt, int root_offset, uint64_t lpcm_addr,
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uint64_t lpcm_size)
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2019-03-07 23:35:39 +01:00
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{
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const char compat[] = "ibm,power9-lpcm-opb\0simple-bus";
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const char lpc_compat[] = "ibm,power9-lpc\0ibm,lpc";
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char *name;
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int offset, lpcm_offset;
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uint32_t opb_ranges[8] = { 0,
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cpu_to_be32(lpcm_addr >> 32),
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cpu_to_be32((uint32_t)lpcm_addr),
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2019-12-05 19:44:54 +01:00
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cpu_to_be32(lpcm_size / 2),
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cpu_to_be32(lpcm_size / 2),
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2019-03-07 23:35:39 +01:00
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cpu_to_be32(lpcm_addr >> 32),
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2019-12-05 19:44:54 +01:00
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cpu_to_be32(lpcm_size / 2),
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cpu_to_be32(lpcm_size / 2),
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2019-03-07 23:35:39 +01:00
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};
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uint32_t opb_reg[4] = { cpu_to_be32(lpcm_addr >> 32),
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cpu_to_be32((uint32_t)lpcm_addr),
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2019-12-05 19:44:54 +01:00
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cpu_to_be32(lpcm_size >> 32),
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cpu_to_be32((uint32_t)lpcm_size),
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2019-03-07 23:35:39 +01:00
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};
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2019-11-18 10:19:08 +01:00
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uint32_t lpc_ranges[12] = { 0, 0,
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cpu_to_be32(LPC_MEM_OPB_ADDR),
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cpu_to_be32(LPC_MEM_OPB_SIZE),
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cpu_to_be32(1), 0,
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cpu_to_be32(LPC_IO_OPB_ADDR),
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cpu_to_be32(LPC_IO_OPB_SIZE),
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cpu_to_be32(3), 0,
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cpu_to_be32(LPC_FW_OPB_ADDR),
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cpu_to_be32(LPC_FW_OPB_SIZE),
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};
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2019-03-07 23:35:39 +01:00
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uint32_t reg[2];
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/*
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* OPB bus
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*/
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name = g_strdup_printf("lpcm-opb@%"PRIx64, lpcm_addr);
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lpcm_offset = fdt_add_subnode(fdt, root_offset, name);
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_FDT(lpcm_offset);
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g_free(name);
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_FDT((fdt_setprop(fdt, lpcm_offset, "reg", opb_reg, sizeof(opb_reg))));
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_FDT((fdt_setprop_cell(fdt, lpcm_offset, "#address-cells", 1)));
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_FDT((fdt_setprop_cell(fdt, lpcm_offset, "#size-cells", 1)));
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_FDT((fdt_setprop(fdt, lpcm_offset, "compatible", compat, sizeof(compat))));
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_FDT((fdt_setprop_cell(fdt, lpcm_offset, "ibm,chip-id", chip->chip_id)));
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_FDT((fdt_setprop(fdt, lpcm_offset, "ranges", opb_ranges,
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sizeof(opb_ranges))));
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/*
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* OPB Master registers
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*/
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name = g_strdup_printf("opb-master@%x", LPC_OPB_REGS_OPB_ADDR);
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offset = fdt_add_subnode(fdt, lpcm_offset, name);
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_FDT(offset);
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g_free(name);
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reg[0] = cpu_to_be32(LPC_OPB_REGS_OPB_ADDR);
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reg[1] = cpu_to_be32(LPC_OPB_REGS_OPB_SIZE);
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_FDT((fdt_setprop(fdt, offset, "reg", reg, sizeof(reg))));
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_FDT((fdt_setprop_string(fdt, offset, "compatible",
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"ibm,power9-lpcm-opb-master")));
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/*
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* OPB arbitrer registers
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*/
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name = g_strdup_printf("opb-arbitrer@%x", LPC_OPB_REGS_OPBA_ADDR);
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offset = fdt_add_subnode(fdt, lpcm_offset, name);
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_FDT(offset);
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g_free(name);
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reg[0] = cpu_to_be32(LPC_OPB_REGS_OPBA_ADDR);
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reg[1] = cpu_to_be32(LPC_OPB_REGS_OPBA_SIZE);
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_FDT((fdt_setprop(fdt, offset, "reg", reg, sizeof(reg))));
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_FDT((fdt_setprop_string(fdt, offset, "compatible",
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"ibm,power9-lpcm-opb-arbiter")));
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/*
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* LPC Host Controller registers
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*/
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name = g_strdup_printf("lpc-controller@%x", LPC_HC_REGS_OPB_ADDR);
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offset = fdt_add_subnode(fdt, lpcm_offset, name);
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_FDT(offset);
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g_free(name);
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reg[0] = cpu_to_be32(LPC_HC_REGS_OPB_ADDR);
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reg[1] = cpu_to_be32(LPC_HC_REGS_OPB_SIZE);
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_FDT((fdt_setprop(fdt, offset, "reg", reg, sizeof(reg))));
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_FDT((fdt_setprop_string(fdt, offset, "compatible",
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"ibm,power9-lpc-controller")));
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name = g_strdup_printf("lpc@0");
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offset = fdt_add_subnode(fdt, lpcm_offset, name);
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_FDT(offset);
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g_free(name);
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_FDT((fdt_setprop_cell(fdt, offset, "#address-cells", 2)));
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_FDT((fdt_setprop_cell(fdt, offset, "#size-cells", 1)));
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_FDT((fdt_setprop(fdt, offset, "compatible", lpc_compat,
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sizeof(lpc_compat))));
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2019-11-18 10:19:08 +01:00
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_FDT((fdt_setprop(fdt, offset, "ranges", lpc_ranges,
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sizeof(lpc_ranges))));
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2019-03-07 23:35:39 +01:00
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return 0;
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}
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2016-10-22 11:46:42 +02:00
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/*
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* These read/write handlers of the OPB address space should be common
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* with the P9 LPC Controller which uses direct MMIOs.
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*
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* TODO: rework to use address_space_stq() and address_space_ldq()
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* instead.
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*/
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static bool opb_read(PnvLpcController *lpc, uint32_t addr, uint8_t *data,
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int sz)
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{
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/* XXX Handle access size limits and FW read caching here */
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2020-02-18 12:24:57 +01:00
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return !address_space_read(&lpc->opb_as, addr, MEMTXATTRS_UNSPECIFIED,
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data, sz);
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2016-10-22 11:46:42 +02:00
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}
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static bool opb_write(PnvLpcController *lpc, uint32_t addr, uint8_t *data,
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int sz)
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{
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/* XXX Handle access size limits here */
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2020-02-18 12:24:57 +01:00
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return !address_space_write(&lpc->opb_as, addr, MEMTXATTRS_UNSPECIFIED,
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data, sz);
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2016-10-22 11:46:42 +02:00
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}
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2017-12-22 10:55:51 +01:00
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#define ECCB_CTL_READ PPC_BIT(15)
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2016-10-22 11:46:42 +02:00
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#define ECCB_CTL_SZ_LSH (63 - 7)
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2017-12-22 10:55:51 +01:00
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#define ECCB_CTL_SZ_MASK PPC_BITMASK(4, 7)
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#define ECCB_CTL_ADDR_MASK PPC_BITMASK(32, 63)
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2016-10-22 11:46:42 +02:00
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2017-12-22 10:55:51 +01:00
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#define ECCB_STAT_OP_DONE PPC_BIT(52)
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#define ECCB_STAT_OP_ERR PPC_BIT(52)
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2016-10-22 11:46:42 +02:00
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#define ECCB_STAT_RD_DATA_LSH (63 - 37)
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#define ECCB_STAT_RD_DATA_MASK (0xffffffff << ECCB_STAT_RD_DATA_LSH)
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static void pnv_lpc_do_eccb(PnvLpcController *lpc, uint64_t cmd)
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{
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/* XXX Check for magic bits at the top, addr size etc... */
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unsigned int sz = (cmd & ECCB_CTL_SZ_MASK) >> ECCB_CTL_SZ_LSH;
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uint32_t opb_addr = cmd & ECCB_CTL_ADDR_MASK;
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2018-10-26 14:33:58 +02:00
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uint8_t data[8];
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2016-10-22 11:46:42 +02:00
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bool success;
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2018-10-26 14:33:58 +02:00
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if (sz > sizeof(data)) {
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qemu_log_mask(LOG_GUEST_ERROR,
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"ECCB: invalid operation at @0x%08x size %d\n", opb_addr, sz);
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return;
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}
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2016-10-22 11:46:42 +02:00
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if (cmd & ECCB_CTL_READ) {
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|
|
success = opb_read(lpc, opb_addr, data, sz);
|
|
|
|
if (success) {
|
|
|
|
lpc->eccb_stat_reg = ECCB_STAT_OP_DONE |
|
|
|
|
(((uint64_t)data[0]) << 24 |
|
|
|
|
((uint64_t)data[1]) << 16 |
|
|
|
|
((uint64_t)data[2]) << 8 |
|
|
|
|
((uint64_t)data[3])) << ECCB_STAT_RD_DATA_LSH;
|
|
|
|
} else {
|
|
|
|
lpc->eccb_stat_reg = ECCB_STAT_OP_DONE |
|
|
|
|
(0xffffffffull << ECCB_STAT_RD_DATA_LSH);
|
|
|
|
}
|
|
|
|
} else {
|
|
|
|
data[0] = lpc->eccb_data_reg >> 24;
|
|
|
|
data[1] = lpc->eccb_data_reg >> 16;
|
|
|
|
data[2] = lpc->eccb_data_reg >> 8;
|
|
|
|
data[3] = lpc->eccb_data_reg;
|
|
|
|
|
|
|
|
success = opb_write(lpc, opb_addr, data, sz);
|
|
|
|
lpc->eccb_stat_reg = ECCB_STAT_OP_DONE;
|
|
|
|
}
|
|
|
|
/* XXX Which error bit (if any) to signal OPB error ? */
|
|
|
|
}
|
|
|
|
|
|
|
|
static uint64_t pnv_lpc_xscom_read(void *opaque, hwaddr addr, unsigned size)
|
|
|
|
{
|
|
|
|
PnvLpcController *lpc = PNV_LPC(opaque);
|
|
|
|
uint32_t offset = addr >> 3;
|
|
|
|
uint64_t val = 0;
|
|
|
|
|
|
|
|
switch (offset & 3) {
|
|
|
|
case ECCB_CTL:
|
|
|
|
case ECCB_RESET:
|
|
|
|
val = 0;
|
|
|
|
break;
|
|
|
|
case ECCB_STAT:
|
|
|
|
val = lpc->eccb_stat_reg;
|
|
|
|
lpc->eccb_stat_reg = 0;
|
|
|
|
break;
|
|
|
|
case ECCB_DATA:
|
|
|
|
val = ((uint64_t)lpc->eccb_data_reg) << 32;
|
|
|
|
break;
|
|
|
|
}
|
|
|
|
return val;
|
|
|
|
}
|
|
|
|
|
|
|
|
static void pnv_lpc_xscom_write(void *opaque, hwaddr addr,
|
|
|
|
uint64_t val, unsigned size)
|
|
|
|
{
|
|
|
|
PnvLpcController *lpc = PNV_LPC(opaque);
|
|
|
|
uint32_t offset = addr >> 3;
|
|
|
|
|
|
|
|
switch (offset & 3) {
|
|
|
|
case ECCB_CTL:
|
|
|
|
pnv_lpc_do_eccb(lpc, val);
|
|
|
|
break;
|
|
|
|
case ECCB_RESET:
|
|
|
|
/* XXXX */
|
|
|
|
break;
|
|
|
|
case ECCB_STAT:
|
|
|
|
break;
|
|
|
|
case ECCB_DATA:
|
|
|
|
lpc->eccb_data_reg = val >> 32;
|
|
|
|
break;
|
|
|
|
}
|
|
|
|
}
|
|
|
|
|
|
|
|
static const MemoryRegionOps pnv_lpc_xscom_ops = {
|
|
|
|
.read = pnv_lpc_xscom_read,
|
|
|
|
.write = pnv_lpc_xscom_write,
|
|
|
|
.valid.min_access_size = 8,
|
|
|
|
.valid.max_access_size = 8,
|
|
|
|
.impl.min_access_size = 8,
|
|
|
|
.impl.max_access_size = 8,
|
|
|
|
.endianness = DEVICE_BIG_ENDIAN,
|
|
|
|
};
|
|
|
|
|
2019-03-07 23:35:39 +01:00
|
|
|
static uint64_t pnv_lpc_mmio_read(void *opaque, hwaddr addr, unsigned size)
|
|
|
|
{
|
|
|
|
PnvLpcController *lpc = PNV_LPC(opaque);
|
|
|
|
uint64_t val = 0;
|
|
|
|
uint32_t opb_addr = addr & ECCB_CTL_ADDR_MASK;
|
|
|
|
MemTxResult result;
|
|
|
|
|
|
|
|
switch (size) {
|
|
|
|
case 4:
|
|
|
|
val = address_space_ldl(&lpc->opb_as, opb_addr, MEMTXATTRS_UNSPECIFIED,
|
|
|
|
&result);
|
|
|
|
break;
|
|
|
|
case 1:
|
|
|
|
val = address_space_ldub(&lpc->opb_as, opb_addr, MEMTXATTRS_UNSPECIFIED,
|
|
|
|
&result);
|
|
|
|
break;
|
|
|
|
default:
|
|
|
|
qemu_log_mask(LOG_GUEST_ERROR, "OPB read failed at @0x%"
|
|
|
|
HWADDR_PRIx " invalid size %d\n", addr, size);
|
|
|
|
return 0;
|
|
|
|
}
|
|
|
|
|
|
|
|
if (result != MEMTX_OK) {
|
|
|
|
qemu_log_mask(LOG_GUEST_ERROR, "OPB read failed at @0x%"
|
|
|
|
HWADDR_PRIx "\n", addr);
|
|
|
|
}
|
|
|
|
|
|
|
|
return val;
|
|
|
|
}
|
|
|
|
|
|
|
|
static void pnv_lpc_mmio_write(void *opaque, hwaddr addr,
|
|
|
|
uint64_t val, unsigned size)
|
|
|
|
{
|
|
|
|
PnvLpcController *lpc = PNV_LPC(opaque);
|
|
|
|
uint32_t opb_addr = addr & ECCB_CTL_ADDR_MASK;
|
|
|
|
MemTxResult result;
|
|
|
|
|
|
|
|
switch (size) {
|
|
|
|
case 4:
|
|
|
|
address_space_stl(&lpc->opb_as, opb_addr, val, MEMTXATTRS_UNSPECIFIED,
|
|
|
|
&result);
|
|
|
|
break;
|
|
|
|
case 1:
|
|
|
|
address_space_stb(&lpc->opb_as, opb_addr, val, MEMTXATTRS_UNSPECIFIED,
|
|
|
|
&result);
|
|
|
|
break;
|
|
|
|
default:
|
|
|
|
qemu_log_mask(LOG_GUEST_ERROR, "OPB write failed at @0x%"
|
|
|
|
HWADDR_PRIx " invalid size %d\n", addr, size);
|
|
|
|
return;
|
|
|
|
}
|
|
|
|
|
|
|
|
if (result != MEMTX_OK) {
|
|
|
|
qemu_log_mask(LOG_GUEST_ERROR, "OPB write failed at @0x%"
|
|
|
|
HWADDR_PRIx "\n", addr);
|
|
|
|
}
|
|
|
|
}
|
|
|
|
|
|
|
|
static const MemoryRegionOps pnv_lpc_mmio_ops = {
|
|
|
|
.read = pnv_lpc_mmio_read,
|
|
|
|
.write = pnv_lpc_mmio_write,
|
|
|
|
.impl = {
|
|
|
|
.min_access_size = 1,
|
|
|
|
.max_access_size = 4,
|
|
|
|
},
|
|
|
|
.endianness = DEVICE_BIG_ENDIAN,
|
|
|
|
};
|
|
|
|
|
2017-04-11 17:29:59 +02:00
|
|
|
static void pnv_lpc_eval_irqs(PnvLpcController *lpc)
|
|
|
|
{
|
|
|
|
bool lpc_to_opb_irq = false;
|
|
|
|
|
|
|
|
/* Update LPC controller to OPB line */
|
|
|
|
if (lpc->lpc_hc_irqser_ctrl & LPC_HC_IRQSER_EN) {
|
|
|
|
uint32_t irqs;
|
|
|
|
|
|
|
|
irqs = lpc->lpc_hc_irqstat & lpc->lpc_hc_irqmask;
|
|
|
|
lpc_to_opb_irq = (irqs != 0);
|
|
|
|
}
|
|
|
|
|
|
|
|
/* We don't honor the polarity register, it's pointless and unused
|
|
|
|
* anyway
|
|
|
|
*/
|
|
|
|
if (lpc_to_opb_irq) {
|
|
|
|
lpc->opb_irq_input |= OPB_MASTER_IRQ_LPC;
|
|
|
|
} else {
|
|
|
|
lpc->opb_irq_input &= ~OPB_MASTER_IRQ_LPC;
|
|
|
|
}
|
|
|
|
|
|
|
|
/* Update OPB internal latch */
|
|
|
|
lpc->opb_irq_stat |= lpc->opb_irq_input & lpc->opb_irq_mask;
|
|
|
|
|
|
|
|
/* Reflect the interrupt */
|
2022-03-23 08:28:43 +01:00
|
|
|
qemu_set_irq(lpc->psi_irq, lpc->opb_irq_stat != 0);
|
2017-04-11 17:29:59 +02:00
|
|
|
}
|
|
|
|
|
2016-10-22 11:46:42 +02:00
|
|
|
static uint64_t lpc_hc_read(void *opaque, hwaddr addr, unsigned size)
|
|
|
|
{
|
|
|
|
PnvLpcController *lpc = opaque;
|
|
|
|
uint64_t val = 0xfffffffffffffffful;
|
|
|
|
|
|
|
|
switch (addr) {
|
|
|
|
case LPC_HC_FW_SEG_IDSEL:
|
|
|
|
val = lpc->lpc_hc_fw_seg_idsel;
|
|
|
|
break;
|
|
|
|
case LPC_HC_FW_RD_ACC_SIZE:
|
|
|
|
val = lpc->lpc_hc_fw_rd_acc_size;
|
|
|
|
break;
|
|
|
|
case LPC_HC_IRQSER_CTRL:
|
|
|
|
val = lpc->lpc_hc_irqser_ctrl;
|
|
|
|
break;
|
|
|
|
case LPC_HC_IRQMASK:
|
|
|
|
val = lpc->lpc_hc_irqmask;
|
|
|
|
break;
|
|
|
|
case LPC_HC_IRQSTAT:
|
|
|
|
val = lpc->lpc_hc_irqstat;
|
|
|
|
break;
|
|
|
|
case LPC_HC_ERROR_ADDRESS:
|
|
|
|
val = lpc->lpc_hc_error_addr;
|
|
|
|
break;
|
|
|
|
default:
|
2019-03-06 09:50:16 +01:00
|
|
|
qemu_log_mask(LOG_UNIMP, "LPC HC Unimplemented register: 0x%"
|
2016-10-22 11:46:42 +02:00
|
|
|
HWADDR_PRIx "\n", addr);
|
|
|
|
}
|
|
|
|
return val;
|
|
|
|
}
|
|
|
|
|
|
|
|
static void lpc_hc_write(void *opaque, hwaddr addr, uint64_t val,
|
|
|
|
unsigned size)
|
|
|
|
{
|
|
|
|
PnvLpcController *lpc = opaque;
|
|
|
|
|
|
|
|
/* XXX Filter out reserved bits */
|
|
|
|
|
|
|
|
switch (addr) {
|
|
|
|
case LPC_HC_FW_SEG_IDSEL:
|
|
|
|
/* XXX Actually figure out how that works as this impact
|
|
|
|
* memory regions/aliases
|
|
|
|
*/
|
|
|
|
lpc->lpc_hc_fw_seg_idsel = val;
|
|
|
|
break;
|
|
|
|
case LPC_HC_FW_RD_ACC_SIZE:
|
|
|
|
lpc->lpc_hc_fw_rd_acc_size = val;
|
|
|
|
break;
|
|
|
|
case LPC_HC_IRQSER_CTRL:
|
|
|
|
lpc->lpc_hc_irqser_ctrl = val;
|
2017-04-11 17:29:59 +02:00
|
|
|
pnv_lpc_eval_irqs(lpc);
|
2016-10-22 11:46:42 +02:00
|
|
|
break;
|
|
|
|
case LPC_HC_IRQMASK:
|
|
|
|
lpc->lpc_hc_irqmask = val;
|
2017-04-11 17:29:59 +02:00
|
|
|
pnv_lpc_eval_irqs(lpc);
|
2016-10-22 11:46:42 +02:00
|
|
|
break;
|
|
|
|
case LPC_HC_IRQSTAT:
|
|
|
|
lpc->lpc_hc_irqstat &= ~val;
|
2017-04-11 17:29:59 +02:00
|
|
|
pnv_lpc_eval_irqs(lpc);
|
2016-10-22 11:46:42 +02:00
|
|
|
break;
|
|
|
|
case LPC_HC_ERROR_ADDRESS:
|
|
|
|
break;
|
|
|
|
default:
|
2019-03-06 09:50:16 +01:00
|
|
|
qemu_log_mask(LOG_UNIMP, "LPC HC Unimplemented register: 0x%"
|
2016-10-22 11:46:42 +02:00
|
|
|
HWADDR_PRIx "\n", addr);
|
|
|
|
}
|
|
|
|
}
|
|
|
|
|
|
|
|
static const MemoryRegionOps lpc_hc_ops = {
|
|
|
|
.read = lpc_hc_read,
|
|
|
|
.write = lpc_hc_write,
|
|
|
|
.endianness = DEVICE_BIG_ENDIAN,
|
|
|
|
.valid = {
|
|
|
|
.min_access_size = 4,
|
|
|
|
.max_access_size = 4,
|
|
|
|
},
|
|
|
|
.impl = {
|
|
|
|
.min_access_size = 4,
|
|
|
|
.max_access_size = 4,
|
|
|
|
},
|
|
|
|
};
|
|
|
|
|
|
|
|
static uint64_t opb_master_read(void *opaque, hwaddr addr, unsigned size)
|
|
|
|
{
|
|
|
|
PnvLpcController *lpc = opaque;
|
|
|
|
uint64_t val = 0xfffffffffffffffful;
|
|
|
|
|
|
|
|
switch (addr) {
|
2019-03-07 23:35:40 +01:00
|
|
|
case OPB_MASTER_LS_ROUTE0: /* TODO */
|
|
|
|
val = lpc->opb_irq_route0;
|
|
|
|
break;
|
|
|
|
case OPB_MASTER_LS_ROUTE1: /* TODO */
|
|
|
|
val = lpc->opb_irq_route1;
|
|
|
|
break;
|
2016-10-22 11:46:42 +02:00
|
|
|
case OPB_MASTER_LS_IRQ_STAT:
|
|
|
|
val = lpc->opb_irq_stat;
|
|
|
|
break;
|
|
|
|
case OPB_MASTER_LS_IRQ_MASK:
|
|
|
|
val = lpc->opb_irq_mask;
|
|
|
|
break;
|
|
|
|
case OPB_MASTER_LS_IRQ_POL:
|
|
|
|
val = lpc->opb_irq_pol;
|
|
|
|
break;
|
|
|
|
case OPB_MASTER_LS_IRQ_INPUT:
|
|
|
|
val = lpc->opb_irq_input;
|
|
|
|
break;
|
|
|
|
default:
|
2019-03-06 09:50:16 +01:00
|
|
|
qemu_log_mask(LOG_UNIMP, "OPBM: read on unimplemented register: 0x%"
|
2016-10-22 11:46:42 +02:00
|
|
|
HWADDR_PRIx "\n", addr);
|
|
|
|
}
|
|
|
|
|
|
|
|
return val;
|
|
|
|
}
|
|
|
|
|
|
|
|
static void opb_master_write(void *opaque, hwaddr addr,
|
|
|
|
uint64_t val, unsigned size)
|
|
|
|
{
|
|
|
|
PnvLpcController *lpc = opaque;
|
|
|
|
|
|
|
|
switch (addr) {
|
2019-03-07 23:35:40 +01:00
|
|
|
case OPB_MASTER_LS_ROUTE0: /* TODO */
|
|
|
|
lpc->opb_irq_route0 = val;
|
|
|
|
break;
|
|
|
|
case OPB_MASTER_LS_ROUTE1: /* TODO */
|
|
|
|
lpc->opb_irq_route1 = val;
|
|
|
|
break;
|
2016-10-22 11:46:42 +02:00
|
|
|
case OPB_MASTER_LS_IRQ_STAT:
|
|
|
|
lpc->opb_irq_stat &= ~val;
|
2017-04-11 17:29:59 +02:00
|
|
|
pnv_lpc_eval_irqs(lpc);
|
2016-10-22 11:46:42 +02:00
|
|
|
break;
|
|
|
|
case OPB_MASTER_LS_IRQ_MASK:
|
|
|
|
lpc->opb_irq_mask = val;
|
2017-04-11 17:29:59 +02:00
|
|
|
pnv_lpc_eval_irqs(lpc);
|
2016-10-22 11:46:42 +02:00
|
|
|
break;
|
|
|
|
case OPB_MASTER_LS_IRQ_POL:
|
|
|
|
lpc->opb_irq_pol = val;
|
2017-04-11 17:29:59 +02:00
|
|
|
pnv_lpc_eval_irqs(lpc);
|
2016-10-22 11:46:42 +02:00
|
|
|
break;
|
|
|
|
case OPB_MASTER_LS_IRQ_INPUT:
|
|
|
|
/* Read only */
|
|
|
|
break;
|
|
|
|
default:
|
2019-03-06 09:50:16 +01:00
|
|
|
qemu_log_mask(LOG_UNIMP, "OPBM: write on unimplemented register: 0x%"
|
|
|
|
HWADDR_PRIx " val=0x%08"PRIx64"\n", addr, val);
|
2016-10-22 11:46:42 +02:00
|
|
|
}
|
|
|
|
}
|
|
|
|
|
|
|
|
static const MemoryRegionOps opb_master_ops = {
|
|
|
|
.read = opb_master_read,
|
|
|
|
.write = opb_master_write,
|
|
|
|
.endianness = DEVICE_BIG_ENDIAN,
|
|
|
|
.valid = {
|
|
|
|
.min_access_size = 4,
|
|
|
|
.max_access_size = 4,
|
|
|
|
},
|
|
|
|
.impl = {
|
|
|
|
.min_access_size = 4,
|
|
|
|
.max_access_size = 4,
|
|
|
|
},
|
|
|
|
};
|
|
|
|
|
2019-03-07 23:35:37 +01:00
|
|
|
static void pnv_lpc_power8_realize(DeviceState *dev, Error **errp)
|
|
|
|
{
|
|
|
|
PnvLpcController *lpc = PNV_LPC(dev);
|
|
|
|
PnvLpcClass *plc = PNV_LPC_GET_CLASS(dev);
|
|
|
|
Error *local_err = NULL;
|
|
|
|
|
|
|
|
plc->parent_realize(dev, &local_err);
|
|
|
|
if (local_err) {
|
|
|
|
error_propagate(errp, local_err);
|
|
|
|
return;
|
|
|
|
}
|
|
|
|
|
|
|
|
/* P8 uses a XSCOM region for LPC registers */
|
|
|
|
pnv_xscom_region_init(&lpc->xscom_regs, OBJECT(lpc),
|
|
|
|
&pnv_lpc_xscom_ops, lpc, "xscom-lpc",
|
|
|
|
PNV_XSCOM_LPC_SIZE);
|
|
|
|
}
|
|
|
|
|
|
|
|
static void pnv_lpc_power8_class_init(ObjectClass *klass, void *data)
|
|
|
|
{
|
|
|
|
DeviceClass *dc = DEVICE_CLASS(klass);
|
|
|
|
PnvXScomInterfaceClass *xdc = PNV_XSCOM_INTERFACE_CLASS(klass);
|
|
|
|
PnvLpcClass *plc = PNV_LPC_CLASS(klass);
|
|
|
|
|
|
|
|
dc->desc = "PowerNV LPC Controller POWER8";
|
|
|
|
|
|
|
|
xdc->dt_xscom = pnv_lpc_dt_xscom;
|
|
|
|
|
|
|
|
device_class_set_parent_realize(dc, pnv_lpc_power8_realize,
|
|
|
|
&plc->parent_realize);
|
|
|
|
}
|
|
|
|
|
|
|
|
static const TypeInfo pnv_lpc_power8_info = {
|
|
|
|
.name = TYPE_PNV8_LPC,
|
|
|
|
.parent = TYPE_PNV_LPC,
|
|
|
|
.class_init = pnv_lpc_power8_class_init,
|
|
|
|
.interfaces = (InterfaceInfo[]) {
|
|
|
|
{ TYPE_PNV_XSCOM_INTERFACE },
|
|
|
|
{ }
|
|
|
|
}
|
|
|
|
};
|
|
|
|
|
2019-03-07 23:35:39 +01:00
|
|
|
static void pnv_lpc_power9_realize(DeviceState *dev, Error **errp)
|
|
|
|
{
|
|
|
|
PnvLpcController *lpc = PNV_LPC(dev);
|
|
|
|
PnvLpcClass *plc = PNV_LPC_GET_CLASS(dev);
|
|
|
|
Error *local_err = NULL;
|
|
|
|
|
|
|
|
plc->parent_realize(dev, &local_err);
|
|
|
|
if (local_err) {
|
|
|
|
error_propagate(errp, local_err);
|
|
|
|
return;
|
|
|
|
}
|
|
|
|
|
|
|
|
/* P9 uses a MMIO region */
|
|
|
|
memory_region_init_io(&lpc->xscom_regs, OBJECT(lpc), &pnv_lpc_mmio_ops,
|
|
|
|
lpc, "lpcm", PNV9_LPCM_SIZE);
|
|
|
|
}
|
|
|
|
|
|
|
|
static void pnv_lpc_power9_class_init(ObjectClass *klass, void *data)
|
|
|
|
{
|
|
|
|
DeviceClass *dc = DEVICE_CLASS(klass);
|
|
|
|
PnvLpcClass *plc = PNV_LPC_CLASS(klass);
|
|
|
|
|
|
|
|
dc->desc = "PowerNV LPC Controller POWER9";
|
|
|
|
|
|
|
|
device_class_set_parent_realize(dc, pnv_lpc_power9_realize,
|
|
|
|
&plc->parent_realize);
|
|
|
|
}
|
|
|
|
|
|
|
|
static const TypeInfo pnv_lpc_power9_info = {
|
|
|
|
.name = TYPE_PNV9_LPC,
|
|
|
|
.parent = TYPE_PNV_LPC,
|
|
|
|
.class_init = pnv_lpc_power9_class_init,
|
|
|
|
};
|
|
|
|
|
2019-12-05 19:44:54 +01:00
|
|
|
static void pnv_lpc_power10_class_init(ObjectClass *klass, void *data)
|
|
|
|
{
|
|
|
|
DeviceClass *dc = DEVICE_CLASS(klass);
|
|
|
|
|
|
|
|
dc->desc = "PowerNV LPC Controller POWER10";
|
|
|
|
}
|
|
|
|
|
|
|
|
static const TypeInfo pnv_lpc_power10_info = {
|
|
|
|
.name = TYPE_PNV10_LPC,
|
|
|
|
.parent = TYPE_PNV9_LPC,
|
|
|
|
.class_init = pnv_lpc_power10_class_init,
|
|
|
|
};
|
|
|
|
|
2016-10-22 11:46:42 +02:00
|
|
|
static void pnv_lpc_realize(DeviceState *dev, Error **errp)
|
|
|
|
{
|
|
|
|
PnvLpcController *lpc = PNV_LPC(dev);
|
2019-03-07 23:35:37 +01:00
|
|
|
|
2016-10-22 11:46:42 +02:00
|
|
|
/* Reg inits */
|
|
|
|
lpc->lpc_hc_fw_rd_acc_size = LPC_HC_FW_RD_4B;
|
|
|
|
|
|
|
|
/* Create address space and backing MR for the OPB bus */
|
|
|
|
memory_region_init(&lpc->opb_mr, OBJECT(dev), "lpc-opb", 0x100000000ull);
|
|
|
|
address_space_init(&lpc->opb_as, &lpc->opb_mr, "lpc-opb");
|
|
|
|
|
|
|
|
/* Create ISA IO and Mem space regions which are the root of
|
|
|
|
* the ISA bus (ie, ISA address spaces). We don't create a
|
|
|
|
* separate one for FW which we alias to memory.
|
|
|
|
*/
|
|
|
|
memory_region_init(&lpc->isa_io, OBJECT(dev), "isa-io", ISA_IO_SIZE);
|
|
|
|
memory_region_init(&lpc->isa_mem, OBJECT(dev), "isa-mem", ISA_MEM_SIZE);
|
2018-06-11 19:12:10 +02:00
|
|
|
memory_region_init(&lpc->isa_fw, OBJECT(dev), "isa-fw", ISA_FW_SIZE);
|
2016-10-22 11:46:42 +02:00
|
|
|
|
|
|
|
/* Create windows from the OPB space to the ISA space */
|
|
|
|
memory_region_init_alias(&lpc->opb_isa_io, OBJECT(dev), "lpc-isa-io",
|
|
|
|
&lpc->isa_io, 0, LPC_IO_OPB_SIZE);
|
|
|
|
memory_region_add_subregion(&lpc->opb_mr, LPC_IO_OPB_ADDR,
|
|
|
|
&lpc->opb_isa_io);
|
|
|
|
memory_region_init_alias(&lpc->opb_isa_mem, OBJECT(dev), "lpc-isa-mem",
|
|
|
|
&lpc->isa_mem, 0, LPC_MEM_OPB_SIZE);
|
|
|
|
memory_region_add_subregion(&lpc->opb_mr, LPC_MEM_OPB_ADDR,
|
|
|
|
&lpc->opb_isa_mem);
|
|
|
|
memory_region_init_alias(&lpc->opb_isa_fw, OBJECT(dev), "lpc-isa-fw",
|
2018-06-11 19:12:10 +02:00
|
|
|
&lpc->isa_fw, 0, LPC_FW_OPB_SIZE);
|
2016-10-22 11:46:42 +02:00
|
|
|
memory_region_add_subregion(&lpc->opb_mr, LPC_FW_OPB_ADDR,
|
|
|
|
&lpc->opb_isa_fw);
|
|
|
|
|
|
|
|
/* Create MMIO regions for LPC HC and OPB registers */
|
|
|
|
memory_region_init_io(&lpc->opb_master_regs, OBJECT(dev), &opb_master_ops,
|
|
|
|
lpc, "lpc-opb-master", LPC_OPB_REGS_OPB_SIZE);
|
|
|
|
memory_region_add_subregion(&lpc->opb_mr, LPC_OPB_REGS_OPB_ADDR,
|
|
|
|
&lpc->opb_master_regs);
|
|
|
|
memory_region_init_io(&lpc->lpc_hc_regs, OBJECT(dev), &lpc_hc_ops, lpc,
|
|
|
|
"lpc-hc", LPC_HC_REGS_OPB_SIZE);
|
|
|
|
memory_region_add_subregion(&lpc->opb_mr, LPC_HC_REGS_OPB_ADDR,
|
|
|
|
&lpc->lpc_hc_regs);
|
|
|
|
|
2022-03-23 08:28:43 +01:00
|
|
|
qdev_init_gpio_out(DEVICE(dev), &lpc->psi_irq, 1);
|
|
|
|
}
|
2019-11-15 16:55:43 +01:00
|
|
|
|
2016-10-22 11:46:42 +02:00
|
|
|
static void pnv_lpc_class_init(ObjectClass *klass, void *data)
|
|
|
|
{
|
|
|
|
DeviceClass *dc = DEVICE_CLASS(klass);
|
|
|
|
|
|
|
|
dc->realize = pnv_lpc_realize;
|
2019-03-07 23:35:37 +01:00
|
|
|
dc->desc = "PowerNV LPC Controller";
|
2020-01-29 12:37:20 +01:00
|
|
|
dc->user_creatable = false;
|
2016-10-22 11:46:42 +02:00
|
|
|
}
|
|
|
|
|
|
|
|
static const TypeInfo pnv_lpc_info = {
|
|
|
|
.name = TYPE_PNV_LPC,
|
|
|
|
.parent = TYPE_DEVICE,
|
2020-08-22 10:39:20 +02:00
|
|
|
.instance_size = sizeof(PnvLpcController),
|
2016-10-22 11:46:42 +02:00
|
|
|
.class_init = pnv_lpc_class_init,
|
2019-03-07 23:35:37 +01:00
|
|
|
.class_size = sizeof(PnvLpcClass),
|
|
|
|
.abstract = true,
|
2016-10-22 11:46:42 +02:00
|
|
|
};
|
|
|
|
|
|
|
|
static void pnv_lpc_register_types(void)
|
|
|
|
{
|
|
|
|
type_register_static(&pnv_lpc_info);
|
2019-03-07 23:35:37 +01:00
|
|
|
type_register_static(&pnv_lpc_power8_info);
|
2019-03-07 23:35:39 +01:00
|
|
|
type_register_static(&pnv_lpc_power9_info);
|
2019-12-05 19:44:54 +01:00
|
|
|
type_register_static(&pnv_lpc_power10_info);
|
2016-10-22 11:46:42 +02:00
|
|
|
}
|
|
|
|
|
|
|
|
type_init(pnv_lpc_register_types)
|
2017-04-11 17:29:59 +02:00
|
|
|
|
|
|
|
/* If we don't use the built-in LPC interrupt deserializer, we need
|
|
|
|
* to provide a set of qirqs for the ISA bus or things will go bad.
|
|
|
|
*
|
|
|
|
* Most machines using pre-Naples chips (without said deserializer)
|
|
|
|
* have a CPLD that will collect the SerIRQ and shoot them as a
|
|
|
|
* single level interrupt to the P8 chip. So let's setup a hook
|
|
|
|
* for doing just that.
|
|
|
|
*/
|
|
|
|
static void pnv_lpc_isa_irq_handler_cpld(void *opaque, int n, int level)
|
|
|
|
{
|
2017-12-15 14:56:01 +01:00
|
|
|
PnvMachineState *pnv = PNV_MACHINE(qdev_get_machine());
|
2017-04-11 17:29:59 +02:00
|
|
|
uint32_t old_state = pnv->cpld_irqstate;
|
|
|
|
PnvLpcController *lpc = PNV_LPC(opaque);
|
|
|
|
|
|
|
|
if (level) {
|
|
|
|
pnv->cpld_irqstate |= 1u << n;
|
|
|
|
} else {
|
|
|
|
pnv->cpld_irqstate &= ~(1u << n);
|
|
|
|
}
|
|
|
|
|
|
|
|
if (pnv->cpld_irqstate != old_state) {
|
2022-03-23 08:28:43 +01:00
|
|
|
qemu_set_irq(lpc->psi_irq, pnv->cpld_irqstate != 0);
|
2017-04-11 17:29:59 +02:00
|
|
|
}
|
|
|
|
}
|
|
|
|
|
|
|
|
static void pnv_lpc_isa_irq_handler(void *opaque, int n, int level)
|
|
|
|
{
|
|
|
|
PnvLpcController *lpc = PNV_LPC(opaque);
|
|
|
|
|
|
|
|
/* The Naples HW latches the 1 levels, clearing is done by SW */
|
|
|
|
if (level) {
|
|
|
|
lpc->lpc_hc_irqstat |= LPC_HC_IRQ_SERIRQ0 >> n;
|
|
|
|
pnv_lpc_eval_irqs(lpc);
|
|
|
|
}
|
|
|
|
}
|
|
|
|
|
2018-06-15 17:25:34 +02:00
|
|
|
ISABus *pnv_lpc_isa_create(PnvLpcController *lpc, bool use_cpld, Error **errp)
|
2017-04-11 17:29:59 +02:00
|
|
|
{
|
2018-06-15 17:25:34 +02:00
|
|
|
Error *local_err = NULL;
|
|
|
|
ISABus *isa_bus;
|
|
|
|
qemu_irq *irqs;
|
|
|
|
qemu_irq_handler handler;
|
|
|
|
|
|
|
|
/* let isa_bus_new() create its own bridge on SysBus otherwise
|
2020-02-28 13:33:03 +01:00
|
|
|
* devices specified on the command line won't find the bus and
|
2018-06-15 17:25:34 +02:00
|
|
|
* will fail to create.
|
|
|
|
*/
|
|
|
|
isa_bus = isa_bus_new(NULL, &lpc->isa_mem, &lpc->isa_io, &local_err);
|
|
|
|
if (local_err) {
|
|
|
|
error_propagate(errp, local_err);
|
|
|
|
return NULL;
|
|
|
|
}
|
|
|
|
|
2017-04-11 17:29:59 +02:00
|
|
|
/* Not all variants have a working serial irq decoder. If not,
|
|
|
|
* handling of LPC interrupts becomes a platform issue (some
|
|
|
|
* platforms have a CPLD to do it).
|
|
|
|
*/
|
2018-06-15 17:25:34 +02:00
|
|
|
if (use_cpld) {
|
|
|
|
handler = pnv_lpc_isa_irq_handler_cpld;
|
2017-04-11 17:29:59 +02:00
|
|
|
} else {
|
2018-06-15 17:25:34 +02:00
|
|
|
handler = pnv_lpc_isa_irq_handler;
|
2017-04-11 17:29:59 +02:00
|
|
|
}
|
2018-06-15 17:25:34 +02:00
|
|
|
|
|
|
|
irqs = qemu_allocate_irqs(handler, lpc, ISA_NUM_IRQS);
|
|
|
|
|
|
|
|
isa_bus_irqs(isa_bus, irqs);
|
2019-10-28 08:00:27 +01:00
|
|
|
|
2018-06-15 17:25:34 +02:00
|
|
|
return isa_bus;
|
2017-04-11 17:29:59 +02:00
|
|
|
}
|