2019-08-17 11:55:58 +02:00
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riscv_ss = ss.source_set()
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2020-09-01 12:15:41 +02:00
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riscv_ss.add(files('boot.c'), fdt)
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2021-05-13 08:07:56 +02:00
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riscv_ss.add(when: 'CONFIG_RISCV_NUMA', if_true: files('numa.c'))
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2020-09-03 12:40:21 +02:00
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riscv_ss.add(files('riscv_hart.c'))
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2019-08-17 11:55:58 +02:00
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riscv_ss.add(when: 'CONFIG_OPENTITAN', if_true: files('opentitan.c'))
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riscv_ss.add(when: 'CONFIG_RISCV_VIRT', if_true: files('virt.c'))
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2021-04-01 20:14:55 +02:00
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riscv_ss.add(when: 'CONFIG_SHAKTI_C', if_true: files('shakti_c.c'))
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2019-08-17 11:55:58 +02:00
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riscv_ss.add(when: 'CONFIG_SIFIVE_E', if_true: files('sifive_e.c'))
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riscv_ss.add(when: 'CONFIG_SIFIVE_U', if_true: files('sifive_u.c'))
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riscv_ss.add(when: 'CONFIG_SPIKE', if_true: files('spike.c'))
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2020-09-01 03:38:59 +02:00
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riscv_ss.add(when: 'CONFIG_MICROCHIP_PFSOC', if_true: files('microchip_pfsoc.c'))
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2023-03-02 10:12:08 +01:00
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riscv_ss.add(when: 'CONFIG_ACPI', if_true: files('virt-acpi-build.c'))
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2019-08-17 11:55:58 +02:00
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hw_arch += {'riscv': riscv_ss}
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