2021-04-30 15:27:30 +02:00
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/*
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* AArch32 translation, common definitions.
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*
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* Copyright (c) 2021 Linaro, Ltd.
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*
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* This library is free software; you can redistribute it and/or
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* modify it under the terms of the GNU Lesser General Public
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* License as published by the Free Software Foundation; either
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* version 2.1 of the License, or (at your option) any later version.
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*
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* This library is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
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* Lesser General Public License for more details.
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*
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* You should have received a copy of the GNU Lesser General Public
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* License along with this library; if not, see <http://www.gnu.org/licenses/>.
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*/
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2022-05-06 15:49:08 +02:00
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#ifndef TARGET_ARM_TRANSLATE_A32_H
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#define TARGET_ARM_TRANSLATE_A32_H
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2021-04-30 15:27:30 +02:00
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2021-04-30 15:27:31 +02:00
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/* Prototypes for autogenerated disassembler functions */
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bool disas_m_nocp(DisasContext *dc, uint32_t insn);
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2021-06-14 17:09:20 +02:00
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bool disas_mve(DisasContext *dc, uint32_t insn);
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2021-04-30 15:27:35 +02:00
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bool disas_vfp(DisasContext *s, uint32_t insn);
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bool disas_vfp_uncond(DisasContext *s, uint32_t insn);
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2021-04-30 15:27:40 +02:00
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bool disas_neon_dp(DisasContext *s, uint32_t insn);
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bool disas_neon_ls(DisasContext *s, uint32_t insn);
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bool disas_neon_shared(DisasContext *s, uint32_t insn);
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2021-04-30 15:27:31 +02:00
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2021-04-30 15:27:30 +02:00
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void load_reg_var(DisasContext *s, TCGv_i32 var, int reg);
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void arm_gen_condlabel(DisasContext *s);
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bool vfp_access_check(DisasContext *s);
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2021-06-18 16:10:19 +02:00
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bool vfp_access_check_m(DisasContext *s, bool skip_context_update);
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2021-04-30 15:27:30 +02:00
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void read_neon_element32(TCGv_i32 dest, int reg, int ele, MemOp memop);
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void read_neon_element64(TCGv_i64 dest, int reg, int ele, MemOp memop);
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void write_neon_element32(TCGv_i32 src, int reg, int ele, MemOp memop);
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void write_neon_element64(TCGv_i64 src, int reg, int ele, MemOp memop);
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2021-04-30 15:27:34 +02:00
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TCGv_i32 add_reg_for_lit(DisasContext *s, int reg, int ofs);
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void gen_set_cpsr(TCGv_i32 var, uint32_t mask);
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void gen_set_condexec(DisasContext *s);
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void gen_set_pc_im(DisasContext *s, target_ulong val);
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void gen_lookup_tb(DisasContext *s);
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long vfp_reg_offset(bool dp, unsigned reg);
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long neon_full_reg_offset(unsigned reg);
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2021-04-30 15:27:39 +02:00
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long neon_element_offset(int reg, int element, MemOp memop);
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void gen_rev16(TCGv_i32 dest, TCGv_i32 var);
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target/arm: Add handling for PSR.ECI/ICI
On A-profile, PSR bits [15:10][26:25] are always the IT state bits.
On M-profile, some of the reserved encodings of the IT state are used
to instead indicate partial progress through instructions that were
interrupted partway through by an exception and can be resumed.
These resumable instructions fall into two categories:
(1) load/store multiple instructions, where these bits are called
"ICI" and specify the register in the ldm/stm list where execution
should resume. (Specifically: LDM, STM, VLDM, VSTM, VLLDM, VLSTM,
CLRM, VSCCLRM.)
(2) MVE instructions subject to beatwise execution, where these bits
are called "ECI" and specify which beats in this and possibly also
the following MVE insn have been executed.
There are also a few insns (LE, LETP, and BKPT) which do not use the
ICI/ECI bits but must leave them alone.
Otherwise, we should raise an INVSTATE UsageFault for any attempt to
execute an insn with non-zero ICI/ECI bits.
So far we have been able to ignore ECI/ICI, because the architecture
allows the IMPDEF choice of "always restart load/store multiple from
the beginning regardless of ICI state", so the only thing we have
been missing is that we don't raise the INVSTATE fault for bad guest
code. However, MVE requires that we honour ECI bits and do not
rexecute beats of an insn that have already been executed.
Add the support in the decoder for handling ECI/ICI:
* identify the ECI/ICI case in the CONDEXEC TB flags
* when a load/store multiple insn succeeds, it updates the ECI/ICI
state (both in DisasContext and in the CPU state), and sets a flag
to say that the ECI/ICI state was handled
* if we find that the insn we just decoded did not handle the
ECI/ICI state, we delete all the code that we just generated for
it and instead emit the code to raise the INVFAULT. This allows
us to avoid having to update every non-MVE non-LDM/STM insn to
make it check for "is ECI/ICI set?".
We continue with our existing IMPDEF choice of not caring about the
ICI state for the load/store multiples and simply restarting them
from the beginning. Because we don't allow interrupts in the middle
of an insn, the only way we would see this state is if the guest set
ICI manually on return from an exception handler, so it's a corner
case which doesn't merit optimisation.
ICI update for LDM/STM is simple -- it always zeroes the state. ECI
update for MVE beatwise insns will be a little more complex, since
the ECI state may include information for the following insn.
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Message-id: 20210614151007.4545-5-peter.maydell@linaro.org
2021-06-14 17:09:14 +02:00
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void clear_eci_state(DisasContext *s);
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2021-06-17 14:16:28 +02:00
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bool mve_eci_check(DisasContext *s);
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2021-08-13 18:11:56 +02:00
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void mve_update_eci(DisasContext *s);
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2021-06-17 14:16:28 +02:00
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void mve_update_and_store_eci(DisasContext *s);
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2021-08-13 18:11:55 +02:00
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bool mve_skip_vmov(DisasContext *s, int vn, int index, int size);
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2021-04-30 15:27:30 +02:00
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static inline TCGv_i32 load_cpu_offset(int offset)
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{
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TCGv_i32 tmp = tcg_temp_new_i32();
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tcg_gen_ld_i32(tmp, cpu_env, offset);
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return tmp;
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}
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#define load_cpu_field(name) load_cpu_offset(offsetof(CPUARMState, name))
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2022-04-17 19:43:33 +02:00
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void store_cpu_offset(TCGv_i32 var, int offset, int size);
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2021-04-30 15:27:30 +02:00
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2022-04-17 19:43:33 +02:00
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#define store_cpu_field(var, name) \
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store_cpu_offset(var, offsetof(CPUARMState, name), \
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sizeof_field(CPUARMState, name))
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2021-04-30 15:27:30 +02:00
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2021-10-30 01:18:31 +02:00
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#define store_cpu_field_constant(val, name) \
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2022-04-17 19:43:33 +02:00
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store_cpu_field(tcg_constant_i32(val), name)
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2021-10-30 01:18:31 +02:00
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2021-04-30 15:27:30 +02:00
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/* Create a new temporary and set it to the value of a CPU register. */
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static inline TCGv_i32 load_reg(DisasContext *s, int reg)
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{
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TCGv_i32 tmp = tcg_temp_new_i32();
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load_reg_var(s, tmp, reg);
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return tmp;
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}
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2021-04-30 15:27:34 +02:00
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void store_reg(DisasContext *s, int reg, TCGv_i32 var);
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2021-04-30 15:27:32 +02:00
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void gen_aa32_ld_internal_i32(DisasContext *s, TCGv_i32 val,
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TCGv_i32 a32, int index, MemOp opc);
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void gen_aa32_st_internal_i32(DisasContext *s, TCGv_i32 val,
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TCGv_i32 a32, int index, MemOp opc);
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void gen_aa32_ld_internal_i64(DisasContext *s, TCGv_i64 val,
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TCGv_i32 a32, int index, MemOp opc);
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void gen_aa32_st_internal_i64(DisasContext *s, TCGv_i64 val,
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TCGv_i32 a32, int index, MemOp opc);
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void gen_aa32_ld_i32(DisasContext *s, TCGv_i32 val, TCGv_i32 a32,
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int index, MemOp opc);
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void gen_aa32_st_i32(DisasContext *s, TCGv_i32 val, TCGv_i32 a32,
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int index, MemOp opc);
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void gen_aa32_ld_i64(DisasContext *s, TCGv_i64 val, TCGv_i32 a32,
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int index, MemOp opc);
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void gen_aa32_st_i64(DisasContext *s, TCGv_i64 val, TCGv_i32 a32,
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int index, MemOp opc);
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#define DO_GEN_LD(SUFF, OPC) \
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static inline void gen_aa32_ld##SUFF(DisasContext *s, TCGv_i32 val, \
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TCGv_i32 a32, int index) \
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{ \
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gen_aa32_ld_i32(s, val, a32, index, OPC); \
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}
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#define DO_GEN_ST(SUFF, OPC) \
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static inline void gen_aa32_st##SUFF(DisasContext *s, TCGv_i32 val, \
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TCGv_i32 a32, int index) \
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{ \
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gen_aa32_st_i32(s, val, a32, index, OPC); \
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}
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static inline void gen_aa32_ld64(DisasContext *s, TCGv_i64 val,
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TCGv_i32 a32, int index)
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{
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2022-01-06 22:00:51 +01:00
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gen_aa32_ld_i64(s, val, a32, index, MO_UQ);
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2021-04-30 15:27:32 +02:00
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}
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static inline void gen_aa32_st64(DisasContext *s, TCGv_i64 val,
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TCGv_i32 a32, int index)
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{
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2022-01-06 22:00:51 +01:00
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gen_aa32_st_i64(s, val, a32, index, MO_UQ);
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2021-04-30 15:27:32 +02:00
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}
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DO_GEN_LD(8u, MO_UB)
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DO_GEN_LD(16u, MO_UW)
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DO_GEN_LD(32u, MO_UL)
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DO_GEN_ST(8, MO_UB)
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DO_GEN_ST(16, MO_UW)
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DO_GEN_ST(32, MO_UL)
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#undef DO_GEN_LD
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#undef DO_GEN_ST
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2021-04-30 15:27:34 +02:00
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#if defined(CONFIG_USER_ONLY)
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#define IS_USER(s) 1
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#else
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#define IS_USER(s) (s->user)
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#endif
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/* Set NZCV flags from the high 4 bits of var. */
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#define gen_set_nzcv(var) gen_set_cpsr(var, CPSR_NZCV)
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2021-04-30 15:27:39 +02:00
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/* Swap low and high halfwords. */
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static inline void gen_swap_half(TCGv_i32 dest, TCGv_i32 var)
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{
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tcg_gen_rotri_i32(dest, var, 16);
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}
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2021-04-30 15:27:30 +02:00
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#endif
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