2018-08-24 14:17:42 +02:00
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/*
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* ARM IoTKit system control element
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*
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* Copyright (c) 2018 Linaro Limited
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* Written by Peter Maydell
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License version 2 or
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* (at your option) any later version.
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*/
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/*
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* This is a model of the "system control element" which is part of the
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* Arm IoTKit and documented in
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2021-02-15 12:51:38 +01:00
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* https://developer.arm.com/documentation/ecm0601256/latest
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2018-08-24 14:17:42 +02:00
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* Specifically, it implements the "system information block" and
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* "system control register" blocks.
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*
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* QEMU interface:
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2021-02-19 15:45:38 +01:00
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* + QOM property "sse-version": indicates which SSE version this is part of
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* (used to identify whether to provide SSE-200-only registers, etc)
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2018-08-24 14:17:42 +02:00
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* + sysbus MMIO region 0: the system information register bank
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* + sysbus MMIO region 1: the system control register bank
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*/
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#ifndef HW_MISC_IOTKIT_SYSCTL_H
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#define HW_MISC_IOTKIT_SYSCTL_H
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#include "hw/sysbus.h"
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2020-09-03 22:43:22 +02:00
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#include "qom/object.h"
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2018-08-24 14:17:42 +02:00
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#define TYPE_IOTKIT_SYSCTL "iotkit-sysctl"
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2020-09-16 20:25:19 +02:00
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OBJECT_DECLARE_SIMPLE_TYPE(IoTKitSysCtl, IOTKIT_SYSCTL)
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2018-08-24 14:17:42 +02:00
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2020-09-03 22:43:22 +02:00
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struct IoTKitSysCtl {
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2018-08-24 14:17:42 +02:00
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/*< private >*/
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SysBusDevice parent_obj;
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/*< public >*/
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MemoryRegion iomem;
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uint32_t secure_debug;
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uint32_t reset_syndrome;
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uint32_t reset_mask;
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uint32_t gretreg;
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2019-02-28 11:55:16 +01:00
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uint32_t initsvtor0;
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2018-08-24 14:17:42 +02:00
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uint32_t cpuwait;
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uint32_t wicctrl;
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2019-02-28 11:55:16 +01:00
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uint32_t scsecctrl;
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uint32_t fclk_div;
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uint32_t sysclk_div;
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uint32_t clock_force;
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uint32_t initsvtor1;
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uint32_t nmi_enable;
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uint32_t ewctrl;
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2021-02-19 15:45:49 +01:00
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uint32_t pwrctrl;
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2019-02-28 11:55:16 +01:00
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uint32_t pdcm_pd_sys_sense;
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uint32_t pdcm_pd_sram0_sense;
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uint32_t pdcm_pd_sram1_sense;
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uint32_t pdcm_pd_sram2_sense;
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uint32_t pdcm_pd_sram3_sense;
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2021-02-19 15:45:50 +01:00
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uint32_t pdcm_pd_cpu0_sense;
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uint32_t pdcm_pd_vmr0_sense;
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uint32_t pdcm_pd_vmr1_sense;
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2019-02-28 11:55:16 +01:00
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/* Properties */
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2021-02-19 15:45:38 +01:00
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uint32_t sse_version;
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2019-02-28 11:55:16 +01:00
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uint32_t cpuwait_rst;
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uint32_t initsvtor0_rst;
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uint32_t initsvtor1_rst;
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2020-09-03 22:43:22 +02:00
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};
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2018-08-24 14:17:42 +02:00
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#endif
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