2016-09-29 12:32:44 +02:00
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/*
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* libqos PCI bindings for SPAPR
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*
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* This work is licensed under the terms of the GNU GPL, version 2 or later.
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* See the COPYING file in the top-level directory.
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*/
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#include "qemu/osdep.h"
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#include "libqtest.h"
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#include "libqos/pci-spapr.h"
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#include "libqos/rtas.h"
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2018-07-10 16:09:26 +02:00
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#include "libqos/qgraph.h"
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2016-09-29 12:32:44 +02:00
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#include "hw/pci/pci_regs.h"
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#include "qemu-common.h"
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#include "qemu/host-utils.h"
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/*
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* PCI devices are always little-endian
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* SPAPR by default is big-endian
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* so PCI accessors need to swap data endianness
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*/
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2016-10-18 08:02:49 +02:00
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static uint8_t qpci_spapr_pio_readb(QPCIBus *bus, uint32_t addr)
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2016-09-29 12:32:44 +02:00
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{
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2016-10-12 04:30:07 +02:00
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QPCIBusSPAPR *s = container_of(bus, QPCIBusSPAPR, bus);
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2018-11-06 20:15:38 +01:00
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return qtest_readb(bus->qts, s->pio_cpu_base + addr);
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2016-09-29 12:32:44 +02:00
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}
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2016-10-18 08:02:49 +02:00
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static void qpci_spapr_pio_writeb(QPCIBus *bus, uint32_t addr, uint8_t val)
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2016-09-29 12:32:44 +02:00
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{
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2016-10-12 04:30:07 +02:00
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QPCIBusSPAPR *s = container_of(bus, QPCIBusSPAPR, bus);
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2018-11-06 20:15:38 +01:00
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qtest_writeb(bus->qts, s->pio_cpu_base + addr, val);
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2016-09-29 12:32:44 +02:00
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}
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2016-10-18 08:02:49 +02:00
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static uint16_t qpci_spapr_pio_readw(QPCIBus *bus, uint32_t addr)
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2016-09-29 12:32:44 +02:00
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{
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2016-10-12 04:30:07 +02:00
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QPCIBusSPAPR *s = container_of(bus, QPCIBusSPAPR, bus);
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2018-11-06 20:15:38 +01:00
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return bswap16(qtest_readw(bus->qts, s->pio_cpu_base + addr));
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2016-09-29 12:32:44 +02:00
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}
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2016-10-18 08:02:49 +02:00
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static void qpci_spapr_pio_writew(QPCIBus *bus, uint32_t addr, uint16_t val)
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{
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QPCIBusSPAPR *s = container_of(bus, QPCIBusSPAPR, bus);
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2018-11-06 20:15:38 +01:00
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qtest_writew(bus->qts, s->pio_cpu_base + addr, bswap16(val));
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2016-10-18 08:02:49 +02:00
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}
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static uint32_t qpci_spapr_pio_readl(QPCIBus *bus, uint32_t addr)
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{
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QPCIBusSPAPR *s = container_of(bus, QPCIBusSPAPR, bus);
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2018-11-06 20:15:38 +01:00
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return bswap32(qtest_readl(bus->qts, s->pio_cpu_base + addr));
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2016-10-18 08:02:49 +02:00
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}
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static void qpci_spapr_pio_writel(QPCIBus *bus, uint32_t addr, uint32_t val)
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{
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QPCIBusSPAPR *s = container_of(bus, QPCIBusSPAPR, bus);
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2018-11-06 20:15:38 +01:00
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qtest_writel(bus->qts, s->pio_cpu_base + addr, bswap32(val));
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2016-10-18 08:02:49 +02:00
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}
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2016-10-19 06:00:21 +02:00
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static uint64_t qpci_spapr_pio_readq(QPCIBus *bus, uint32_t addr)
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{
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QPCIBusSPAPR *s = container_of(bus, QPCIBusSPAPR, bus);
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2018-11-06 20:15:38 +01:00
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return bswap64(qtest_readq(bus->qts, s->pio_cpu_base + addr));
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2016-10-19 06:00:21 +02:00
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}
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static void qpci_spapr_pio_writeq(QPCIBus *bus, uint32_t addr, uint64_t val)
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{
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QPCIBusSPAPR *s = container_of(bus, QPCIBusSPAPR, bus);
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2018-11-06 20:15:38 +01:00
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qtest_writeq(bus->qts, s->pio_cpu_base + addr, bswap64(val));
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2016-10-19 06:00:21 +02:00
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}
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2016-10-19 05:19:47 +02:00
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static void qpci_spapr_memread(QPCIBus *bus, uint32_t addr,
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void *buf, size_t len)
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{
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QPCIBusSPAPR *s = container_of(bus, QPCIBusSPAPR, bus);
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2018-11-06 20:15:38 +01:00
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qtest_memread(bus->qts, s->mmio32_cpu_base + addr, buf, len);
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2016-10-19 05:19:47 +02:00
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}
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static void qpci_spapr_memwrite(QPCIBus *bus, uint32_t addr,
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const void *buf, size_t len)
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{
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QPCIBusSPAPR *s = container_of(bus, QPCIBusSPAPR, bus);
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2018-11-06 20:15:38 +01:00
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qtest_memwrite(bus->qts, s->mmio32_cpu_base + addr, buf, len);
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2016-10-19 05:19:47 +02:00
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}
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2016-09-29 12:32:44 +02:00
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static uint8_t qpci_spapr_config_readb(QPCIBus *bus, int devfn, uint8_t offset)
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{
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QPCIBusSPAPR *s = container_of(bus, QPCIBusSPAPR, bus);
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uint32_t config_addr = (devfn << 8) | offset;
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2017-09-11 19:19:58 +02:00
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return qrtas_ibm_read_pci_config(bus->qts, s->alloc, s->buid,
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config_addr, 1);
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2016-09-29 12:32:44 +02:00
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}
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static uint16_t qpci_spapr_config_readw(QPCIBus *bus, int devfn, uint8_t offset)
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{
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QPCIBusSPAPR *s = container_of(bus, QPCIBusSPAPR, bus);
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uint32_t config_addr = (devfn << 8) | offset;
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2017-09-11 19:19:58 +02:00
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return qrtas_ibm_read_pci_config(bus->qts, s->alloc, s->buid,
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config_addr, 2);
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2016-09-29 12:32:44 +02:00
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}
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static uint32_t qpci_spapr_config_readl(QPCIBus *bus, int devfn, uint8_t offset)
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{
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QPCIBusSPAPR *s = container_of(bus, QPCIBusSPAPR, bus);
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uint32_t config_addr = (devfn << 8) | offset;
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2017-09-11 19:19:58 +02:00
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return qrtas_ibm_read_pci_config(bus->qts, s->alloc, s->buid,
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config_addr, 4);
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2016-09-29 12:32:44 +02:00
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}
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static void qpci_spapr_config_writeb(QPCIBus *bus, int devfn, uint8_t offset,
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uint8_t value)
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{
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QPCIBusSPAPR *s = container_of(bus, QPCIBusSPAPR, bus);
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uint32_t config_addr = (devfn << 8) | offset;
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2017-09-11 19:19:58 +02:00
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qrtas_ibm_write_pci_config(bus->qts, s->alloc, s->buid,
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config_addr, 1, value);
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2016-09-29 12:32:44 +02:00
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}
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static void qpci_spapr_config_writew(QPCIBus *bus, int devfn, uint8_t offset,
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uint16_t value)
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{
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QPCIBusSPAPR *s = container_of(bus, QPCIBusSPAPR, bus);
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uint32_t config_addr = (devfn << 8) | offset;
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2017-09-11 19:19:58 +02:00
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qrtas_ibm_write_pci_config(bus->qts, s->alloc, s->buid,
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config_addr, 2, value);
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2016-09-29 12:32:44 +02:00
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}
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static void qpci_spapr_config_writel(QPCIBus *bus, int devfn, uint8_t offset,
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uint32_t value)
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{
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QPCIBusSPAPR *s = container_of(bus, QPCIBusSPAPR, bus);
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uint32_t config_addr = (devfn << 8) | offset;
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2017-09-11 19:19:58 +02:00
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qrtas_ibm_write_pci_config(bus->qts, s->alloc, s->buid,
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config_addr, 4, value);
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2016-09-29 12:32:44 +02:00
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}
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2016-10-16 03:04:15 +02:00
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#define SPAPR_PCI_BASE (1ULL << 45)
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2016-10-12 05:07:04 +02:00
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#define SPAPR_PCI_MMIO32_WIN_SIZE 0x80000000 /* 2 GiB */
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2016-10-12 04:30:07 +02:00
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#define SPAPR_PCI_IO_WIN_SIZE 0x10000
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2018-07-10 16:09:26 +02:00
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static void *qpci_spapr_get_driver(void *obj, const char *interface)
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2016-09-29 12:32:44 +02:00
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{
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2018-07-10 16:09:26 +02:00
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QPCIBusSPAPR *qpci = obj;
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if (!g_strcmp0(interface, "pci-bus")) {
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return &qpci->bus;
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}
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fprintf(stderr, "%s not present in pci-bus-spapr", interface);
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g_assert_not_reached();
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}
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2016-09-29 12:32:44 +02:00
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2018-07-10 16:09:26 +02:00
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void qpci_init_spapr(QPCIBusSPAPR *qpci, QTestState *qts,
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QGuestAllocator *alloc)
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{
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2017-09-11 19:19:52 +02:00
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assert(qts);
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2016-09-29 12:32:44 +02:00
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2018-08-09 12:44:56 +02:00
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/* tests cannot use spapr, needs to be fixed first */
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2019-03-23 15:26:36 +01:00
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qpci->bus.has_buggy_msi = true;
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2018-08-09 12:44:56 +02:00
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2018-07-10 16:09:26 +02:00
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qpci->alloc = alloc;
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2016-09-29 12:32:44 +02:00
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2018-07-10 16:09:26 +02:00
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qpci->bus.pio_readb = qpci_spapr_pio_readb;
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qpci->bus.pio_readw = qpci_spapr_pio_readw;
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qpci->bus.pio_readl = qpci_spapr_pio_readl;
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qpci->bus.pio_readq = qpci_spapr_pio_readq;
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2016-10-18 08:02:49 +02:00
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2018-07-10 16:09:26 +02:00
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qpci->bus.pio_writeb = qpci_spapr_pio_writeb;
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qpci->bus.pio_writew = qpci_spapr_pio_writew;
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qpci->bus.pio_writel = qpci_spapr_pio_writel;
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qpci->bus.pio_writeq = qpci_spapr_pio_writeq;
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2016-10-18 08:02:49 +02:00
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2018-07-10 16:09:26 +02:00
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qpci->bus.memread = qpci_spapr_memread;
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qpci->bus.memwrite = qpci_spapr_memwrite;
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2016-10-19 05:19:47 +02:00
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2018-07-10 16:09:26 +02:00
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qpci->bus.config_readb = qpci_spapr_config_readb;
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qpci->bus.config_readw = qpci_spapr_config_readw;
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qpci->bus.config_readl = qpci_spapr_config_readl;
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2016-09-29 12:32:44 +02:00
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2018-07-10 16:09:26 +02:00
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qpci->bus.config_writeb = qpci_spapr_config_writeb;
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qpci->bus.config_writew = qpci_spapr_config_writew;
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qpci->bus.config_writel = qpci_spapr_config_writel;
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2016-09-29 12:32:44 +02:00
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2016-10-12 04:30:07 +02:00
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/* FIXME: We assume the default location of the PHB for now.
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* Ideally we'd parse the device tree deposited in the guest to
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* get the window locations */
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2018-07-10 16:09:26 +02:00
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qpci->buid = 0x800000020000000ULL;
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2016-10-12 04:30:07 +02:00
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2018-07-10 16:09:26 +02:00
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qpci->pio_cpu_base = SPAPR_PCI_BASE;
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qpci->pio.pci_base = 0;
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qpci->pio.size = SPAPR_PCI_IO_WIN_SIZE;
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2016-10-12 04:30:07 +02:00
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2016-10-12 05:07:04 +02:00
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/* 32-bit portion of the MMIO window is at PCI address 2..4 GiB */
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2018-07-10 16:09:26 +02:00
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qpci->mmio32_cpu_base = SPAPR_PCI_BASE;
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qpci->mmio32.pci_base = SPAPR_PCI_MMIO32_WIN_SIZE;
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qpci->mmio32.size = SPAPR_PCI_MMIO32_WIN_SIZE;
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2016-10-12 04:30:07 +02:00
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2018-07-10 16:09:26 +02:00
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qpci->bus.qts = qts;
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qpci->bus.pio_alloc_ptr = 0xc000;
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qpci->bus.mmio_alloc_ptr = qpci->mmio32.pci_base;
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qpci->bus.mmio_limit = qpci->mmio32.pci_base + qpci->mmio32.size;
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2016-09-29 12:32:44 +02:00
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2018-07-10 16:09:26 +02:00
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qpci->obj.get_driver = qpci_spapr_get_driver;
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}
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QPCIBus *qpci_new_spapr(QTestState *qts, QGuestAllocator *alloc)
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{
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QPCIBusSPAPR *qpci = g_new0(QPCIBusSPAPR, 1);
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qpci_init_spapr(qpci, qts, alloc);
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return &qpci->bus;
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2016-09-29 12:32:44 +02:00
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}
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void qpci_free_spapr(QPCIBus *bus)
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{
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2018-07-10 16:09:26 +02:00
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QPCIBusSPAPR *s;
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if (!bus) {
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return;
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}
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s = container_of(bus, QPCIBusSPAPR, bus);
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2016-09-29 12:32:44 +02:00
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g_free(s);
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}
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2018-07-10 16:09:26 +02:00
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static void qpci_spapr_register_nodes(void)
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{
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qos_node_create_driver("pci-bus-spapr", NULL);
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qos_node_produces("pci-bus-spapr", "pci-bus");
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}
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libqos_init(qpci_spapr_register_nodes);
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