2007-11-11 01:04:49 +01:00
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/*
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* SSD0323 OLED controller with OSRAM Pictiva 128x64 display.
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*
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* Copyright (c) 2006-2007 CodeSourcery.
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* Written by Paul Brook
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*
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* This code is licenced under the GPL.
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*/
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/* The controller can support a variety of different displays, but we only
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implement one. Most of the commends relating to brightness and geometry
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setup are ignored. */
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2007-11-17 18:14:51 +01:00
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#include "hw.h"
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#include "devices.h"
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#include "console.h"
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2007-11-11 01:04:49 +01:00
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//#define DEBUG_SSD0323 1
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#ifdef DEBUG_SSD0323
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#define DPRINTF(fmt, args...) \
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do { printf("ssd0323: " fmt , ##args); } while (0)
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#define BADF(fmt, args...) \
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do { fprintf(stderr, "ssd0323: error: " fmt , ##args); exit(1);} while (0)
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#else
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#define DPRINTF(fmt, args...) do {} while(0)
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#define BADF(fmt, args...) \
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do { fprintf(stderr, "ssd0323: error: " fmt , ##args);} while (0)
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#endif
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/* Scaling factor for pixels. */
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#define MAGNIFY 4
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2007-11-18 22:54:57 +01:00
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#define REMAP_SWAP_COLUMN 0x01
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#define REMAP_SWAP_NYBBLE 0x02
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#define REMAP_VERTICAL 0x04
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#define REMAP_SWAP_COM 0x10
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#define REMAP_SPLIT_COM 0x40
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2007-11-11 01:04:49 +01:00
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enum ssd0323_mode
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{
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SSD0323_CMD,
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SSD0323_DATA
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};
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typedef struct {
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DisplayState *ds;
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int cmd_len;
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int cmd;
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int cmd_data[8];
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int row;
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int row_start;
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int row_end;
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int col;
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int col_start;
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int col_end;
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int redraw;
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2007-11-18 22:54:57 +01:00
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int remap;
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2007-11-11 01:04:49 +01:00
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enum ssd0323_mode mode;
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uint8_t framebuffer[128 * 80 / 2];
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} ssd0323_state;
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int ssd0323_xfer_ssi(void *opaque, int data)
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{
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ssd0323_state *s = (ssd0323_state *)opaque;
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switch (s->mode) {
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case SSD0323_DATA:
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DPRINTF("data 0x%02x\n", data);
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s->framebuffer[s->col + s->row * 64] = data;
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2007-11-18 22:54:57 +01:00
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if (s->remap & REMAP_VERTICAL) {
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2007-11-11 01:04:49 +01:00
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s->row++;
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2007-11-18 22:54:57 +01:00
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if (s->row > s->row_end) {
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s->row = s->row_start;
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s->col++;
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}
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if (s->col > s->col_end) {
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s->col = s->col_start;
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}
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} else {
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s->col++;
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if (s->col > s->col_end) {
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s->row++;
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s->col = s->col_start;
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}
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if (s->row > s->row_end) {
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s->row = s->row_start;
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}
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2007-11-11 01:04:49 +01:00
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}
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s->redraw = 1;
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break;
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case SSD0323_CMD:
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DPRINTF("cmd 0x%02x\n", data);
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if (s->cmd_len == 0) {
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s->cmd = data;
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} else {
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s->cmd_data[s->cmd_len - 1] = data;
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}
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s->cmd_len++;
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switch (s->cmd) {
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#define DATA(x) if (s->cmd_len <= (x)) return 0
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case 0x15: /* Set column. */
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DATA(2);
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2007-11-18 22:54:57 +01:00
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s->col = s->col_start = s->cmd_data[0] % 64;
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2007-11-11 01:04:49 +01:00
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s->col_end = s->cmd_data[1] % 64;
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break;
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case 0x75: /* Set row. */
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DATA(2);
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2007-11-18 22:54:57 +01:00
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s->row = s->row_start = s->cmd_data[0] % 80;
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2007-11-11 01:04:49 +01:00
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s->row_end = s->cmd_data[1] % 80;
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break;
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case 0x81: /* Set contrast */
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DATA(1);
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break;
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case 0x84: case 0x85: case 0x86: /* Max current. */
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DATA(0);
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break;
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case 0xa0: /* Set remapping. */
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/* FIXME: Implement this. */
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DATA(1);
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2007-11-18 22:54:57 +01:00
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s->remap = s->cmd_data[0];
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2007-11-11 01:04:49 +01:00
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break;
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case 0xa1: /* Set display start line. */
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case 0xa2: /* Set display offset. */
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/* FIXME: Implement these. */
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DATA(1);
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break;
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case 0xa4: /* Normal mode. */
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case 0xa5: /* All on. */
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case 0xa6: /* All off. */
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case 0xa7: /* Inverse. */
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/* FIXME: Implement these. */
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DATA(0);
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break;
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case 0xa8: /* Set multiplex ratio. */
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case 0xad: /* Set DC-DC converter. */
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DATA(1);
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/* Ignored. Don't care. */
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break;
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case 0xae: /* Display off. */
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case 0xaf: /* Display on. */
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DATA(0);
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/* TODO: Implement power control. */
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break;
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case 0xb1: /* Set phase length. */
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case 0xb2: /* Set row period. */
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case 0xb3: /* Set clock rate. */
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case 0xbc: /* Set precharge. */
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case 0xbe: /* Set VCOMH. */
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case 0xbf: /* Set segment low. */
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DATA(1);
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/* Ignored. Don't care. */
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break;
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case 0xb8: /* Set grey scale table. */
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/* FIXME: Implement this. */
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DATA(8);
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break;
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case 0xe3: /* NOP. */
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DATA(0);
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break;
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2007-11-25 00:35:08 +01:00
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case 0xff: /* Nasty hack because we don't handle chip selects
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properly. */
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break;
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2007-11-11 01:04:49 +01:00
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default:
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BADF("Unknown command: 0x%x\n", data);
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}
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s->cmd_len = 0;
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return 0;
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}
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return 0;
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}
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static void ssd0323_update_display(void *opaque)
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{
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ssd0323_state *s = (ssd0323_state *)opaque;
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uint8_t *dest;
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uint8_t *src;
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int x;
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int y;
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int i;
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int line;
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char *colors[16];
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char colortab[MAGNIFY * 64];
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char *p;
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int dest_width;
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if (s->redraw) {
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switch (s->ds->depth) {
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case 0:
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return;
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case 15:
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dest_width = 2;
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break;
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case 16:
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dest_width = 2;
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break;
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case 24:
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dest_width = 3;
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break;
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case 32:
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dest_width = 4;
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break;
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default:
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BADF("Bad color depth\n");
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return;
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}
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p = colortab;
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for (i = 0; i < 16; i++) {
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int n;
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colors[i] = p;
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switch (s->ds->depth) {
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case 15:
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n = i * 2 + (i >> 3);
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p[0] = n | (n << 5);
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p[1] = (n << 2) | (n >> 3);
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break;
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case 16:
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n = i * 2 + (i >> 3);
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p[0] = n | (n << 6) | ((n << 1) & 0x20);
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p[1] = (n << 3) | (n >> 2);
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break;
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case 24:
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case 32:
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n = (i << 4) | i;
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p[0] = p[1] = p[2] = n;
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break;
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default:
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BADF("Bad color depth\n");
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return;
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}
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p += dest_width;
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}
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2007-11-18 22:54:57 +01:00
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/* TODO: Implement row/column remapping. */
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2007-11-11 01:04:49 +01:00
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dest = s->ds->data;
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for (y = 0; y < 64; y++) {
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line = y;
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src = s->framebuffer + 64 * line;
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for (x = 0; x < 64; x++) {
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int val;
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val = *src >> 4;
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for (i = 0; i < MAGNIFY; i++) {
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memcpy(dest, colors[val], dest_width);
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dest += dest_width;
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}
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val = *src & 0xf;
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for (i = 0; i < MAGNIFY; i++) {
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memcpy(dest, colors[val], dest_width);
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dest += dest_width;
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}
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src++;
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}
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for (i = 1; i < MAGNIFY; i++) {
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memcpy(dest, dest - dest_width * MAGNIFY * 128,
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dest_width * 128 * MAGNIFY);
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dest += dest_width * 128 * MAGNIFY;
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}
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}
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}
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dpy_update(s->ds, 0, 0, 128 * MAGNIFY, 64 * MAGNIFY);
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}
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static void ssd0323_invalidate_display(void * opaque)
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{
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ssd0323_state *s = (ssd0323_state *)opaque;
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s->redraw = 1;
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}
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/* Command/data input. */
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static void ssd0323_cd(void *opaque, int n, int level)
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{
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ssd0323_state *s = (ssd0323_state *)opaque;
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DPRINTF("%s mode\n", level ? "Data" : "Command");
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s->mode = level ? SSD0323_DATA : SSD0323_CMD;
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}
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void *ssd0323_init(DisplayState *ds, qemu_irq *cmd_p)
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{
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ssd0323_state *s;
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qemu_irq *cmd;
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s = (ssd0323_state *)qemu_mallocz(sizeof(ssd0323_state));
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s->ds = ds;
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graphic_console_init(ds, ssd0323_update_display, ssd0323_invalidate_display,
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NULL, s);
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dpy_resize(s->ds, 128 * MAGNIFY, 64 * MAGNIFY);
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s->col_end = 63;
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s->row_end = 79;
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cmd = qemu_allocate_irqs(ssd0323_cd, s, 1);
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*cmd_p = *cmd;
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return s;
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}
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