2019-03-09 18:21:40 +01:00
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/*
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* QEMU ATI SVGA emulation
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*
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* Copyright (c) 2019 BALATON Zoltan
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*
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* This work is licensed under the GNU GPL license version 2 or later.
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*/
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#ifndef ATI_INT_H
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#define ATI_INT_H
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2019-08-16 00:18:09 +02:00
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#include "qemu/timer.h"
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2022-12-22 11:03:28 +01:00
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#include "hw/pci/pci_device.h"
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2019-06-20 12:55:23 +02:00
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#include "hw/i2c/bitbang_i2c.h"
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2019-03-09 18:21:40 +01:00
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#include "vga_int.h"
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2020-09-03 22:43:22 +02:00
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#include "qom/object.h"
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2019-03-09 18:21:40 +01:00
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/*#define DEBUG_ATI*/
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#ifdef DEBUG_ATI
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#define DPRINTF(fmt, ...) printf("%s: " fmt, __func__, ## __VA_ARGS__)
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#else
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#define DPRINTF(fmt, ...) do {} while (0)
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#endif
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#define PCI_VENDOR_ID_ATI 0x1002
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/* Rage128 Pro GL */
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#define PCI_DEVICE_ID_ATI_RAGE128_PF 0x5046
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/* Radeon RV100 (VE) */
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#define PCI_DEVICE_ID_ATI_RADEON_QY 0x5159
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#define TYPE_ATI_VGA "ati-vga"
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2020-09-16 20:25:19 +02:00
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OBJECT_DECLARE_SIMPLE_TYPE(ATIVGAState, ATI_VGA)
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2019-03-09 18:21:40 +01:00
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typedef struct ATIVGARegs {
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uint32_t mm_index;
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uint32_t bios_scratch[8];
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2019-08-16 00:18:09 +02:00
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uint32_t gen_int_cntl;
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uint32_t gen_int_status;
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2019-03-09 18:21:40 +01:00
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uint32_t crtc_gen_cntl;
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uint32_t crtc_ext_cntl;
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uint32_t dac_cntl;
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2019-06-20 12:55:23 +02:00
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uint32_t gpio_vga_ddc;
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uint32_t gpio_dvi_ddc;
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uint32_t gpio_monid;
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2019-08-11 23:14:53 +02:00
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uint32_t config_cntl;
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2019-03-09 18:21:40 +01:00
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uint32_t crtc_h_total_disp;
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uint32_t crtc_h_sync_strt_wid;
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uint32_t crtc_v_total_disp;
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uint32_t crtc_v_sync_strt_wid;
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uint32_t crtc_offset;
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uint32_t crtc_offset_cntl;
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uint32_t crtc_pitch;
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uint32_t cur_offset;
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uint32_t cur_hv_pos;
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uint32_t cur_hv_offs;
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uint32_t cur_color0;
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uint32_t cur_color1;
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uint32_t dst_offset;
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uint32_t dst_pitch;
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uint32_t dst_tile;
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uint32_t dst_width;
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uint32_t dst_height;
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uint32_t src_offset;
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uint32_t src_pitch;
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uint32_t src_tile;
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uint32_t src_x;
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uint32_t src_y;
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uint32_t dst_x;
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uint32_t dst_y;
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uint32_t dp_gui_master_cntl;
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uint32_t dp_brush_bkgd_clr;
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uint32_t dp_brush_frgd_clr;
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uint32_t dp_src_frgd_clr;
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uint32_t dp_src_bkgd_clr;
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uint32_t dp_cntl;
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uint32_t dp_datatype;
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uint32_t dp_mix;
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uint32_t dp_write_mask;
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uint32_t default_offset;
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uint32_t default_pitch;
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2019-06-24 11:50:12 +02:00
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uint32_t default_tile;
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2019-03-09 18:21:40 +01:00
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uint32_t default_sc_bottom_right;
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} ATIVGARegs;
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2020-09-03 22:43:22 +02:00
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struct ATIVGAState {
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2019-03-09 18:21:40 +01:00
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PCIDevice dev;
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VGACommonState vga;
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char *model;
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uint16_t dev_id;
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uint8_t mode;
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bool cursor_guest_mode;
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uint16_t cursor_size;
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uint32_t cursor_offset;
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QEMUCursor *cursor;
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2019-08-16 00:18:09 +02:00
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QEMUTimer vblank_timer;
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2019-07-02 18:38:44 +02:00
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bitbang_i2c_interface bbi2c;
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2019-03-09 18:21:40 +01:00
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MemoryRegion io;
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MemoryRegion mm;
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ATIVGARegs regs;
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2020-09-03 22:43:22 +02:00
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};
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2019-03-09 18:21:40 +01:00
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const char *ati_reg_name(int num);
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void ati_2d_blt(ATIVGAState *s);
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#endif /* ATI_INT_H */
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