2003-09-30 22:34:21 +02:00
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/*
|
2008-05-28 14:51:20 +02:00
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* i386 helpers (without register variable usage)
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2007-09-16 23:08:06 +02:00
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*
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2003-09-30 22:34:21 +02:00
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* Copyright (c) 2003 Fabrice Bellard
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*
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* This library is free software; you can redistribute it and/or
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* modify it under the terms of the GNU Lesser General Public
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* License as published by the Free Software Foundation; either
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2020-10-23 14:28:01 +02:00
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* version 2.1 of the License, or (at your option) any later version.
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2003-09-30 22:34:21 +02:00
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*
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* This library is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
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* Lesser General Public License for more details.
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*
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* You should have received a copy of the GNU Lesser General Public
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2009-07-16 22:47:01 +02:00
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* License along with this library; if not, see <http://www.gnu.org/licenses/>.
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2003-09-30 22:34:21 +02:00
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*/
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2016-01-26 19:17:03 +01:00
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#include "qemu/osdep.h"
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2020-09-30 12:04:40 +02:00
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#include "qapi/qapi-events-run-state.h"
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2008-05-28 14:51:20 +02:00
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#include "cpu.h"
|
2016-03-15 13:18:37 +01:00
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#include "exec/exec-all.h"
|
2019-08-12 07:23:59 +02:00
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#include "sysemu/runstate.h"
|
2020-12-12 16:55:08 +01:00
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#include "kvm/kvm_i386.h"
|
2011-03-02 08:56:08 +01:00
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#ifndef CONFIG_USER_ONLY
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2017-01-10 11:59:55 +01:00
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#include "sysemu/hw_accel.h"
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2012-12-17 18:19:49 +01:00
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#include "monitor/monitor.h"
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2011-03-02 08:56:08 +01:00
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#endif
|
2022-02-07 09:27:56 +01:00
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#include "qemu/log.h"
|
2003-11-14 00:15:36 +01:00
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2022-04-25 00:01:25 +02:00
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void cpu_sync_avx_hflag(CPUX86State *env)
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{
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if ((env->cr[4] & CR4_OSXSAVE_MASK)
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&& (env->xcr0 & (XSTATE_SSE_MASK | XSTATE_YMM_MASK))
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== (XSTATE_SSE_MASK | XSTATE_YMM_MASK)) {
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env->hflags |= HF_AVX_EN_MASK;
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} else{
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env->hflags &= ~HF_AVX_EN_MASK;
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}
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}
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|
2017-07-03 12:12:15 +02:00
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void cpu_sync_bndcs_hflags(CPUX86State *env)
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{
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uint32_t hflags = env->hflags;
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uint32_t hflags2 = env->hflags2;
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uint32_t bndcsr;
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if ((hflags & HF_CPL_MASK) == 3) {
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bndcsr = env->bndcs_regs.cfgu;
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} else {
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bndcsr = env->msr_bndcfgs;
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}
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if ((env->cr[4] & CR4_OSXSAVE_MASK)
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&& (env->xcr0 & XSTATE_BNDCSR_MASK)
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&& (bndcsr & BNDCFG_ENABLE)) {
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hflags |= HF_MPX_EN_MASK;
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} else {
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hflags &= ~HF_MPX_EN_MASK;
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}
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if (bndcsr & BNDCFG_BNDPRESERVE) {
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hflags2 |= HF2_MPX_PR_MASK;
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} else {
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hflags2 &= ~HF2_MPX_PR_MASK;
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}
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env->hflags = hflags;
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env->hflags2 = hflags2;
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}
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|
2012-03-14 01:38:21 +01:00
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static void cpu_x86_version(CPUX86State *env, int *family, int *model)
|
2010-12-10 09:21:14 +01:00
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|
{
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int cpuver = env->cpuid_version;
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if (family == NULL || model == NULL) {
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return;
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}
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*family = (cpuver >> 8) & 0x0f;
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*model = ((cpuver >> 12) & 0xf0) + ((cpuver >> 4) & 0x0f);
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}
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/* Broadcast MCA signal for processor version 06H_EH and above */
|
2012-03-14 01:38:21 +01:00
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int cpu_x86_support_mca_broadcast(CPUX86State *env)
|
2010-12-10 09:21:14 +01:00
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|
|
{
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int family = 0;
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int model = 0;
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cpu_x86_version(env, &family, &model);
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if ((family == 6 && model >= 14) || family > 6) {
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return 1;
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}
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return 0;
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}
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2008-05-28 14:51:20 +02:00
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/***********************************************************/
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/* x86 mmu */
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/* XXX: add PGE support */
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|
2013-01-18 15:19:06 +01:00
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void x86_cpu_set_a20(X86CPU *cpu, int a20_state)
|
2003-09-30 22:34:21 +02:00
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{
|
2013-01-18 15:19:06 +01:00
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CPUX86State *env = &cpu->env;
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|
2008-05-28 14:51:20 +02:00
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a20_state = (a20_state != 0);
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if (a20_state != ((env->a20_mask >> 20) & 1)) {
|
2013-09-04 02:19:44 +02:00
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CPUState *cs = CPU(cpu);
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|
2014-12-13 17:48:18 +01:00
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qemu_log_mask(CPU_LOG_MMU, "A20 update: a20=%d\n", a20_state);
|
2008-05-28 14:51:20 +02:00
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/* if the cpu is currently executing code, we must unlink it and
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all the potentially executing TB */
|
2013-09-04 02:19:44 +02:00
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cpu_interrupt(cs, CPU_INTERRUPT_EXITTB);
|
2007-09-17 10:09:54 +02:00
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|
2008-05-28 14:51:20 +02:00
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/* when a20 is changed, all the MMU mappings are invalid, so
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we must flush everything */
|
2016-11-14 15:17:28 +01:00
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|
tlb_flush(cs);
|
2009-09-29 22:48:49 +02:00
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env->a20_mask = ~(1 << 20) | (a20_state << 20);
|
2003-11-13 00:39:19 +01:00
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|
}
|
2003-09-30 22:34:21 +02:00
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}
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2008-05-28 14:51:20 +02:00
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void cpu_x86_update_cr0(CPUX86State *env, uint32_t new_cr0)
|
2003-09-30 22:34:21 +02:00
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|
{
|
2019-03-23 02:08:48 +01:00
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|
X86CPU *cpu = env_archcpu(env);
|
2008-05-28 14:51:20 +02:00
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int pe_state;
|
2003-09-30 22:34:21 +02:00
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|
2014-12-13 17:48:18 +01:00
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qemu_log_mask(CPU_LOG_MMU, "CR0 update: CR0=0x%08x\n", new_cr0);
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2008-05-28 14:51:20 +02:00
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if ((new_cr0 & (CR0_PG_MASK | CR0_WP_MASK | CR0_PE_MASK)) !=
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(env->cr[0] & (CR0_PG_MASK | CR0_WP_MASK | CR0_PE_MASK))) {
|
2016-11-14 15:17:28 +01:00
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tlb_flush(CPU(cpu));
|
2008-05-28 14:51:20 +02:00
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}
|
2003-09-30 22:34:21 +02:00
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2008-05-28 14:51:20 +02:00
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#ifdef TARGET_X86_64
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if (!(env->cr[0] & CR0_PG_MASK) && (new_cr0 & CR0_PG_MASK) &&
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(env->efer & MSR_EFER_LME)) {
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/* enter in long mode */
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/* XXX: generate an exception */
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if (!(env->cr[4] & CR4_PAE_MASK))
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return;
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env->efer |= MSR_EFER_LMA;
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env->hflags |= HF_LMA_MASK;
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} else if ((env->cr[0] & CR0_PG_MASK) && !(new_cr0 & CR0_PG_MASK) &&
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(env->efer & MSR_EFER_LMA)) {
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/* exit long mode */
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env->efer &= ~MSR_EFER_LMA;
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env->hflags &= ~(HF_LMA_MASK | HF_CS64_MASK);
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env->eip &= 0xffffffff;
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}
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#endif
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env->cr[0] = new_cr0 | CR0_ET_MASK;
|
2003-11-13 00:39:19 +01:00
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|
2008-05-28 14:51:20 +02:00
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/* update PE flag in hidden flags */
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pe_state = (env->cr[0] & CR0_PE_MASK);
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env->hflags = (env->hflags & ~HF_PE_MASK) | (pe_state << HF_PE_SHIFT);
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|
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/* ensure that ADDSEG is always set in real mode */
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env->hflags |= ((pe_state ^ 1) << HF_ADDSEG_SHIFT);
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|
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/* update FPU flags */
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env->hflags = (env->hflags & ~(HF_MP_MASK | HF_EM_MASK | HF_TS_MASK)) |
|
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((new_cr0 << (HF_MP_SHIFT - 1)) & (HF_MP_MASK | HF_EM_MASK | HF_TS_MASK));
|
2003-11-13 00:39:19 +01:00
|
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|
}
|
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|
2008-05-28 14:51:20 +02:00
|
|
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/* XXX: in legacy PAE mode, generate a GPF if reserved bits are set in
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|
the PDPT */
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void cpu_x86_update_cr3(CPUX86State *env, target_ulong new_cr3)
|
2003-11-13 00:39:19 +01:00
|
|
|
{
|
2008-05-28 14:51:20 +02:00
|
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|
env->cr[3] = new_cr3;
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if (env->cr[0] & CR0_PG_MASK) {
|
2014-12-13 17:48:18 +01:00
|
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|
qemu_log_mask(CPU_LOG_MMU,
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|
|
"CR3 update: CR3=" TARGET_FMT_lx "\n", new_cr3);
|
2019-03-23 02:08:48 +01:00
|
|
|
tlb_flush(env_cpu(env));
|
2008-05-28 14:51:20 +02:00
|
|
|
}
|
2003-11-13 00:39:19 +01:00
|
|
|
}
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|
|
2008-05-28 14:51:20 +02:00
|
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|
void cpu_x86_update_cr4(CPUX86State *env, uint32_t new_cr4)
|
2003-11-13 00:39:19 +01:00
|
|
|
{
|
2015-07-02 15:53:40 +02:00
|
|
|
uint32_t hflags;
|
2013-09-04 02:19:44 +02:00
|
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|
|
2008-05-28 14:51:20 +02:00
|
|
|
#if defined(DEBUG_MMU)
|
2016-12-15 01:13:05 +01:00
|
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|
printf("CR4 update: %08x -> %08x\n", (uint32_t)env->cr[4], new_cr4);
|
2008-05-28 14:51:20 +02:00
|
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|
#endif
|
2012-09-26 22:18:43 +02:00
|
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|
if ((new_cr4 ^ env->cr[4]) &
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(CR4_PGE_MASK | CR4_PAE_MASK | CR4_PSE_MASK |
|
2016-12-15 01:13:05 +01:00
|
|
|
CR4_SMEP_MASK | CR4_SMAP_MASK | CR4_LA57_MASK)) {
|
2019-03-23 02:08:48 +01:00
|
|
|
tlb_flush(env_cpu(env));
|
2008-05-28 14:51:20 +02:00
|
|
|
}
|
2015-07-02 15:53:40 +02:00
|
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|
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|
|
/* Clear bits we're going to recompute. */
|
2022-02-06 23:36:09 +01:00
|
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|
hflags = env->hflags & ~(HF_OSFXSR_MASK | HF_SMAP_MASK | HF_UMIP_MASK);
|
2015-07-02 15:53:40 +02:00
|
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|
|
2008-05-28 14:51:20 +02:00
|
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/* SSE handling */
|
2013-04-22 21:00:15 +02:00
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if (!(env->features[FEAT_1_EDX] & CPUID_SSE)) {
|
2008-05-28 14:51:20 +02:00
|
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|
new_cr4 &= ~CR4_OSFXSR_MASK;
|
2012-09-26 22:18:43 +02:00
|
|
|
}
|
|
|
|
if (new_cr4 & CR4_OSFXSR_MASK) {
|
2015-07-02 15:53:40 +02:00
|
|
|
hflags |= HF_OSFXSR_MASK;
|
2012-09-26 22:18:43 +02:00
|
|
|
}
|
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|
|
2013-04-22 21:00:15 +02:00
|
|
|
if (!(env->features[FEAT_7_0_EBX] & CPUID_7_0_EBX_SMAP)) {
|
2012-09-26 22:18:43 +02:00
|
|
|
new_cr4 &= ~CR4_SMAP_MASK;
|
|
|
|
}
|
|
|
|
if (new_cr4 & CR4_SMAP_MASK) {
|
2015-07-02 15:53:40 +02:00
|
|
|
hflags |= HF_SMAP_MASK;
|
2012-09-26 22:18:43 +02:00
|
|
|
}
|
2022-02-06 23:36:09 +01:00
|
|
|
if (!(env->features[FEAT_7_0_ECX] & CPUID_7_0_ECX_UMIP)) {
|
|
|
|
new_cr4 &= ~CR4_UMIP_MASK;
|
|
|
|
}
|
|
|
|
if (new_cr4 & CR4_UMIP_MASK) {
|
|
|
|
hflags |= HF_UMIP_MASK;
|
|
|
|
}
|
2008-05-15 18:46:30 +02:00
|
|
|
|
2016-02-09 14:14:28 +01:00
|
|
|
if (!(env->features[FEAT_7_0_ECX] & CPUID_7_0_ECX_PKU)) {
|
|
|
|
new_cr4 &= ~CR4_PKE_MASK;
|
|
|
|
}
|
2021-01-27 09:28:49 +01:00
|
|
|
if (!(env->features[FEAT_7_0_ECX] & CPUID_7_0_ECX_PKS)) {
|
|
|
|
new_cr4 &= ~CR4_PKS_MASK;
|
|
|
|
}
|
2016-02-09 14:14:28 +01:00
|
|
|
|
2008-05-28 14:51:20 +02:00
|
|
|
env->cr[4] = new_cr4;
|
2015-07-02 15:53:40 +02:00
|
|
|
env->hflags = hflags;
|
2015-07-02 16:57:14 +02:00
|
|
|
|
|
|
|
cpu_sync_bndcs_hflags(env);
|
2022-04-25 00:01:25 +02:00
|
|
|
cpu_sync_avx_hflag(env);
|
2008-05-15 18:46:30 +02:00
|
|
|
}
|
|
|
|
|
2017-07-03 18:10:00 +02:00
|
|
|
#if !defined(CONFIG_USER_ONLY)
|
2019-09-18 12:07:06 +02:00
|
|
|
hwaddr x86_cpu_get_phys_page_attrs_debug(CPUState *cs, vaddr addr,
|
|
|
|
MemTxAttrs *attrs)
|
2005-01-04 00:50:08 +01:00
|
|
|
{
|
2013-06-29 18:55:54 +02:00
|
|
|
X86CPU *cpu = X86_CPU(cs);
|
|
|
|
CPUX86State *env = &cpu->env;
|
2008-05-28 14:51:20 +02:00
|
|
|
target_ulong pde_addr, pte_addr;
|
|
|
|
uint64_t pte;
|
2017-05-11 13:35:28 +02:00
|
|
|
int32_t a20_mask;
|
2008-05-28 14:51:20 +02:00
|
|
|
uint32_t page_offset;
|
|
|
|
int page_size;
|
2005-01-04 00:50:08 +01:00
|
|
|
|
2019-09-18 12:07:06 +02:00
|
|
|
*attrs = cpu_get_mem_attrs(env);
|
|
|
|
|
2017-05-11 13:35:28 +02:00
|
|
|
a20_mask = x86_get_a20_mask(env);
|
2013-08-30 11:58:45 +02:00
|
|
|
if (!(env->cr[0] & CR0_PG_MASK)) {
|
2017-05-11 13:35:28 +02:00
|
|
|
pte = addr & a20_mask;
|
2013-08-30 11:58:45 +02:00
|
|
|
page_size = 4096;
|
|
|
|
} else if (env->cr[4] & CR4_PAE_MASK) {
|
2008-05-28 14:51:20 +02:00
|
|
|
target_ulong pdpe_addr;
|
|
|
|
uint64_t pde, pdpe;
|
2005-01-04 00:50:08 +01:00
|
|
|
|
2008-05-28 14:51:20 +02:00
|
|
|
#ifdef TARGET_X86_64
|
|
|
|
if (env->hflags & HF_LMA_MASK) {
|
2016-12-15 01:13:05 +01:00
|
|
|
bool la57 = env->cr[4] & CR4_LA57_MASK;
|
|
|
|
uint64_t pml5e_addr, pml5e;
|
2008-05-28 14:51:20 +02:00
|
|
|
uint64_t pml4e_addr, pml4e;
|
|
|
|
int32_t sext;
|
|
|
|
|
|
|
|
/* test virtual address sign extension */
|
2016-12-15 01:13:05 +01:00
|
|
|
sext = la57 ? (int64_t)addr >> 56 : (int64_t)addr >> 47;
|
2014-05-27 14:58:47 +02:00
|
|
|
if (sext != 0 && sext != -1) {
|
2008-05-28 14:51:20 +02:00
|
|
|
return -1;
|
2014-05-27 14:58:47 +02:00
|
|
|
}
|
2016-12-15 01:13:05 +01:00
|
|
|
|
|
|
|
if (la57) {
|
|
|
|
pml5e_addr = ((env->cr[3] & ~0xfff) +
|
2017-05-11 13:35:28 +02:00
|
|
|
(((addr >> 48) & 0x1ff) << 3)) & a20_mask;
|
2016-12-15 01:13:05 +01:00
|
|
|
pml5e = x86_ldq_phys(cs, pml5e_addr);
|
|
|
|
if (!(pml5e & PG_PRESENT_MASK)) {
|
|
|
|
return -1;
|
|
|
|
}
|
|
|
|
} else {
|
|
|
|
pml5e = env->cr[3];
|
|
|
|
}
|
|
|
|
|
|
|
|
pml4e_addr = ((pml5e & PG_ADDRESS_MASK) +
|
2017-05-11 13:35:28 +02:00
|
|
|
(((addr >> 39) & 0x1ff) << 3)) & a20_mask;
|
2015-04-08 13:39:37 +02:00
|
|
|
pml4e = x86_ldq_phys(cs, pml4e_addr);
|
2014-05-27 14:58:47 +02:00
|
|
|
if (!(pml4e & PG_PRESENT_MASK)) {
|
2008-05-28 14:51:20 +02:00
|
|
|
return -1;
|
2014-05-27 14:58:47 +02:00
|
|
|
}
|
|
|
|
pdpe_addr = ((pml4e & PG_ADDRESS_MASK) +
|
2017-05-11 13:35:28 +02:00
|
|
|
(((addr >> 30) & 0x1ff) << 3)) & a20_mask;
|
2015-04-08 13:39:37 +02:00
|
|
|
pdpe = x86_ldq_phys(cs, pdpe_addr);
|
2014-05-27 14:58:47 +02:00
|
|
|
if (!(pdpe & PG_PRESENT_MASK)) {
|
2008-05-28 14:51:20 +02:00
|
|
|
return -1;
|
2014-05-27 14:58:47 +02:00
|
|
|
}
|
2014-03-19 22:03:53 +01:00
|
|
|
if (pdpe & PG_PSE_MASK) {
|
|
|
|
page_size = 1024 * 1024 * 1024;
|
2014-05-27 14:58:47 +02:00
|
|
|
pte = pdpe;
|
2014-03-19 22:03:53 +01:00
|
|
|
goto out;
|
|
|
|
}
|
|
|
|
|
2008-05-28 14:51:20 +02:00
|
|
|
} else
|
|
|
|
#endif
|
|
|
|
{
|
|
|
|
pdpe_addr = ((env->cr[3] & ~0x1f) + ((addr >> 27) & 0x18)) &
|
2017-05-11 13:35:28 +02:00
|
|
|
a20_mask;
|
2015-04-08 13:39:37 +02:00
|
|
|
pdpe = x86_ldq_phys(cs, pdpe_addr);
|
2008-05-28 14:51:20 +02:00
|
|
|
if (!(pdpe & PG_PRESENT_MASK))
|
|
|
|
return -1;
|
2005-01-04 00:50:08 +01:00
|
|
|
}
|
|
|
|
|
2014-05-27 14:58:47 +02:00
|
|
|
pde_addr = ((pdpe & PG_ADDRESS_MASK) +
|
2017-05-11 13:35:28 +02:00
|
|
|
(((addr >> 21) & 0x1ff) << 3)) & a20_mask;
|
2015-04-08 13:39:37 +02:00
|
|
|
pde = x86_ldq_phys(cs, pde_addr);
|
2008-05-28 14:51:20 +02:00
|
|
|
if (!(pde & PG_PRESENT_MASK)) {
|
|
|
|
return -1;
|
|
|
|
}
|
|
|
|
if (pde & PG_PSE_MASK) {
|
|
|
|
/* 2 MB page */
|
|
|
|
page_size = 2048 * 1024;
|
2014-05-27 14:58:47 +02:00
|
|
|
pte = pde;
|
2008-05-28 14:51:20 +02:00
|
|
|
} else {
|
|
|
|
/* 4 KB page */
|
2014-05-27 14:58:47 +02:00
|
|
|
pte_addr = ((pde & PG_ADDRESS_MASK) +
|
2017-05-11 13:35:28 +02:00
|
|
|
(((addr >> 12) & 0x1ff) << 3)) & a20_mask;
|
2008-05-28 14:51:20 +02:00
|
|
|
page_size = 4096;
|
2015-04-08 13:39:37 +02:00
|
|
|
pte = x86_ldq_phys(cs, pte_addr);
|
2008-05-28 14:51:20 +02:00
|
|
|
}
|
2014-05-27 14:58:47 +02:00
|
|
|
if (!(pte & PG_PRESENT_MASK)) {
|
2008-08-18 20:00:31 +02:00
|
|
|
return -1;
|
2014-05-27 14:58:47 +02:00
|
|
|
}
|
2005-01-04 00:50:08 +01:00
|
|
|
} else {
|
2008-05-28 14:51:20 +02:00
|
|
|
uint32_t pde;
|
2007-09-17 10:09:54 +02:00
|
|
|
|
2013-08-30 11:58:45 +02:00
|
|
|
/* page directory entry */
|
2017-05-11 13:35:28 +02:00
|
|
|
pde_addr = ((env->cr[3] & ~0xfff) + ((addr >> 20) & 0xffc)) & a20_mask;
|
2015-04-08 13:39:37 +02:00
|
|
|
pde = x86_ldl_phys(cs, pde_addr);
|
2013-08-30 11:58:45 +02:00
|
|
|
if (!(pde & PG_PRESENT_MASK))
|
|
|
|
return -1;
|
|
|
|
if ((pde & PG_PSE_MASK) && (env->cr[4] & CR4_PSE_MASK)) {
|
2016-02-09 11:44:35 +01:00
|
|
|
pte = pde | ((pde & 0x1fe000LL) << (32 - 13));
|
2013-08-30 11:58:45 +02:00
|
|
|
page_size = 4096 * 1024;
|
2008-05-28 14:51:20 +02:00
|
|
|
} else {
|
|
|
|
/* page directory entry */
|
2017-05-11 13:35:28 +02:00
|
|
|
pte_addr = ((pde & ~0xfff) + ((addr >> 10) & 0xffc)) & a20_mask;
|
2015-04-08 13:39:37 +02:00
|
|
|
pte = x86_ldl_phys(cs, pte_addr);
|
2014-05-27 14:58:47 +02:00
|
|
|
if (!(pte & PG_PRESENT_MASK)) {
|
2008-05-28 14:51:20 +02:00
|
|
|
return -1;
|
2014-05-27 14:58:47 +02:00
|
|
|
}
|
2013-08-30 11:58:45 +02:00
|
|
|
page_size = 4096;
|
2008-05-28 14:51:20 +02:00
|
|
|
}
|
2017-05-11 13:35:28 +02:00
|
|
|
pte = pte & a20_mask;
|
2005-01-04 00:50:08 +01:00
|
|
|
}
|
|
|
|
|
2014-03-19 22:03:53 +01:00
|
|
|
#ifdef TARGET_X86_64
|
|
|
|
out:
|
|
|
|
#endif
|
2014-05-27 14:58:47 +02:00
|
|
|
pte &= PG_ADDRESS_MASK & ~(page_size - 1);
|
2008-05-28 14:51:20 +02:00
|
|
|
page_offset = (addr & TARGET_PAGE_MASK) & (page_size - 1);
|
2014-05-27 14:58:47 +02:00
|
|
|
return pte | page_offset;
|
2006-09-24 20:41:56 +02:00
|
|
|
}
|
2008-11-18 22:08:15 +01:00
|
|
|
|
2011-03-02 08:56:15 +01:00
|
|
|
typedef struct MCEInjectionParams {
|
|
|
|
Monitor *mon;
|
|
|
|
int bank;
|
|
|
|
uint64_t status;
|
|
|
|
uint64_t mcg_status;
|
|
|
|
uint64_t addr;
|
|
|
|
uint64_t misc;
|
|
|
|
int flags;
|
|
|
|
} MCEInjectionParams;
|
|
|
|
|
2020-09-30 12:04:40 +02:00
|
|
|
static void emit_guest_memory_failure(MemoryFailureAction action, bool ar,
|
|
|
|
bool recursive)
|
|
|
|
{
|
|
|
|
MemoryFailureFlags mff = {.action_required = ar, .recursive = recursive};
|
|
|
|
|
|
|
|
qapi_event_send_memory_failure(MEMORY_FAILURE_RECIPIENT_GUEST, action,
|
|
|
|
&mff);
|
|
|
|
}
|
|
|
|
|
2016-10-31 10:36:08 +01:00
|
|
|
static void do_inject_x86_mce(CPUState *cs, run_on_cpu_data data)
|
2009-06-23 04:05:14 +02:00
|
|
|
{
|
2016-10-31 10:36:08 +01:00
|
|
|
MCEInjectionParams *params = data.host_ptr;
|
2016-08-02 19:27:33 +02:00
|
|
|
X86CPU *cpu = X86_CPU(cs);
|
|
|
|
CPUX86State *cenv = &cpu->env;
|
2011-03-02 08:56:15 +01:00
|
|
|
uint64_t *banks = cenv->mce_banks + 4 * params->bank;
|
2020-09-30 12:04:38 +02:00
|
|
|
g_autofree char *msg = NULL;
|
|
|
|
bool need_reset = false;
|
2020-09-30 12:04:40 +02:00
|
|
|
bool recursive;
|
|
|
|
bool ar = !!(params->status & MCI_STATUS_AR);
|
2011-03-02 08:56:15 +01:00
|
|
|
|
2016-08-02 19:27:33 +02:00
|
|
|
cpu_synchronize_state(cs);
|
2020-09-30 12:04:40 +02:00
|
|
|
recursive = !!(cenv->mcg_status & MCG_STATUS_MCIP);
|
2011-03-02 08:56:09 +01:00
|
|
|
|
2011-03-02 08:56:10 +01:00
|
|
|
/*
|
|
|
|
* If there is an MCE exception being processed, ignore this SRAO MCE
|
|
|
|
* unless unconditional injection was requested.
|
|
|
|
*/
|
2020-09-30 12:04:40 +02:00
|
|
|
if (!(params->flags & MCE_INJECT_UNCOND_AO) && !ar && recursive) {
|
|
|
|
emit_guest_memory_failure(MEMORY_FAILURE_ACTION_IGNORE, ar, recursive);
|
2011-03-02 08:56:10 +01:00
|
|
|
return;
|
|
|
|
}
|
2011-03-02 08:56:15 +01:00
|
|
|
|
|
|
|
if (params->status & MCI_STATUS_UC) {
|
2011-03-02 08:56:09 +01:00
|
|
|
/*
|
|
|
|
* if MSR_MCG_CTL is not all 1s, the uncorrected error
|
|
|
|
* reporting is disabled
|
|
|
|
*/
|
2011-03-02 08:56:15 +01:00
|
|
|
if ((cenv->mcg_cap & MCG_CTL_P) && cenv->mcg_ctl != ~(uint64_t)0) {
|
|
|
|
monitor_printf(params->mon,
|
2011-03-02 08:56:09 +01:00
|
|
|
"CPU %d: Uncorrected error reporting disabled\n",
|
2016-08-02 19:27:33 +02:00
|
|
|
cs->cpu_index);
|
2011-03-02 08:56:09 +01:00
|
|
|
return;
|
|
|
|
}
|
|
|
|
|
|
|
|
/*
|
|
|
|
* if MSR_MCi_CTL is not all 1s, the uncorrected error
|
|
|
|
* reporting is disabled for the bank
|
|
|
|
*/
|
|
|
|
if (banks[0] != ~(uint64_t)0) {
|
2011-03-02 08:56:15 +01:00
|
|
|
monitor_printf(params->mon,
|
|
|
|
"CPU %d: Uncorrected error reporting disabled for"
|
|
|
|
" bank %d\n",
|
2016-08-02 19:27:33 +02:00
|
|
|
cs->cpu_index, params->bank);
|
2011-03-02 08:56:09 +01:00
|
|
|
return;
|
|
|
|
}
|
|
|
|
|
2020-09-30 12:04:38 +02:00
|
|
|
if (!(cenv->cr[4] & CR4_MCE_MASK)) {
|
|
|
|
need_reset = true;
|
|
|
|
msg = g_strdup_printf("CPU %d: MCE capability is not enabled, "
|
|
|
|
"raising triple fault", cs->cpu_index);
|
2020-10-06 09:48:23 +02:00
|
|
|
} else if (recursive) {
|
|
|
|
need_reset = true;
|
|
|
|
msg = g_strdup_printf("CPU %d: Previous MCE still in progress, "
|
|
|
|
"raising triple fault", cs->cpu_index);
|
2020-09-30 12:04:38 +02:00
|
|
|
}
|
|
|
|
|
|
|
|
if (need_reset) {
|
2020-09-30 12:04:40 +02:00
|
|
|
emit_guest_memory_failure(MEMORY_FAILURE_ACTION_RESET, ar,
|
|
|
|
recursive);
|
2022-09-29 13:42:12 +02:00
|
|
|
monitor_puts(params->mon, msg);
|
2020-09-30 12:04:38 +02:00
|
|
|
qemu_log_mask(CPU_LOG_RESET, "%s\n", msg);
|
2017-05-15 23:41:13 +02:00
|
|
|
qemu_system_reset_request(SHUTDOWN_CAUSE_GUEST_RESET);
|
2009-06-23 04:05:14 +02:00
|
|
|
return;
|
|
|
|
}
|
2020-09-30 12:04:38 +02:00
|
|
|
|
2011-03-02 08:56:08 +01:00
|
|
|
if (banks[1] & MCI_STATUS_VAL) {
|
2011-03-02 08:56:15 +01:00
|
|
|
params->status |= MCI_STATUS_OVER;
|
2011-03-02 08:56:08 +01:00
|
|
|
}
|
2011-03-02 08:56:15 +01:00
|
|
|
banks[2] = params->addr;
|
|
|
|
banks[3] = params->misc;
|
|
|
|
cenv->mcg_status = params->mcg_status;
|
|
|
|
banks[1] = params->status;
|
2016-08-02 19:27:33 +02:00
|
|
|
cpu_interrupt(cs, CPU_INTERRUPT_MCE);
|
2009-06-23 04:05:14 +02:00
|
|
|
} else if (!(banks[1] & MCI_STATUS_VAL)
|
|
|
|
|| !(banks[1] & MCI_STATUS_UC)) {
|
2011-03-02 08:56:08 +01:00
|
|
|
if (banks[1] & MCI_STATUS_VAL) {
|
2011-03-02 08:56:15 +01:00
|
|
|
params->status |= MCI_STATUS_OVER;
|
2011-03-02 08:56:08 +01:00
|
|
|
}
|
2011-03-02 08:56:15 +01:00
|
|
|
banks[2] = params->addr;
|
|
|
|
banks[3] = params->misc;
|
|
|
|
banks[1] = params->status;
|
2011-03-02 08:56:08 +01:00
|
|
|
} else {
|
2009-06-23 04:05:14 +02:00
|
|
|
banks[1] |= MCI_STATUS_OVER;
|
2011-03-02 08:56:08 +01:00
|
|
|
}
|
2020-09-30 12:04:40 +02:00
|
|
|
|
|
|
|
emit_guest_memory_failure(MEMORY_FAILURE_ACTION_INJECT, ar, recursive);
|
2009-06-23 04:05:14 +02:00
|
|
|
}
|
2010-12-10 09:20:44 +01:00
|
|
|
|
2012-05-03 15:22:54 +02:00
|
|
|
void cpu_x86_inject_mce(Monitor *mon, X86CPU *cpu, int bank,
|
2011-03-02 08:56:09 +01:00
|
|
|
uint64_t status, uint64_t mcg_status, uint64_t addr,
|
2011-03-02 08:56:10 +01:00
|
|
|
uint64_t misc, int flags)
|
2010-12-10 09:20:44 +01:00
|
|
|
{
|
2013-05-29 22:29:20 +02:00
|
|
|
CPUState *cs = CPU(cpu);
|
2012-05-03 15:22:54 +02:00
|
|
|
CPUX86State *cenv = &cpu->env;
|
2011-03-02 08:56:15 +01:00
|
|
|
MCEInjectionParams params = {
|
|
|
|
.mon = mon,
|
|
|
|
.bank = bank,
|
|
|
|
.status = status,
|
|
|
|
.mcg_status = mcg_status,
|
|
|
|
.addr = addr,
|
|
|
|
.misc = misc,
|
|
|
|
.flags = flags,
|
|
|
|
};
|
2010-12-10 09:20:44 +01:00
|
|
|
unsigned bank_num = cenv->mcg_cap & 0xff;
|
|
|
|
|
2011-03-02 08:56:09 +01:00
|
|
|
if (!cenv->mcg_cap) {
|
|
|
|
monitor_printf(mon, "MCE injection not supported\n");
|
2010-12-10 09:20:44 +01:00
|
|
|
return;
|
|
|
|
}
|
2011-03-02 08:56:09 +01:00
|
|
|
if (bank >= bank_num) {
|
|
|
|
monitor_printf(mon, "Invalid MCE bank number\n");
|
|
|
|
return;
|
|
|
|
}
|
|
|
|
if (!(status & MCI_STATUS_VAL)) {
|
|
|
|
monitor_printf(mon, "Invalid MCE status code\n");
|
|
|
|
return;
|
|
|
|
}
|
2011-03-02 08:56:10 +01:00
|
|
|
if ((flags & MCE_INJECT_BROADCAST)
|
|
|
|
&& !cpu_x86_support_mca_broadcast(cenv)) {
|
2011-03-02 08:56:09 +01:00
|
|
|
monitor_printf(mon, "Guest CPU does not support MCA broadcast\n");
|
|
|
|
return;
|
2010-12-10 09:21:14 +01:00
|
|
|
}
|
|
|
|
|
2016-10-31 10:36:08 +01:00
|
|
|
run_on_cpu(cs, do_inject_x86_mce, RUN_ON_CPU_HOST_PTR(¶ms));
|
2011-03-02 08:56:16 +01:00
|
|
|
if (flags & MCE_INJECT_BROADCAST) {
|
2013-05-29 22:29:20 +02:00
|
|
|
CPUState *other_cs;
|
|
|
|
|
2011-03-02 08:56:16 +01:00
|
|
|
params.bank = 1;
|
|
|
|
params.status = MCI_STATUS_VAL | MCI_STATUS_UC;
|
|
|
|
params.mcg_status = MCG_STATUS_MCIP | MCG_STATUS_RIPV;
|
|
|
|
params.addr = 0;
|
|
|
|
params.misc = 0;
|
2013-06-24 23:50:24 +02:00
|
|
|
CPU_FOREACH(other_cs) {
|
2013-05-29 22:29:20 +02:00
|
|
|
if (other_cs == cs) {
|
2011-03-02 08:56:16 +01:00
|
|
|
continue;
|
2010-12-10 09:21:02 +01:00
|
|
|
}
|
2016-10-31 10:36:08 +01:00
|
|
|
run_on_cpu(other_cs, do_inject_x86_mce, RUN_ON_CPU_HOST_PTR(¶ms));
|
2010-12-10 09:21:02 +01:00
|
|
|
}
|
2010-12-10 09:20:44 +01:00
|
|
|
}
|
|
|
|
}
|
2012-02-17 18:31:17 +01:00
|
|
|
|
2022-10-24 14:45:29 +02:00
|
|
|
static inline target_ulong get_memio_eip(CPUX86State *env)
|
|
|
|
{
|
|
|
|
#ifdef CONFIG_TCG
|
|
|
|
uint64_t data[TARGET_INSN_START_WORDS];
|
|
|
|
CPUState *cs = env_cpu(env);
|
|
|
|
|
|
|
|
if (!cpu_unwind_state_data(cs, cs->mem_io_pc, data)) {
|
|
|
|
return env->eip;
|
|
|
|
}
|
|
|
|
|
|
|
|
/* Per x86_restore_state_to_opc. */
|
2023-02-27 14:51:42 +01:00
|
|
|
if (cs->tcg_cflags & CF_PCREL) {
|
2022-10-24 14:45:29 +02:00
|
|
|
return (env->eip & TARGET_PAGE_MASK) | data[0];
|
|
|
|
} else {
|
|
|
|
return data[0] - env->segs[R_CS].base;
|
|
|
|
}
|
|
|
|
#else
|
|
|
|
qemu_build_not_reached();
|
|
|
|
#endif
|
|
|
|
}
|
|
|
|
|
2012-03-14 01:38:21 +01:00
|
|
|
void cpu_report_tpr_access(CPUX86State *env, TPRAccess access)
|
2012-02-17 18:31:17 +01:00
|
|
|
{
|
2019-03-23 02:08:48 +01:00
|
|
|
X86CPU *cpu = env_archcpu(env);
|
|
|
|
CPUState *cs = env_cpu(env);
|
2013-12-23 10:04:02 +01:00
|
|
|
|
2021-04-02 22:25:34 +02:00
|
|
|
if (kvm_enabled() || whpx_enabled() || nvmm_enabled()) {
|
2012-02-17 18:31:17 +01:00
|
|
|
env->tpr_access_type = access;
|
|
|
|
|
2013-08-26 03:41:01 +02:00
|
|
|
cpu_interrupt(cs, CPU_INTERRUPT_TPR);
|
2017-07-03 12:12:22 +02:00
|
|
|
} else if (tcg_enabled()) {
|
2022-10-24 14:45:29 +02:00
|
|
|
target_ulong eip = get_memio_eip(env);
|
2012-02-17 18:31:17 +01:00
|
|
|
|
2022-10-24 14:45:29 +02:00
|
|
|
apic_handle_tpr_access_report(cpu->apic_state, eip, access);
|
2012-02-17 18:31:17 +01:00
|
|
|
}
|
|
|
|
}
|
2006-09-27 23:31:59 +02:00
|
|
|
#endif /* !CONFIG_USER_ONLY */
|
2008-11-05 16:34:06 +01:00
|
|
|
|
2009-06-27 09:53:51 +02:00
|
|
|
int cpu_x86_get_descr_debug(CPUX86State *env, unsigned int selector,
|
|
|
|
target_ulong *base, unsigned int *limit,
|
|
|
|
unsigned int *flags)
|
|
|
|
{
|
2019-03-23 02:08:48 +01:00
|
|
|
CPUState *cs = env_cpu(env);
|
2009-06-27 09:53:51 +02:00
|
|
|
SegmentCache *dt;
|
|
|
|
target_ulong ptr;
|
|
|
|
uint32_t e1, e2;
|
|
|
|
int index;
|
|
|
|
|
|
|
|
if (selector & 0x4)
|
|
|
|
dt = &env->ldt;
|
|
|
|
else
|
|
|
|
dt = &env->gdt;
|
|
|
|
index = selector & ~7;
|
|
|
|
ptr = dt->base + index;
|
|
|
|
if ((index + 7) > dt->limit
|
2013-06-29 19:40:58 +02:00
|
|
|
|| cpu_memory_rw_debug(cs, ptr, (uint8_t *)&e1, sizeof(e1), 0) != 0
|
|
|
|
|| cpu_memory_rw_debug(cs, ptr+4, (uint8_t *)&e2, sizeof(e2), 0) != 0)
|
2009-06-27 09:53:51 +02:00
|
|
|
return 0;
|
|
|
|
|
|
|
|
*base = ((e1 >> 16) | ((e2 & 0xff) << 16) | (e2 & 0xff000000));
|
|
|
|
*limit = (e1 & 0xffff) | (e2 & 0x000f0000);
|
|
|
|
if (e2 & DESC_G_MASK)
|
|
|
|
*limit = (*limit << 12) | 0xfff;
|
|
|
|
*flags = e2;
|
|
|
|
|
|
|
|
return 1;
|
|
|
|
}
|
|
|
|
|
2009-06-17 22:26:59 +02:00
|
|
|
#if !defined(CONFIG_USER_ONLY)
|
2012-05-05 01:14:41 +02:00
|
|
|
void do_cpu_init(X86CPU *cpu)
|
2009-06-17 22:26:59 +02:00
|
|
|
{
|
2013-01-17 18:51:17 +01:00
|
|
|
CPUState *cs = CPU(cpu);
|
2012-05-05 01:14:41 +02:00
|
|
|
CPUX86State *env = &cpu->env;
|
2013-03-12 13:16:28 +01:00
|
|
|
CPUX86State *save = g_new(CPUX86State, 1);
|
2013-01-17 18:51:17 +01:00
|
|
|
int sipi = cs->interrupt_request & CPU_INTERRUPT_SIPI;
|
2013-03-12 13:16:28 +01:00
|
|
|
|
|
|
|
*save = *env;
|
2011-03-15 12:26:21 +01:00
|
|
|
|
2013-01-17 18:51:17 +01:00
|
|
|
cpu_reset(cs);
|
|
|
|
cs->interrupt_request = sipi;
|
2013-03-12 13:16:28 +01:00
|
|
|
memcpy(&env->start_init_save, &save->start_init_save,
|
|
|
|
offsetof(CPUX86State, end_init_save) -
|
|
|
|
offsetof(CPUX86State, start_init_save));
|
|
|
|
g_free(save);
|
|
|
|
|
2013-03-08 19:21:50 +01:00
|
|
|
if (kvm_enabled()) {
|
|
|
|
kvm_arch_do_init_vcpu(cpu);
|
|
|
|
}
|
2013-12-23 10:04:02 +01:00
|
|
|
apic_init_reset(cpu->apic_state);
|
2009-06-17 22:26:59 +02:00
|
|
|
}
|
|
|
|
|
2012-05-05 01:14:41 +02:00
|
|
|
void do_cpu_sipi(X86CPU *cpu)
|
2009-06-17 22:26:59 +02:00
|
|
|
{
|
2013-12-23 10:04:02 +01:00
|
|
|
apic_sipi(cpu->apic_state);
|
2009-06-17 22:26:59 +02:00
|
|
|
}
|
|
|
|
#else
|
2012-05-05 01:14:41 +02:00
|
|
|
void do_cpu_init(X86CPU *cpu)
|
2009-06-17 22:26:59 +02:00
|
|
|
{
|
|
|
|
}
|
2012-05-05 01:14:41 +02:00
|
|
|
void do_cpu_sipi(X86CPU *cpu)
|
2009-06-17 22:26:59 +02:00
|
|
|
{
|
|
|
|
}
|
|
|
|
#endif
|
2014-09-13 18:45:14 +02:00
|
|
|
|
2015-04-08 13:39:37 +02:00
|
|
|
#ifndef CONFIG_USER_ONLY
|
2021-03-22 14:27:57 +01:00
|
|
|
|
|
|
|
void cpu_load_efer(CPUX86State *env, uint64_t val)
|
|
|
|
{
|
|
|
|
env->efer = val;
|
|
|
|
env->hflags &= ~(HF_LMA_MASK | HF_SVME_MASK);
|
|
|
|
if (env->efer & MSR_EFER_LMA) {
|
|
|
|
env->hflags |= HF_LMA_MASK;
|
|
|
|
}
|
|
|
|
if (env->efer & MSR_EFER_SVME) {
|
|
|
|
env->hflags |= HF_SVME_MASK;
|
|
|
|
}
|
|
|
|
}
|
|
|
|
|
2015-04-08 13:39:37 +02:00
|
|
|
uint8_t x86_ldub_phys(CPUState *cs, hwaddr addr)
|
|
|
|
{
|
|
|
|
X86CPU *cpu = X86_CPU(cs);
|
|
|
|
CPUX86State *env = &cpu->env;
|
2017-03-01 10:34:48 +01:00
|
|
|
MemTxAttrs attrs = cpu_get_mem_attrs(env);
|
|
|
|
AddressSpace *as = cpu_addressspace(cs, attrs);
|
2015-04-08 13:39:37 +02:00
|
|
|
|
2017-03-01 10:34:48 +01:00
|
|
|
return address_space_ldub(as, addr, attrs, NULL);
|
2015-04-08 13:39:37 +02:00
|
|
|
}
|
|
|
|
|
|
|
|
uint32_t x86_lduw_phys(CPUState *cs, hwaddr addr)
|
|
|
|
{
|
|
|
|
X86CPU *cpu = X86_CPU(cs);
|
|
|
|
CPUX86State *env = &cpu->env;
|
2017-03-01 10:34:48 +01:00
|
|
|
MemTxAttrs attrs = cpu_get_mem_attrs(env);
|
|
|
|
AddressSpace *as = cpu_addressspace(cs, attrs);
|
2015-04-08 13:39:37 +02:00
|
|
|
|
2017-03-01 10:34:48 +01:00
|
|
|
return address_space_lduw(as, addr, attrs, NULL);
|
2015-04-08 13:39:37 +02:00
|
|
|
}
|
|
|
|
|
|
|
|
uint32_t x86_ldl_phys(CPUState *cs, hwaddr addr)
|
|
|
|
{
|
|
|
|
X86CPU *cpu = X86_CPU(cs);
|
|
|
|
CPUX86State *env = &cpu->env;
|
2017-03-01 10:34:48 +01:00
|
|
|
MemTxAttrs attrs = cpu_get_mem_attrs(env);
|
|
|
|
AddressSpace *as = cpu_addressspace(cs, attrs);
|
2015-04-08 13:39:37 +02:00
|
|
|
|
2017-03-01 10:34:48 +01:00
|
|
|
return address_space_ldl(as, addr, attrs, NULL);
|
2015-04-08 13:39:37 +02:00
|
|
|
}
|
|
|
|
|
|
|
|
uint64_t x86_ldq_phys(CPUState *cs, hwaddr addr)
|
|
|
|
{
|
|
|
|
X86CPU *cpu = X86_CPU(cs);
|
|
|
|
CPUX86State *env = &cpu->env;
|
2017-03-01 10:34:48 +01:00
|
|
|
MemTxAttrs attrs = cpu_get_mem_attrs(env);
|
|
|
|
AddressSpace *as = cpu_addressspace(cs, attrs);
|
2015-04-08 13:39:37 +02:00
|
|
|
|
2017-03-01 10:34:48 +01:00
|
|
|
return address_space_ldq(as, addr, attrs, NULL);
|
2015-04-08 13:39:37 +02:00
|
|
|
}
|
|
|
|
|
|
|
|
void x86_stb_phys(CPUState *cs, hwaddr addr, uint8_t val)
|
|
|
|
{
|
|
|
|
X86CPU *cpu = X86_CPU(cs);
|
|
|
|
CPUX86State *env = &cpu->env;
|
2017-03-01 10:34:48 +01:00
|
|
|
MemTxAttrs attrs = cpu_get_mem_attrs(env);
|
|
|
|
AddressSpace *as = cpu_addressspace(cs, attrs);
|
2015-04-08 13:39:37 +02:00
|
|
|
|
2017-03-01 10:34:48 +01:00
|
|
|
address_space_stb(as, addr, val, attrs, NULL);
|
2015-04-08 13:39:37 +02:00
|
|
|
}
|
|
|
|
|
|
|
|
void x86_stl_phys_notdirty(CPUState *cs, hwaddr addr, uint32_t val)
|
|
|
|
{
|
|
|
|
X86CPU *cpu = X86_CPU(cs);
|
|
|
|
CPUX86State *env = &cpu->env;
|
2017-03-01 10:34:48 +01:00
|
|
|
MemTxAttrs attrs = cpu_get_mem_attrs(env);
|
|
|
|
AddressSpace *as = cpu_addressspace(cs, attrs);
|
2015-04-08 13:39:37 +02:00
|
|
|
|
2017-03-01 10:34:48 +01:00
|
|
|
address_space_stl_notdirty(as, addr, val, attrs, NULL);
|
2015-04-08 13:39:37 +02:00
|
|
|
}
|
|
|
|
|
|
|
|
void x86_stw_phys(CPUState *cs, hwaddr addr, uint32_t val)
|
|
|
|
{
|
|
|
|
X86CPU *cpu = X86_CPU(cs);
|
|
|
|
CPUX86State *env = &cpu->env;
|
2017-03-01 10:34:48 +01:00
|
|
|
MemTxAttrs attrs = cpu_get_mem_attrs(env);
|
|
|
|
AddressSpace *as = cpu_addressspace(cs, attrs);
|
2015-04-08 13:39:37 +02:00
|
|
|
|
2017-03-01 10:34:48 +01:00
|
|
|
address_space_stw(as, addr, val, attrs, NULL);
|
2015-04-08 13:39:37 +02:00
|
|
|
}
|
|
|
|
|
|
|
|
void x86_stl_phys(CPUState *cs, hwaddr addr, uint32_t val)
|
|
|
|
{
|
|
|
|
X86CPU *cpu = X86_CPU(cs);
|
|
|
|
CPUX86State *env = &cpu->env;
|
2017-03-01 10:34:48 +01:00
|
|
|
MemTxAttrs attrs = cpu_get_mem_attrs(env);
|
|
|
|
AddressSpace *as = cpu_addressspace(cs, attrs);
|
2015-04-08 13:39:37 +02:00
|
|
|
|
2017-03-01 10:34:48 +01:00
|
|
|
address_space_stl(as, addr, val, attrs, NULL);
|
2015-04-08 13:39:37 +02:00
|
|
|
}
|
|
|
|
|
|
|
|
void x86_stq_phys(CPUState *cs, hwaddr addr, uint64_t val)
|
|
|
|
{
|
|
|
|
X86CPU *cpu = X86_CPU(cs);
|
|
|
|
CPUX86State *env = &cpu->env;
|
2017-03-01 10:34:48 +01:00
|
|
|
MemTxAttrs attrs = cpu_get_mem_attrs(env);
|
|
|
|
AddressSpace *as = cpu_addressspace(cs, attrs);
|
2015-04-08 13:39:37 +02:00
|
|
|
|
2017-03-01 10:34:48 +01:00
|
|
|
address_space_stq(as, addr, val, attrs, NULL);
|
2015-04-08 13:39:37 +02:00
|
|
|
}
|
|
|
|
#endif
|