291 lines
7.1 KiB
C
291 lines
7.1 KiB
C
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/*
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* Copyright (c) 2006-2008 Openedhand Ltd.
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* Written by Andrzej Zaborowski <balrog@zabor.org>
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*
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* This program is free software; you can redistribute it and/or
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* modify it under the terms of the GNU General Public License as
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* published by the Free Software Foundation; either version 2 or
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* (at your option) version 3 of the License.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*
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* You should have received a copy of the GNU General Public License
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* along with this program; if not, write to the Free Software
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* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
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* MA 02111-1307 USA
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*/
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#include "hw.h"
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#include "pxa.h"
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#include "sharpsl.h"
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#undef REG_FMT
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#if TARGET_PHYS_ADDR_BITS == 32
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#define REG_FMT "0x%02x"
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#else
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#define REG_FMT "0x%02lx"
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#endif
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/* SCOOP devices */
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struct scoop_info_s {
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target_phys_addr_t target_base;
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qemu_irq handler[16];
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qemu_irq *in;
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uint16_t status;
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uint16_t power;
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uint32_t gpio_level;
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uint32_t gpio_dir;
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uint32_t prev_level;
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uint16_t mcr;
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uint16_t cdr;
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uint16_t ccr;
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uint16_t irr;
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uint16_t imr;
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uint16_t isr;
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uint16_t gprr;
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};
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#define SCOOP_MCR 0x00
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#define SCOOP_CDR 0x04
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#define SCOOP_CSR 0x08
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#define SCOOP_CPR 0x0c
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#define SCOOP_CCR 0x10
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#define SCOOP_IRR_IRM 0x14
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#define SCOOP_IMR 0x18
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#define SCOOP_ISR 0x1c
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#define SCOOP_GPCR 0x20
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#define SCOOP_GPWR 0x24
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#define SCOOP_GPRR 0x28
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static inline void scoop_gpio_handler_update(struct scoop_info_s *s) {
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uint32_t level, diff;
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int bit;
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level = s->gpio_level & s->gpio_dir;
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for (diff = s->prev_level ^ level; diff; diff ^= 1 << bit) {
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bit = ffs(diff) - 1;
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qemu_set_irq(s->handler[bit], (level >> bit) & 1);
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}
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s->prev_level = level;
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}
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static uint32_t scoop_readb(void *opaque, target_phys_addr_t addr)
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{
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struct scoop_info_s *s = (struct scoop_info_s *) opaque;
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addr -= s->target_base;
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switch (addr) {
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case SCOOP_MCR:
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return s->mcr;
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case SCOOP_CDR:
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return s->cdr;
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case SCOOP_CSR:
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return s->status;
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case SCOOP_CPR:
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return s->power;
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case SCOOP_CCR:
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return s->ccr;
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case SCOOP_IRR_IRM:
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return s->irr;
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case SCOOP_IMR:
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return s->imr;
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case SCOOP_ISR:
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return s->isr;
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case SCOOP_GPCR:
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return s->gpio_dir;
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case SCOOP_GPWR:
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return s->gpio_level;
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case SCOOP_GPRR:
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return s->gprr;
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default:
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zaurus_printf("Bad register offset " REG_FMT "\n", addr);
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}
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return 0;
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}
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static void scoop_writeb(void *opaque, target_phys_addr_t addr, uint32_t value)
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{
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struct scoop_info_s *s = (struct scoop_info_s *) opaque;
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addr -= s->target_base;
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value &= 0xffff;
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switch (addr) {
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case SCOOP_MCR:
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s->mcr = value;
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break;
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case SCOOP_CDR:
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s->cdr = value;
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break;
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case SCOOP_CPR:
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s->power = value;
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if (value & 0x80)
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s->power |= 0x8040;
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break;
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case SCOOP_CCR:
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s->ccr = value;
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break;
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case SCOOP_IRR_IRM:
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s->irr = value;
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break;
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case SCOOP_IMR:
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s->imr = value;
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break;
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case SCOOP_ISR:
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s->isr = value;
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break;
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case SCOOP_GPCR:
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s->gpio_dir = value;
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scoop_gpio_handler_update(s);
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break;
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case SCOOP_GPWR:
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s->gpio_level = value & s->gpio_dir;
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scoop_gpio_handler_update(s);
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break;
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case SCOOP_GPRR:
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s->gprr = value;
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break;
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default:
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zaurus_printf("Bad register offset " REG_FMT "\n", addr);
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}
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}
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CPUReadMemoryFunc *scoop_readfn[] = {
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scoop_readb,
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scoop_readb,
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scoop_readb,
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};
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CPUWriteMemoryFunc *scoop_writefn[] = {
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scoop_writeb,
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scoop_writeb,
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scoop_writeb,
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};
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void scoop_gpio_set(void *opaque, int line, int level)
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{
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struct scoop_info_s *s = (struct scoop_info_s *) s;
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if (level)
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s->gpio_level |= (1 << line);
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else
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s->gpio_level &= ~(1 << line);
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}
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qemu_irq *scoop_gpio_in_get(struct scoop_info_s *s)
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{
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return s->in;
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}
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void scoop_gpio_out_set(struct scoop_info_s *s, int line,
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qemu_irq handler) {
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if (line >= 16) {
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fprintf(stderr, "No GPIO pin %i\n", line);
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exit(-1);
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}
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s->handler[line] = handler;
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}
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static void scoop_save(QEMUFile *f, void *opaque)
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{
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struct scoop_info_s *s = (struct scoop_info_s *) opaque;
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qemu_put_be16s(f, &s->status);
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qemu_put_be16s(f, &s->power);
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qemu_put_be32s(f, &s->gpio_level);
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qemu_put_be32s(f, &s->gpio_dir);
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qemu_put_be32s(f, &s->prev_level);
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qemu_put_be16s(f, &s->mcr);
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qemu_put_be16s(f, &s->cdr);
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qemu_put_be16s(f, &s->ccr);
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qemu_put_be16s(f, &s->irr);
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qemu_put_be16s(f, &s->imr);
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qemu_put_be16s(f, &s->isr);
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qemu_put_be16s(f, &s->gprr);
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}
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static int scoop_load(QEMUFile *f, void *opaque, int version_id)
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{
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struct scoop_info_s *s = (struct scoop_info_s *) opaque;
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qemu_get_be16s(f, &s->status);
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qemu_get_be16s(f, &s->power);
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qemu_get_be32s(f, &s->gpio_level);
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qemu_get_be32s(f, &s->gpio_dir);
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qemu_get_be32s(f, &s->prev_level);
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qemu_get_be16s(f, &s->mcr);
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qemu_get_be16s(f, &s->cdr);
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qemu_get_be16s(f, &s->ccr);
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qemu_get_be16s(f, &s->irr);
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qemu_get_be16s(f, &s->imr);
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qemu_get_be16s(f, &s->isr);
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qemu_get_be16s(f, &s->gprr);
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return 0;
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}
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struct scoop_info_s *scoop_init(struct pxa2xx_state_s *cpu,
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int instance,
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target_phys_addr_t target_base) {
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int iomemtype;
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struct scoop_info_s *s;
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s = (struct scoop_info_s *)
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qemu_mallocz(sizeof(struct scoop_info_s));
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memset(s, 0, sizeof(struct scoop_info_s));
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s->target_base = target_base;
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s->status = 0x02;
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s->in = qemu_allocate_irqs(scoop_gpio_set, s, 16);
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iomemtype = cpu_register_io_memory(0, scoop_readfn,
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scoop_writefn, s);
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cpu_register_physical_memory(s->target_base, 0x1000, iomemtype);
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register_savevm("scoop", instance, 0, scoop_save, scoop_load, s);
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return s;
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}
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/* Write the bootloader parameters memory area. */
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#define MAGIC_CHG(a, b, c, d) ((d << 24) | (c << 16) | (b << 8) | a)
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struct __attribute__ ((__packed__)) sl_param_info {
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uint32_t comadj_keyword;
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int32_t comadj;
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uint32_t uuid_keyword;
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char uuid[16];
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uint32_t touch_keyword;
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int32_t touch_xp;
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int32_t touch_yp;
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int32_t touch_xd;
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int32_t touch_yd;
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uint32_t adadj_keyword;
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int32_t adadj;
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uint32_t phad_keyword;
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int32_t phadadj;
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} zaurus_bootparam = {
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.comadj_keyword = MAGIC_CHG('C', 'M', 'A', 'D'),
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.comadj = 125,
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.uuid_keyword = MAGIC_CHG('U', 'U', 'I', 'D'),
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.uuid = { -1 },
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.touch_keyword = MAGIC_CHG('T', 'U', 'C', 'H'),
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.touch_xp = -1,
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.adadj_keyword = MAGIC_CHG('B', 'V', 'A', 'D'),
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.adadj = -1,
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.phad_keyword = MAGIC_CHG('P', 'H', 'A', 'D'),
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.phadadj = 0x01,
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};
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void sl_bootparam_write(uint32_t ptr)
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{
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memcpy(phys_ram_base + ptr, &zaurus_bootparam,
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sizeof(struct sl_param_info));
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}
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