100 lines
3.1 KiB
C
100 lines
3.1 KiB
C
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/*
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* ARM SMMU support - Internal API
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*
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* Copyright (c) 2017 Red Hat, Inc.
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* Copyright (C) 2014-2016 Broadcom Corporation
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* Written by Prem Mallappa, Eric Auger
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License version 2 as
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* published by the Free Software Foundation.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* General Public License for more details.
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*
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* You should have received a copy of the GNU General Public License along
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* with this program; if not, see <http://www.gnu.org/licenses/>.
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*/
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#ifndef HW_ARM_SMMU_INTERNAL_H
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#define HW_ARM_SMMU_INTERNAL_H
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#define TBI0(tbi) ((tbi) & 0x1)
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#define TBI1(tbi) ((tbi) & 0x2 >> 1)
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/* PTE Manipulation */
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#define ARM_LPAE_PTE_TYPE_SHIFT 0
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#define ARM_LPAE_PTE_TYPE_MASK 0x3
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#define ARM_LPAE_PTE_TYPE_BLOCK 1
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#define ARM_LPAE_PTE_TYPE_TABLE 3
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#define ARM_LPAE_L3_PTE_TYPE_RESERVED 1
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#define ARM_LPAE_L3_PTE_TYPE_PAGE 3
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#define ARM_LPAE_PTE_VALID (1 << 0)
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#define PTE_ADDRESS(pte, shift) \
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(extract64(pte, shift, 47 - shift + 1) << shift)
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#define is_invalid_pte(pte) (!(pte & ARM_LPAE_PTE_VALID))
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#define is_reserved_pte(pte, level) \
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((level == 3) && \
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((pte & ARM_LPAE_PTE_TYPE_MASK) == ARM_LPAE_L3_PTE_TYPE_RESERVED))
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#define is_block_pte(pte, level) \
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((level < 3) && \
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((pte & ARM_LPAE_PTE_TYPE_MASK) == ARM_LPAE_PTE_TYPE_BLOCK))
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#define is_table_pte(pte, level) \
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((level < 3) && \
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((pte & ARM_LPAE_PTE_TYPE_MASK) == ARM_LPAE_PTE_TYPE_TABLE))
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#define is_page_pte(pte, level) \
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((level == 3) && \
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((pte & ARM_LPAE_PTE_TYPE_MASK) == ARM_LPAE_L3_PTE_TYPE_PAGE))
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/* access permissions */
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#define PTE_AP(pte) \
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(extract64(pte, 6, 2))
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#define PTE_APTABLE(pte) \
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(extract64(pte, 61, 2))
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/*
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* TODO: At the moment all transactions are considered as privileged (EL1)
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* as IOMMU translation callback does not pass user/priv attributes.
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*/
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#define is_permission_fault(ap, perm) \
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(((perm) & IOMMU_WO) && ((ap) & 0x2))
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#define PTE_AP_TO_PERM(ap) \
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(IOMMU_ACCESS_FLAG(true, !((ap) & 0x2)))
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/* Level Indexing */
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static inline int level_shift(int level, int granule_sz)
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{
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return granule_sz + (3 - level) * (granule_sz - 3);
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}
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static inline uint64_t level_page_mask(int level, int granule_sz)
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{
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return ~(MAKE_64BIT_MASK(0, level_shift(level, granule_sz)));
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}
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static inline
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uint64_t iova_level_offset(uint64_t iova, int inputsize,
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int level, int gsz)
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{
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return ((iova & MAKE_64BIT_MASK(0, inputsize)) >> level_shift(level, gsz)) &
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MAKE_64BIT_MASK(0, gsz - 3);
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}
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#endif
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