2008-12-07 20:08:45 +01:00
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/*
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* SuperH on-chip PCIC emulation.
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*
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* Copyright (c) 2008 Takashi YOSHII
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*
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* Permission is hereby granted, free of charge, to any person obtaining a copy
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* of this software and associated documentation files (the "Software"), to deal
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* in the Software without restriction, including without limitation the rights
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* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
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* copies of the Software, and to permit persons to whom the Software is
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* furnished to do so, subject to the following conditions:
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*
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* The above copyright notice and this permission notice shall be included in
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* all copies or substantial portions of the Software.
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*
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* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
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* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
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* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
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* THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
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* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
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* OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
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* THE SOFTWARE.
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*/
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2011-01-19 18:23:59 +01:00
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#include "sysbus.h"
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2008-12-07 20:08:45 +01:00
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#include "sh.h"
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#include "pci.h"
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2009-11-12 06:58:30 +01:00
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#include "pci_host.h"
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2008-12-07 20:08:45 +01:00
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#include "bswap.h"
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2011-07-26 13:26:19 +02:00
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#include "exec-memory.h"
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2008-12-07 20:08:45 +01:00
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2011-01-19 18:23:59 +01:00
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typedef struct SHPCIState {
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SysBusDevice busdev;
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2008-12-07 20:08:45 +01:00
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PCIBus *bus;
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PCIDevice *dev;
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2011-01-19 18:23:59 +01:00
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qemu_irq irq[4];
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int memconfig;
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2008-12-07 20:08:45 +01:00
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uint32_t par;
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uint32_t mbr;
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uint32_t iobr;
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2011-01-19 18:23:59 +01:00
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} SHPCIState;
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2008-12-07 20:08:45 +01:00
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2009-10-01 23:12:16 +02:00
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static void sh_pci_reg_write (void *p, target_phys_addr_t addr, uint32_t val)
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2008-12-07 20:08:45 +01:00
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{
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2011-01-19 18:23:59 +01:00
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SHPCIState *pcic = p;
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2008-12-07 20:08:45 +01:00
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switch(addr) {
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case 0 ... 0xfc:
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cpu_to_le32w((uint32_t*)(pcic->dev->config + addr), val);
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break;
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case 0x1c0:
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pcic->par = val;
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break;
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case 0x1c4:
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2010-04-11 23:59:39 +02:00
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pcic->mbr = val & 0xff000001;
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2008-12-07 20:08:45 +01:00
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break;
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case 0x1c8:
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2010-04-11 23:59:39 +02:00
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if ((val & 0xfffc0000) != (pcic->iobr & 0xfffc0000)) {
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cpu_register_physical_memory(pcic->iobr & 0xfffc0000, 0x40000,
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IO_MEM_UNASSIGNED);
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pcic->iobr = val & 0xfffc0001;
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2010-12-08 12:05:49 +01:00
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isa_mmio_init(pcic->iobr & 0xfffc0000, 0x40000);
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2010-04-11 23:59:39 +02:00
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}
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2008-12-07 20:08:45 +01:00
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break;
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case 0x220:
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pci_data_write(pcic->bus, pcic->par, val, 4);
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break;
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}
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}
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2009-10-01 23:12:16 +02:00
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static uint32_t sh_pci_reg_read (void *p, target_phys_addr_t addr)
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2008-12-07 20:08:45 +01:00
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{
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2011-01-19 18:23:59 +01:00
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SHPCIState *pcic = p;
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2008-12-07 20:08:45 +01:00
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switch(addr) {
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case 0 ... 0xfc:
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return le32_to_cpup((uint32_t*)(pcic->dev->config + addr));
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case 0x1c0:
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return pcic->par;
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2010-04-11 23:59:39 +02:00
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case 0x1c4:
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return pcic->mbr;
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case 0x1c8:
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return pcic->iobr;
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2008-12-07 20:08:45 +01:00
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case 0x220:
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return pci_data_read(pcic->bus, pcic->par, 4);
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}
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return 0;
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}
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typedef struct {
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2009-08-25 20:29:31 +02:00
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CPUReadMemoryFunc * const r[3];
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CPUWriteMemoryFunc * const w[3];
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2008-12-07 20:08:45 +01:00
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} MemOp;
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static MemOp sh_pci_reg = {
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{ NULL, NULL, sh_pci_reg_read },
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{ NULL, NULL, sh_pci_reg_write },
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};
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2011-01-19 18:23:59 +01:00
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static int sh_pci_map_irq(PCIDevice *d, int irq_num)
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{
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return (d->devfn >> 3);
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}
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static void sh_pci_set_irq(void *opaque, int irq_num, int level)
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{
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qemu_irq *pic = opaque;
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qemu_set_irq(pic[irq_num], level);
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}
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static void sh_pci_map(SysBusDevice *dev, target_phys_addr_t base)
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{
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SHPCIState *s = FROM_SYSBUS(SHPCIState, dev);
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cpu_register_physical_memory(P4ADDR(base), 0x224, s->memconfig);
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cpu_register_physical_memory(A7ADDR(base), 0x224, s->memconfig);
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s->iobr = 0xfe240000;
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isa_mmio_init(s->iobr, 0x40000);
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}
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static int sh_pci_init_device(SysBusDevice *dev)
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{
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SHPCIState *s;
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int i;
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s = FROM_SYSBUS(SHPCIState, dev);
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for (i = 0; i < 4; i++) {
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sysbus_init_irq(dev, &s->irq[i]);
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}
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s->bus = pci_register_bus(&s->busdev.qdev, "pci",
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sh_pci_set_irq, sh_pci_map_irq,
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2011-07-26 13:26:19 +02:00
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s->irq, get_system_memory(),
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PCI_DEVFN(0, 0), 4);
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2011-01-19 18:23:59 +01:00
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s->memconfig = cpu_register_io_memory(sh_pci_reg.r, sh_pci_reg.w,
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s, DEVICE_NATIVE_ENDIAN);
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sysbus_init_mmio_cb(dev, 0x224, sh_pci_map);
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s->dev = pci_create_simple(s->bus, PCI_DEVFN(0, 0), "sh_pci_host");
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return 0;
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}
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static int sh_pci_host_init(PCIDevice *d)
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{
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pci_set_word(d->config + PCI_COMMAND, PCI_COMMAND_WAIT);
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pci_set_word(d->config + PCI_STATUS, PCI_STATUS_CAP_LIST |
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PCI_STATUS_FAST_BACK | PCI_STATUS_DEVSEL_MEDIUM);
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return 0;
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}
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static PCIDeviceInfo sh_pci_host_info = {
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.qdev.name = "sh_pci_host",
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.qdev.size = sizeof(PCIDevice),
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.init = sh_pci_host_init,
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2011-05-25 03:58:26 +02:00
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.vendor_id = PCI_VENDOR_ID_HITACHI,
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.device_id = PCI_DEVICE_ID_HITACHI_SH7751R,
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2011-01-19 18:23:59 +01:00
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};
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static void sh_pci_register_devices(void)
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2008-12-07 20:08:45 +01:00
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{
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2011-01-19 18:23:59 +01:00
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sysbus_register_dev("sh_pci", sizeof(SHPCIState),
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sh_pci_init_device);
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pci_qdev_register(&sh_pci_host_info);
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2008-12-07 20:08:45 +01:00
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}
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2011-01-19 18:23:59 +01:00
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device_init(sh_pci_register_devices)
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