2004-10-01 00:13:50 +02:00
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/*
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2010-04-03 09:40:47 +02:00
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* QEMU Sun4m iommu emulation
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2004-10-01 00:13:50 +02:00
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*
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2005-04-06 22:47:48 +02:00
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* Copyright (c) 2003-2005 Fabrice Bellard
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2007-09-16 23:08:06 +02:00
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*
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2004-10-01 00:13:50 +02:00
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* Permission is hereby granted, free of charge, to any person obtaining a copy
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* of this software and associated documentation files (the "Software"), to deal
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* in the Software without restriction, including without limitation the rights
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* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
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* copies of the Software, and to permit persons to whom the Software is
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* furnished to do so, subject to the following conditions:
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*
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* The above copyright notice and this permission notice shall be included in
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* all copies or substantial portions of the Software.
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*
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* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
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* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
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* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
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* THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
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* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
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* OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
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* THE SOFTWARE.
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*/
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2009-07-16 15:47:55 +02:00
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2007-11-17 18:14:51 +01:00
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#include "sun4m.h"
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2009-07-16 15:47:55 +02:00
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#include "sysbus.h"
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2010-10-31 10:24:14 +01:00
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#include "trace.h"
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2004-10-01 00:13:50 +02:00
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2010-04-03 09:40:47 +02:00
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/*
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* I/O MMU used by Sun4m systems
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*
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* Chipset docs:
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* "Sun-4M System Architecture (revision 2.0) by Chuck Narad", 950-1373-01,
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* http://mediacast.sun.com/users/Barton808/media/Sun4M_SystemArchitecture_edited2.pdf
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*/
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2008-01-25 20:52:54 +01:00
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#define IOMMU_NREGS (4*4096/4)
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2005-10-30 18:24:19 +01:00
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#define IOMMU_CTRL (0x0000 >> 2)
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2004-10-01 00:13:50 +02:00
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#define IOMMU_CTRL_IMPL 0xf0000000 /* Implementation */
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#define IOMMU_CTRL_VERS 0x0f000000 /* Version */
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#define IOMMU_CTRL_RNGE 0x0000001c /* Mapping RANGE */
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#define IOMMU_RNGE_16MB 0x00000000 /* 0xff000000 -> 0xffffffff */
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#define IOMMU_RNGE_32MB 0x00000004 /* 0xfe000000 -> 0xffffffff */
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#define IOMMU_RNGE_64MB 0x00000008 /* 0xfc000000 -> 0xffffffff */
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#define IOMMU_RNGE_128MB 0x0000000c /* 0xf8000000 -> 0xffffffff */
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#define IOMMU_RNGE_256MB 0x00000010 /* 0xf0000000 -> 0xffffffff */
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#define IOMMU_RNGE_512MB 0x00000014 /* 0xe0000000 -> 0xffffffff */
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#define IOMMU_RNGE_1GB 0x00000018 /* 0xc0000000 -> 0xffffffff */
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#define IOMMU_RNGE_2GB 0x0000001c /* 0x80000000 -> 0xffffffff */
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#define IOMMU_CTRL_ENAB 0x00000001 /* IOMMU Enable */
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2005-10-30 18:24:19 +01:00
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#define IOMMU_CTRL_MASK 0x0000001d
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#define IOMMU_BASE (0x0004 >> 2)
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#define IOMMU_BASE_MASK 0x07fffc00
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#define IOMMU_TLBFLUSH (0x0014 >> 2)
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#define IOMMU_TLBFLUSH_MASK 0xffffffff
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#define IOMMU_PGFLUSH (0x0018 >> 2)
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#define IOMMU_PGFLUSH_MASK 0xffffffff
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2007-08-11 09:52:09 +02:00
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#define IOMMU_AFSR (0x1000 >> 2)
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#define IOMMU_AFSR_ERR 0x80000000 /* LE, TO, or BE asserted */
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2007-12-01 15:51:23 +01:00
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#define IOMMU_AFSR_LE 0x40000000 /* SBUS reports error after
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transaction */
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#define IOMMU_AFSR_TO 0x20000000 /* Write access took more than
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12.8 us. */
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#define IOMMU_AFSR_BE 0x10000000 /* Write access received error
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acknowledge */
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2007-08-11 09:52:09 +02:00
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#define IOMMU_AFSR_SIZE 0x0e000000 /* Size of transaction causing error */
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#define IOMMU_AFSR_S 0x01000000 /* Sparc was in supervisor mode */
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2007-12-01 15:51:23 +01:00
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#define IOMMU_AFSR_RESV 0x00800000 /* Reserved, forced to 0x8 by
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hardware */
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2007-08-11 09:52:09 +02:00
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#define IOMMU_AFSR_ME 0x00080000 /* Multiple errors occurred */
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#define IOMMU_AFSR_RD 0x00040000 /* A read operation was in progress */
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#define IOMMU_AFSR_FAV 0x00020000 /* IOMMU afar has valid contents */
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2007-12-01 15:51:24 +01:00
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#define IOMMU_AFSR_MASK 0xff0fffff
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2007-08-11 09:52:09 +02:00
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#define IOMMU_AFAR (0x1004 >> 2)
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2008-12-21 11:46:23 +01:00
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#define IOMMU_AER (0x1008 >> 2) /* Arbiter Enable Register */
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#define IOMMU_AER_EN_P0_ARB 0x00000001 /* MBus master 0x8 (Always 1) */
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#define IOMMU_AER_EN_P1_ARB 0x00000002 /* MBus master 0x9 */
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#define IOMMU_AER_EN_P2_ARB 0x00000004 /* MBus master 0xa */
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#define IOMMU_AER_EN_P3_ARB 0x00000008 /* MBus master 0xb */
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#define IOMMU_AER_EN_0 0x00010000 /* SBus slot 0 */
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#define IOMMU_AER_EN_1 0x00020000 /* SBus slot 1 */
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#define IOMMU_AER_EN_2 0x00040000 /* SBus slot 2 */
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#define IOMMU_AER_EN_3 0x00080000 /* SBus slot 3 */
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#define IOMMU_AER_EN_F 0x00100000 /* SBus on-board */
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#define IOMMU_AER_SBW 0x80000000 /* S-to-M asynchronous writes */
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#define IOMMU_AER_MASK 0x801f000f
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2005-10-30 18:24:19 +01:00
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#define IOMMU_SBCFG0 (0x1010 >> 2) /* SBUS configration per-slot */
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#define IOMMU_SBCFG1 (0x1014 >> 2) /* SBUS configration per-slot */
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#define IOMMU_SBCFG2 (0x1018 >> 2) /* SBUS configration per-slot */
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#define IOMMU_SBCFG3 (0x101c >> 2) /* SBUS configration per-slot */
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2007-12-01 15:51:23 +01:00
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#define IOMMU_SBCFG_SAB30 0x00010000 /* Phys-address bit 30 when
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bypass enabled */
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2005-10-30 18:24:19 +01:00
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#define IOMMU_SBCFG_BA16 0x00000004 /* Slave supports 16 byte bursts */
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#define IOMMU_SBCFG_BA8 0x00000002 /* Slave supports 8 byte bursts */
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#define IOMMU_SBCFG_BYPASS 0x00000001 /* Bypass IOMMU, treat all addresses
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2007-10-06 13:28:21 +02:00
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produced by this device as pure
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2005-10-30 18:24:19 +01:00
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physical. */
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#define IOMMU_SBCFG_MASK 0x00010003
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#define IOMMU_ARBEN (0x2000 >> 2) /* SBUS arbitration enable */
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#define IOMMU_ARBEN_MASK 0x001f0000
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#define IOMMU_MID 0x00000008
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2004-10-01 00:13:50 +02:00
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2008-01-25 20:52:54 +01:00
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#define IOMMU_MASK_ID (0x3018 >> 2) /* Mask ID */
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#define IOMMU_MASK_ID_MASK 0x00ffffff
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#define IOMMU_MSII_MASK 0x26000000 /* microSPARC II mask number */
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#define IOMMU_TS_MASK 0x23000000 /* turboSPARC mask number */
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2004-10-01 00:13:50 +02:00
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/* The format of an iopte in the page tables */
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2007-12-01 15:51:25 +01:00
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#define IOPTE_PAGE 0xffffff00 /* Physical page number (PA[35:12]) */
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2007-12-01 15:51:23 +01:00
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#define IOPTE_CACHE 0x00000080 /* Cached (in vme IOCACHE or
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Viking/MXCC) */
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2011-04-26 10:29:36 +02:00
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#define IOPTE_WRITE 0x00000004 /* Writable */
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2004-10-01 00:13:50 +02:00
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#define IOPTE_VALID 0x00000002 /* IOPTE is valid */
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#define IOPTE_WAZ 0x00000001 /* Write as zeros */
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2008-12-03 17:29:47 +01:00
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#define IOMMU_PAGE_SHIFT 12
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#define IOMMU_PAGE_SIZE (1 << IOMMU_PAGE_SHIFT)
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#define IOMMU_PAGE_MASK ~(IOMMU_PAGE_SIZE - 1)
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2004-10-01 00:13:50 +02:00
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typedef struct IOMMUState {
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2009-07-16 15:47:55 +02:00
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SysBusDevice busdev;
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2011-11-15 10:56:16 +01:00
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MemoryRegion iomem;
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2005-04-06 22:47:48 +02:00
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uint32_t regs[IOMMU_NREGS];
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2012-10-23 12:30:10 +02:00
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hwaddr iostart;
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2008-01-01 18:04:45 +01:00
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qemu_irq irq;
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2011-08-07 21:09:50 +02:00
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uint32_t version;
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2004-10-01 00:13:50 +02:00
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} IOMMUState;
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2012-10-23 12:30:10 +02:00
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static uint64_t iommu_mem_read(void *opaque, hwaddr addr,
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2011-11-15 10:56:16 +01:00
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unsigned size)
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2004-10-01 00:13:50 +02:00
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{
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IOMMUState *s = opaque;
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2012-10-23 12:30:10 +02:00
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hwaddr saddr;
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2008-01-01 18:04:45 +01:00
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uint32_t ret;
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2004-10-01 00:13:50 +02:00
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2008-12-01 19:59:50 +01:00
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saddr = addr >> 2;
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2004-10-01 00:13:50 +02:00
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switch (saddr) {
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default:
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2008-01-01 18:04:45 +01:00
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ret = s->regs[saddr];
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break;
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case IOMMU_AFAR:
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case IOMMU_AFSR:
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ret = s->regs[saddr];
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qemu_irq_lower(s->irq);
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2007-10-06 13:28:21 +02:00
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break;
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2004-10-01 00:13:50 +02:00
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}
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2010-10-31 10:24:14 +01:00
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trace_sun4m_iommu_mem_readl(saddr, ret);
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2008-01-01 18:04:45 +01:00
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return ret;
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2004-10-01 00:13:50 +02:00
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}
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2012-10-23 12:30:10 +02:00
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static void iommu_mem_write(void *opaque, hwaddr addr,
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2011-11-15 10:56:16 +01:00
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uint64_t val, unsigned size)
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2004-10-01 00:13:50 +02:00
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{
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IOMMUState *s = opaque;
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2012-10-23 12:30:10 +02:00
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hwaddr saddr;
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2004-10-01 00:13:50 +02:00
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2008-12-01 19:59:50 +01:00
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saddr = addr >> 2;
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2010-10-31 10:24:14 +01:00
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trace_sun4m_iommu_mem_writel(saddr, val);
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2004-10-01 00:13:50 +02:00
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switch (saddr) {
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2005-10-30 18:24:19 +01:00
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case IOMMU_CTRL:
|
2007-10-06 13:28:21 +02:00
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switch (val & IOMMU_CTRL_RNGE) {
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case IOMMU_RNGE_16MB:
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s->iostart = 0xffffffffff000000ULL;
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break;
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case IOMMU_RNGE_32MB:
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s->iostart = 0xfffffffffe000000ULL;
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break;
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case IOMMU_RNGE_64MB:
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s->iostart = 0xfffffffffc000000ULL;
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break;
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case IOMMU_RNGE_128MB:
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s->iostart = 0xfffffffff8000000ULL;
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break;
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case IOMMU_RNGE_256MB:
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s->iostart = 0xfffffffff0000000ULL;
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break;
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case IOMMU_RNGE_512MB:
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s->iostart = 0xffffffffe0000000ULL;
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break;
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case IOMMU_RNGE_1GB:
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s->iostart = 0xffffffffc0000000ULL;
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break;
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default:
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case IOMMU_RNGE_2GB:
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s->iostart = 0xffffffff80000000ULL;
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break;
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}
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2010-10-31 10:24:14 +01:00
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trace_sun4m_iommu_mem_writel_ctrl(s->iostart);
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2007-11-17 10:04:09 +01:00
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s->regs[saddr] = ((val & IOMMU_CTRL_MASK) | s->version);
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2007-10-06 13:28:21 +02:00
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break;
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2005-10-30 18:24:19 +01:00
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case IOMMU_BASE:
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2007-10-06 13:28:21 +02:00
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s->regs[saddr] = val & IOMMU_BASE_MASK;
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break;
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2005-10-30 18:24:19 +01:00
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case IOMMU_TLBFLUSH:
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2010-10-31 10:24:14 +01:00
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trace_sun4m_iommu_mem_writel_tlbflush(val);
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2007-10-06 13:28:21 +02:00
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s->regs[saddr] = val & IOMMU_TLBFLUSH_MASK;
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break;
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2005-10-30 18:24:19 +01:00
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case IOMMU_PGFLUSH:
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2010-10-31 10:24:14 +01:00
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trace_sun4m_iommu_mem_writel_pgflush(val);
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2007-10-06 13:28:21 +02:00
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s->regs[saddr] = val & IOMMU_PGFLUSH_MASK;
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break;
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2008-01-01 18:04:45 +01:00
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case IOMMU_AFAR:
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s->regs[saddr] = val;
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qemu_irq_lower(s->irq);
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break;
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2008-12-21 11:46:23 +01:00
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case IOMMU_AER:
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s->regs[saddr] = (val & IOMMU_AER_MASK) | IOMMU_AER_EN_P0_ARB;
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break;
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2007-12-01 15:51:24 +01:00
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case IOMMU_AFSR:
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s->regs[saddr] = (val & IOMMU_AFSR_MASK) | IOMMU_AFSR_RESV;
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2008-01-01 18:04:45 +01:00
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qemu_irq_lower(s->irq);
|
2007-12-01 15:51:24 +01:00
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break;
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2005-10-30 18:24:19 +01:00
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case IOMMU_SBCFG0:
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case IOMMU_SBCFG1:
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case IOMMU_SBCFG2:
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case IOMMU_SBCFG3:
|
2007-10-06 13:28:21 +02:00
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s->regs[saddr] = val & IOMMU_SBCFG_MASK;
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break;
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2005-10-30 18:24:19 +01:00
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case IOMMU_ARBEN:
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// XXX implement SBus probing: fault when reading unmapped
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// addresses, fault cause and address stored to MMU/IOMMU
|
2007-10-06 13:28:21 +02:00
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s->regs[saddr] = (val & IOMMU_ARBEN_MASK) | IOMMU_MID;
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break;
|
2008-01-25 20:52:54 +01:00
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case IOMMU_MASK_ID:
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s->regs[saddr] |= val & IOMMU_MASK_ID_MASK;
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break;
|
2004-10-01 00:13:50 +02:00
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default:
|
2007-10-06 13:28:21 +02:00
|
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s->regs[saddr] = val;
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|
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break;
|
2004-10-01 00:13:50 +02:00
|
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}
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}
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|
2011-11-15 10:56:16 +01:00
|
|
|
static const MemoryRegionOps iommu_mem_ops = {
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.read = iommu_mem_read,
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.write = iommu_mem_write,
|
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.endianness = DEVICE_NATIVE_ENDIAN,
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.valid = {
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.min_access_size = 4,
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.max_access_size = 4,
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},
|
2004-10-01 00:13:50 +02:00
|
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|
};
|
|
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|
2012-10-23 12:30:10 +02:00
|
|
|
static uint32_t iommu_page_get_flags(IOMMUState *s, hwaddr addr)
|
2004-10-01 00:13:50 +02:00
|
|
|
{
|
2007-09-20 18:01:51 +02:00
|
|
|
uint32_t ret;
|
2012-10-23 12:30:10 +02:00
|
|
|
hwaddr iopte;
|
|
|
|
hwaddr pa = addr;
|
2004-10-01 00:13:50 +02:00
|
|
|
|
2007-08-11 09:49:55 +02:00
|
|
|
iopte = s->regs[IOMMU_BASE] << 4;
|
2005-04-06 22:47:48 +02:00
|
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|
addr &= ~s->iostart;
|
2008-12-03 17:29:47 +01:00
|
|
|
iopte += (addr >> (IOMMU_PAGE_SHIFT - 2)) & ~3;
|
2007-09-20 18:01:51 +02:00
|
|
|
cpu_physical_memory_read(iopte, (uint8_t *)&ret, 4);
|
2007-09-22 14:09:09 +02:00
|
|
|
tswap32s(&ret);
|
2010-10-31 10:24:14 +01:00
|
|
|
trace_sun4m_iommu_page_get_flags(pa, iopte, ret);
|
2007-08-11 09:49:55 +02:00
|
|
|
return ret;
|
2006-08-29 06:52:16 +02:00
|
|
|
}
|
|
|
|
|
2012-10-23 12:30:10 +02:00
|
|
|
static hwaddr iommu_translate_pa(hwaddr addr,
|
2007-05-19 14:58:30 +02:00
|
|
|
uint32_t pte)
|
2006-08-29 06:52:16 +02:00
|
|
|
{
|
2012-10-23 12:30:10 +02:00
|
|
|
hwaddr pa;
|
2007-05-19 14:58:30 +02:00
|
|
|
|
2008-12-03 17:29:47 +01:00
|
|
|
pa = ((pte & IOPTE_PAGE) << 4) + (addr & ~IOMMU_PAGE_MASK);
|
2010-10-31 10:24:14 +01:00
|
|
|
trace_sun4m_iommu_translate_pa(addr, pa, pte);
|
2005-04-06 22:47:48 +02:00
|
|
|
return pa;
|
2004-10-01 00:13:50 +02:00
|
|
|
}
|
|
|
|
|
2012-10-23 12:30:10 +02:00
|
|
|
static void iommu_bad_addr(IOMMUState *s, hwaddr addr,
|
2007-12-01 15:51:23 +01:00
|
|
|
int is_write)
|
2007-08-11 09:52:09 +02:00
|
|
|
{
|
2010-10-31 10:24:14 +01:00
|
|
|
trace_sun4m_iommu_bad_addr(addr);
|
2007-12-01 15:51:23 +01:00
|
|
|
s->regs[IOMMU_AFSR] = IOMMU_AFSR_ERR | IOMMU_AFSR_LE | IOMMU_AFSR_RESV |
|
2007-08-11 09:52:09 +02:00
|
|
|
IOMMU_AFSR_FAV;
|
|
|
|
if (!is_write)
|
|
|
|
s->regs[IOMMU_AFSR] |= IOMMU_AFSR_RD;
|
|
|
|
s->regs[IOMMU_AFAR] = addr;
|
2008-01-01 18:04:45 +01:00
|
|
|
qemu_irq_raise(s->irq);
|
2007-08-11 09:52:09 +02:00
|
|
|
}
|
|
|
|
|
2012-10-23 12:30:10 +02:00
|
|
|
void sparc_iommu_memory_rw(void *opaque, hwaddr addr,
|
2006-09-03 18:09:07 +02:00
|
|
|
uint8_t *buf, int len, int is_write)
|
2006-08-29 06:52:16 +02:00
|
|
|
{
|
2007-05-19 14:58:30 +02:00
|
|
|
int l;
|
|
|
|
uint32_t flags;
|
2012-10-23 12:30:10 +02:00
|
|
|
hwaddr page, phys_addr;
|
2006-08-29 06:52:16 +02:00
|
|
|
|
|
|
|
while (len > 0) {
|
2008-12-03 17:29:47 +01:00
|
|
|
page = addr & IOMMU_PAGE_MASK;
|
|
|
|
l = (page + IOMMU_PAGE_SIZE) - addr;
|
2006-08-29 06:52:16 +02:00
|
|
|
if (l > len)
|
|
|
|
l = len;
|
|
|
|
flags = iommu_page_get_flags(opaque, page);
|
2007-08-11 09:52:09 +02:00
|
|
|
if (!(flags & IOPTE_VALID)) {
|
|
|
|
iommu_bad_addr(opaque, page, is_write);
|
2006-08-29 06:52:16 +02:00
|
|
|
return;
|
2007-08-11 09:52:09 +02:00
|
|
|
}
|
2008-05-10 12:12:00 +02:00
|
|
|
phys_addr = iommu_translate_pa(addr, flags);
|
2006-08-29 06:52:16 +02:00
|
|
|
if (is_write) {
|
2007-08-11 09:52:09 +02:00
|
|
|
if (!(flags & IOPTE_WRITE)) {
|
|
|
|
iommu_bad_addr(opaque, page, is_write);
|
2006-08-29 06:52:16 +02:00
|
|
|
return;
|
2007-08-11 09:52:09 +02:00
|
|
|
}
|
2008-07-01 21:28:23 +02:00
|
|
|
cpu_physical_memory_write(phys_addr, buf, l);
|
2006-08-29 06:52:16 +02:00
|
|
|
} else {
|
2008-07-01 21:28:23 +02:00
|
|
|
cpu_physical_memory_read(phys_addr, buf, l);
|
2006-08-29 06:52:16 +02:00
|
|
|
}
|
|
|
|
len -= l;
|
|
|
|
buf += l;
|
|
|
|
addr += l;
|
|
|
|
}
|
|
|
|
}
|
|
|
|
|
2009-08-28 22:46:21 +02:00
|
|
|
static const VMStateDescription vmstate_iommu = {
|
|
|
|
.name ="iommu",
|
|
|
|
.version_id = 2,
|
|
|
|
.minimum_version_id = 2,
|
|
|
|
.minimum_version_id_old = 2,
|
|
|
|
.fields = (VMStateField []) {
|
|
|
|
VMSTATE_UINT32_ARRAY(regs, IOMMUState, IOMMU_NREGS),
|
|
|
|
VMSTATE_UINT64(iostart, IOMMUState),
|
|
|
|
VMSTATE_END_OF_LIST()
|
|
|
|
}
|
|
|
|
};
|
2004-12-20 00:18:01 +01:00
|
|
|
|
2009-10-24 21:39:17 +02:00
|
|
|
static void iommu_reset(DeviceState *d)
|
2004-12-20 00:18:01 +01:00
|
|
|
{
|
2009-10-24 21:39:17 +02:00
|
|
|
IOMMUState *s = container_of(d, IOMMUState, busdev.qdev);
|
2004-12-20 00:18:01 +01:00
|
|
|
|
2005-04-06 22:47:48 +02:00
|
|
|
memset(s->regs, 0, IOMMU_NREGS * 4);
|
2004-12-20 00:18:01 +01:00
|
|
|
s->iostart = 0;
|
2007-11-17 10:04:09 +01:00
|
|
|
s->regs[IOMMU_CTRL] = s->version;
|
|
|
|
s->regs[IOMMU_ARBEN] = IOMMU_MID;
|
2007-12-01 15:51:23 +01:00
|
|
|
s->regs[IOMMU_AFSR] = IOMMU_AFSR_RESV;
|
2008-12-21 11:46:23 +01:00
|
|
|
s->regs[IOMMU_AER] = IOMMU_AER_EN_P0_ARB | IOMMU_AER_EN_P1_ARB;
|
2008-01-25 20:52:54 +01:00
|
|
|
s->regs[IOMMU_MASK_ID] = IOMMU_TS_MASK;
|
2004-12-20 00:18:01 +01:00
|
|
|
}
|
|
|
|
|
2009-08-14 10:36:05 +02:00
|
|
|
static int iommu_init1(SysBusDevice *dev)
|
2009-07-16 15:47:55 +02:00
|
|
|
{
|
|
|
|
IOMMUState *s = FROM_SYSBUS(IOMMUState, dev);
|
2004-10-01 00:13:50 +02:00
|
|
|
|
2009-07-16 15:47:55 +02:00
|
|
|
sysbus_init_irq(dev, &s->irq);
|
2004-10-01 00:13:50 +02:00
|
|
|
|
2011-11-15 10:56:16 +01:00
|
|
|
memory_region_init_io(&s->iomem, &iommu_mem_ops, s, "iommu",
|
|
|
|
IOMMU_NREGS * sizeof(uint32_t));
|
2011-11-27 10:38:10 +01:00
|
|
|
sysbus_init_mmio(dev, &s->iomem);
|
2007-09-17 10:09:54 +02:00
|
|
|
|
2009-08-14 10:36:05 +02:00
|
|
|
return 0;
|
2004-10-01 00:13:50 +02:00
|
|
|
}
|
2009-07-16 15:47:55 +02:00
|
|
|
|
2012-01-24 20:12:29 +01:00
|
|
|
static Property iommu_properties[] = {
|
|
|
|
DEFINE_PROP_HEX32("version", IOMMUState, version, 0),
|
|
|
|
DEFINE_PROP_END_OF_LIST(),
|
|
|
|
};
|
|
|
|
|
|
|
|
static void iommu_class_init(ObjectClass *klass, void *data)
|
|
|
|
{
|
2011-12-08 04:34:16 +01:00
|
|
|
DeviceClass *dc = DEVICE_CLASS(klass);
|
2012-01-24 20:12:29 +01:00
|
|
|
SysBusDeviceClass *k = SYS_BUS_DEVICE_CLASS(klass);
|
|
|
|
|
|
|
|
k->init = iommu_init1;
|
2011-12-08 04:34:16 +01:00
|
|
|
dc->reset = iommu_reset;
|
|
|
|
dc->vmsd = &vmstate_iommu;
|
|
|
|
dc->props = iommu_properties;
|
2012-01-24 20:12:29 +01:00
|
|
|
}
|
|
|
|
|
2011-12-08 04:34:16 +01:00
|
|
|
static TypeInfo iommu_info = {
|
|
|
|
.name = "iommu",
|
|
|
|
.parent = TYPE_SYS_BUS_DEVICE,
|
|
|
|
.instance_size = sizeof(IOMMUState),
|
|
|
|
.class_init = iommu_class_init,
|
2009-07-16 15:47:55 +02:00
|
|
|
};
|
|
|
|
|
2012-02-09 15:20:55 +01:00
|
|
|
static void iommu_register_types(void)
|
2009-07-16 15:47:55 +02:00
|
|
|
{
|
2011-12-08 04:34:16 +01:00
|
|
|
type_register_static(&iommu_info);
|
2009-07-16 15:47:55 +02:00
|
|
|
}
|
|
|
|
|
2012-02-09 15:20:55 +01:00
|
|
|
type_init(iommu_register_types)
|