2012-10-30 15:08:37 +01:00
|
|
|
/*
|
|
|
|
* QEMU USB EHCI Emulation
|
|
|
|
*
|
|
|
|
* This library is free software; you can redistribute it and/or
|
|
|
|
* modify it under the terms of the GNU Lesser General Public
|
|
|
|
* License as published by the Free Software Foundation; either
|
2019-01-23 15:40:54 +01:00
|
|
|
* version 2.1 of the License, or (at your option) any later version.
|
2012-10-30 15:08:37 +01:00
|
|
|
*
|
|
|
|
* This library is distributed in the hope that it will be useful,
|
|
|
|
* but WITHOUT ANY WARRANTY; without even the implied warranty of
|
|
|
|
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
|
|
|
|
* Lesser General Public License for more details.
|
|
|
|
*
|
2019-01-23 15:40:54 +01:00
|
|
|
* You should have received a copy of the GNU Lesser General Public License
|
2012-10-30 15:08:37 +01:00
|
|
|
* along with this program; if not, see <http://www.gnu.org/licenses/>.
|
|
|
|
*/
|
|
|
|
|
2016-01-26 19:17:12 +01:00
|
|
|
#include "qemu/osdep.h"
|
2019-08-12 07:23:51 +02:00
|
|
|
#include "hw/qdev-properties.h"
|
2012-10-30 15:08:37 +01:00
|
|
|
#include "hw/usb/hcd-ehci.h"
|
2019-08-12 07:23:45 +02:00
|
|
|
#include "migration/vmstate.h"
|
2019-05-23 16:35:07 +02:00
|
|
|
#include "qemu/module.h"
|
2012-10-30 15:08:37 +01:00
|
|
|
|
|
|
|
static const VMStateDescription vmstate_ehci_sysbus = {
|
|
|
|
.name = "ehci-sysbus",
|
|
|
|
.version_id = 2,
|
|
|
|
.minimum_version_id = 1,
|
2023-12-21 04:16:39 +01:00
|
|
|
.fields = (const VMStateField[]) {
|
2012-10-30 15:08:37 +01:00
|
|
|
VMSTATE_STRUCT(ehci, EHCISysBusState, 2, vmstate_ehci, EHCIState),
|
|
|
|
VMSTATE_END_OF_LIST()
|
|
|
|
}
|
|
|
|
};
|
|
|
|
|
|
|
|
static Property ehci_sysbus_properties[] = {
|
|
|
|
DEFINE_PROP_UINT32("maxframes", EHCISysBusState, ehci.maxframes, 128),
|
2020-02-17 21:48:11 +01:00
|
|
|
DEFINE_PROP_BOOL("companion-enable", EHCISysBusState, ehci.companion_enable,
|
|
|
|
false),
|
2012-10-30 15:08:37 +01:00
|
|
|
DEFINE_PROP_END_OF_LIST(),
|
|
|
|
};
|
|
|
|
|
2013-06-06 15:41:09 +02:00
|
|
|
static void usb_ehci_sysbus_realize(DeviceState *dev, Error **errp)
|
2012-10-30 15:08:37 +01:00
|
|
|
{
|
2013-06-06 15:41:09 +02:00
|
|
|
SysBusDevice *d = SYS_BUS_DEVICE(dev);
|
2012-12-16 04:49:43 +01:00
|
|
|
EHCISysBusState *i = SYS_BUS_EHCI(dev);
|
2013-06-06 15:41:10 +02:00
|
|
|
EHCIState *s = &i->ehci;
|
|
|
|
|
|
|
|
usb_ehci_realize(s, dev, errp);
|
|
|
|
sysbus_init_irq(d, &s->irq);
|
|
|
|
}
|
|
|
|
|
2015-03-18 10:33:47 +01:00
|
|
|
static void usb_ehci_sysbus_reset(DeviceState *dev)
|
|
|
|
{
|
|
|
|
SysBusDevice *d = SYS_BUS_DEVICE(dev);
|
|
|
|
EHCISysBusState *i = SYS_BUS_EHCI(d);
|
|
|
|
EHCIState *s = &i->ehci;
|
|
|
|
|
|
|
|
ehci_reset(s);
|
|
|
|
}
|
|
|
|
|
2013-06-06 15:41:10 +02:00
|
|
|
static void ehci_sysbus_init(Object *obj)
|
|
|
|
{
|
|
|
|
SysBusDevice *d = SYS_BUS_DEVICE(obj);
|
|
|
|
EHCISysBusState *i = SYS_BUS_EHCI(obj);
|
|
|
|
SysBusEHCIClass *sec = SYS_BUS_EHCI_GET_CLASS(obj);
|
2012-10-30 15:08:37 +01:00
|
|
|
EHCIState *s = &i->ehci;
|
|
|
|
|
2012-12-16 04:49:44 +01:00
|
|
|
s->capsbase = sec->capsbase;
|
|
|
|
s->opregbase = sec->opregbase;
|
2013-06-06 15:41:12 +02:00
|
|
|
s->portscbase = sec->portscbase;
|
|
|
|
s->portnr = sec->portnr;
|
2013-04-10 18:15:49 +02:00
|
|
|
s->as = &address_space_memory;
|
2012-10-30 15:08:37 +01:00
|
|
|
|
2013-06-06 15:41:10 +02:00
|
|
|
usb_ehci_init(s, DEVICE(obj));
|
2013-06-06 15:41:09 +02:00
|
|
|
sysbus_init_mmio(d, &s->mem);
|
2012-10-30 15:08:37 +01:00
|
|
|
}
|
|
|
|
|
2021-03-23 19:37:01 +01:00
|
|
|
static void ehci_sysbus_finalize(Object *obj)
|
|
|
|
{
|
|
|
|
EHCISysBusState *i = SYS_BUS_EHCI(obj);
|
|
|
|
EHCIState *s = &i->ehci;
|
|
|
|
|
|
|
|
usb_ehci_finalize(s);
|
|
|
|
}
|
|
|
|
|
2012-10-30 15:08:37 +01:00
|
|
|
static void ehci_sysbus_class_init(ObjectClass *klass, void *data)
|
|
|
|
{
|
|
|
|
DeviceClass *dc = DEVICE_CLASS(klass);
|
2013-06-06 15:41:12 +02:00
|
|
|
SysBusEHCIClass *sec = SYS_BUS_EHCI_CLASS(klass);
|
|
|
|
|
|
|
|
sec->portscbase = 0x44;
|
|
|
|
sec->portnr = NB_PORTS;
|
2012-10-30 15:08:37 +01:00
|
|
|
|
2013-06-06 15:41:09 +02:00
|
|
|
dc->realize = usb_ehci_sysbus_realize;
|
2012-10-30 15:08:37 +01:00
|
|
|
dc->vmsd = &vmstate_ehci_sysbus;
|
2020-01-10 16:30:32 +01:00
|
|
|
device_class_set_props(dc, ehci_sysbus_properties);
|
2015-03-18 10:33:47 +01:00
|
|
|
dc->reset = usb_ehci_sysbus_reset;
|
2013-07-29 16:17:45 +02:00
|
|
|
set_bit(DEVICE_CATEGORY_USB, dc->categories);
|
2012-10-30 15:08:37 +01:00
|
|
|
}
|
|
|
|
|
2012-12-16 04:49:43 +01:00
|
|
|
static const TypeInfo ehci_type_info = {
|
|
|
|
.name = TYPE_SYS_BUS_EHCI,
|
2012-10-30 15:08:37 +01:00
|
|
|
.parent = TYPE_SYS_BUS_DEVICE,
|
|
|
|
.instance_size = sizeof(EHCISysBusState),
|
2013-06-06 15:41:10 +02:00
|
|
|
.instance_init = ehci_sysbus_init,
|
2021-03-23 19:37:01 +01:00
|
|
|
.instance_finalize = ehci_sysbus_finalize,
|
2012-12-16 04:49:43 +01:00
|
|
|
.abstract = true,
|
2012-10-30 15:08:37 +01:00
|
|
|
.class_init = ehci_sysbus_class_init,
|
2012-12-16 04:49:44 +01:00
|
|
|
.class_size = sizeof(SysBusEHCIClass),
|
2012-10-30 15:08:37 +01:00
|
|
|
};
|
|
|
|
|
2018-12-29 11:00:57 +01:00
|
|
|
static void ehci_platform_class_init(ObjectClass *oc, void *data)
|
|
|
|
{
|
|
|
|
SysBusEHCIClass *sec = SYS_BUS_EHCI_CLASS(oc);
|
|
|
|
DeviceClass *dc = DEVICE_CLASS(oc);
|
|
|
|
|
|
|
|
sec->capsbase = 0x0;
|
|
|
|
sec->opregbase = 0x20;
|
|
|
|
set_bit(DEVICE_CATEGORY_USB, dc->categories);
|
|
|
|
}
|
|
|
|
|
|
|
|
static const TypeInfo ehci_platform_type_info = {
|
|
|
|
.name = TYPE_PLATFORM_EHCI,
|
|
|
|
.parent = TYPE_SYS_BUS_EHCI,
|
|
|
|
.class_init = ehci_platform_class_init,
|
|
|
|
};
|
|
|
|
|
2012-12-16 04:49:45 +01:00
|
|
|
static void ehci_exynos4210_class_init(ObjectClass *oc, void *data)
|
|
|
|
{
|
|
|
|
SysBusEHCIClass *sec = SYS_BUS_EHCI_CLASS(oc);
|
2013-07-29 16:17:45 +02:00
|
|
|
DeviceClass *dc = DEVICE_CLASS(oc);
|
2012-12-16 04:49:45 +01:00
|
|
|
|
|
|
|
sec->capsbase = 0x0;
|
|
|
|
sec->opregbase = 0x10;
|
2013-07-29 16:17:45 +02:00
|
|
|
set_bit(DEVICE_CATEGORY_USB, dc->categories);
|
2012-12-16 04:49:45 +01:00
|
|
|
}
|
|
|
|
|
|
|
|
static const TypeInfo ehci_exynos4210_type_info = {
|
|
|
|
.name = TYPE_EXYNOS4210_EHCI,
|
|
|
|
.parent = TYPE_SYS_BUS_EHCI,
|
|
|
|
.class_init = ehci_exynos4210_class_init,
|
|
|
|
};
|
|
|
|
|
2020-03-11 23:18:40 +01:00
|
|
|
static void ehci_aw_h3_class_init(ObjectClass *oc, void *data)
|
|
|
|
{
|
|
|
|
SysBusEHCIClass *sec = SYS_BUS_EHCI_CLASS(oc);
|
|
|
|
DeviceClass *dc = DEVICE_CLASS(oc);
|
|
|
|
|
|
|
|
sec->capsbase = 0x0;
|
|
|
|
sec->opregbase = 0x10;
|
|
|
|
set_bit(DEVICE_CATEGORY_USB, dc->categories);
|
|
|
|
}
|
|
|
|
|
|
|
|
static const TypeInfo ehci_aw_h3_type_info = {
|
|
|
|
.name = TYPE_AW_H3_EHCI,
|
|
|
|
.parent = TYPE_SYS_BUS_EHCI,
|
|
|
|
.class_init = ehci_aw_h3_class_init,
|
|
|
|
};
|
|
|
|
|
hw/arm/npcm7xx: Add EHCI and OHCI controllers
The NPCM730 and NPCM750 chips have a single USB host port shared between
a USB 2.0 EHCI host controller and a USB 1.1 OHCI host controller. This
adds support for both of them.
Testing notes:
* With -device usb-kbd, qemu will automatically insert a full-speed
hub, and the keyboard becomes controlled by the OHCI controller.
* With -device usb-kbd,bus=usb-bus.0,port=1, the keyboard is directly
attached to the port without any hubs, and the device becomes
controlled by the EHCI controller since it's high speed capable.
* With -device usb-kbd,bus=usb-bus.0,port=1,usb_version=1, the
keyboard is directly attached to the port, but it only advertises
itself as full-speed capable, so it becomes controlled by the OHCI
controller.
In all cases, the keyboard device enumerates correctly.
Reviewed-by: Tyrone Ting <kfting@nuvoton.com>
Reviewed-by: Gerd Hoffmann <kraxel@redhat.com>
Signed-off-by: Havard Skinnemoen <hskinnemoen@google.com>
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2020-10-23 23:06:36 +02:00
|
|
|
static void ehci_npcm7xx_class_init(ObjectClass *oc, void *data)
|
|
|
|
{
|
|
|
|
SysBusEHCIClass *sec = SYS_BUS_EHCI_CLASS(oc);
|
|
|
|
DeviceClass *dc = DEVICE_CLASS(oc);
|
|
|
|
|
|
|
|
sec->capsbase = 0x0;
|
|
|
|
sec->opregbase = 0x10;
|
|
|
|
sec->portscbase = 0x44;
|
|
|
|
sec->portnr = 1;
|
|
|
|
set_bit(DEVICE_CATEGORY_USB, dc->categories);
|
|
|
|
}
|
|
|
|
|
|
|
|
static const TypeInfo ehci_npcm7xx_type_info = {
|
|
|
|
.name = TYPE_NPCM7XX_EHCI,
|
|
|
|
.parent = TYPE_SYS_BUS_EHCI,
|
|
|
|
.class_init = ehci_npcm7xx_class_init,
|
|
|
|
};
|
|
|
|
|
2013-06-06 15:41:11 +02:00
|
|
|
static void ehci_tegra2_class_init(ObjectClass *oc, void *data)
|
|
|
|
{
|
|
|
|
SysBusEHCIClass *sec = SYS_BUS_EHCI_CLASS(oc);
|
2013-07-29 16:17:45 +02:00
|
|
|
DeviceClass *dc = DEVICE_CLASS(oc);
|
2013-06-06 15:41:11 +02:00
|
|
|
|
|
|
|
sec->capsbase = 0x100;
|
|
|
|
sec->opregbase = 0x140;
|
2013-07-29 16:17:45 +02:00
|
|
|
set_bit(DEVICE_CATEGORY_USB, dc->categories);
|
2013-06-06 15:41:11 +02:00
|
|
|
}
|
|
|
|
|
|
|
|
static const TypeInfo ehci_tegra2_type_info = {
|
|
|
|
.name = TYPE_TEGRA2_EHCI,
|
|
|
|
.parent = TYPE_SYS_BUS_EHCI,
|
|
|
|
.class_init = ehci_tegra2_class_init,
|
|
|
|
};
|
|
|
|
|
2017-09-16 16:02:41 +02:00
|
|
|
static void ehci_ppc4xx_init(Object *o)
|
|
|
|
{
|
|
|
|
EHCISysBusState *s = SYS_BUS_EHCI(o);
|
|
|
|
|
|
|
|
s->ehci.companion_enable = true;
|
|
|
|
}
|
|
|
|
|
|
|
|
static void ehci_ppc4xx_class_init(ObjectClass *oc, void *data)
|
|
|
|
{
|
|
|
|
SysBusEHCIClass *sec = SYS_BUS_EHCI_CLASS(oc);
|
|
|
|
DeviceClass *dc = DEVICE_CLASS(oc);
|
|
|
|
|
|
|
|
sec->capsbase = 0x0;
|
|
|
|
sec->opregbase = 0x10;
|
|
|
|
set_bit(DEVICE_CATEGORY_USB, dc->categories);
|
|
|
|
}
|
|
|
|
|
|
|
|
static const TypeInfo ehci_ppc4xx_type_info = {
|
|
|
|
.name = TYPE_PPC4xx_EHCI,
|
|
|
|
.parent = TYPE_SYS_BUS_EHCI,
|
|
|
|
.class_init = ehci_ppc4xx_class_init,
|
|
|
|
.instance_init = ehci_ppc4xx_init,
|
|
|
|
};
|
|
|
|
|
2013-06-06 15:41:13 +02:00
|
|
|
/*
|
|
|
|
* Faraday FUSBH200 USB 2.0 EHCI
|
|
|
|
*/
|
|
|
|
|
|
|
|
/**
|
|
|
|
* FUSBH200EHCIRegs:
|
|
|
|
* @FUSBH200_REG_EOF_ASTR: EOF/Async. Sleep Timer Register
|
|
|
|
* @FUSBH200_REG_BMCSR: Bus Monitor Control/Status Register
|
|
|
|
*/
|
|
|
|
enum FUSBH200EHCIRegs {
|
|
|
|
FUSBH200_REG_EOF_ASTR = 0x34,
|
|
|
|
FUSBH200_REG_BMCSR = 0x40,
|
|
|
|
};
|
|
|
|
|
|
|
|
static uint64_t fusbh200_ehci_read(void *opaque, hwaddr addr, unsigned size)
|
|
|
|
{
|
|
|
|
EHCIState *s = opaque;
|
|
|
|
hwaddr off = s->opregbase + s->portscbase + 4 * s->portnr + addr;
|
|
|
|
|
|
|
|
switch (off) {
|
|
|
|
case FUSBH200_REG_EOF_ASTR:
|
|
|
|
return 0x00000041;
|
|
|
|
case FUSBH200_REG_BMCSR:
|
|
|
|
/* High-Speed, VBUS valid, interrupt level-high active */
|
|
|
|
return (2 << 9) | (1 << 8) | (1 << 3);
|
|
|
|
}
|
|
|
|
|
|
|
|
return 0;
|
|
|
|
}
|
|
|
|
|
|
|
|
static void fusbh200_ehci_write(void *opaque, hwaddr addr, uint64_t val,
|
|
|
|
unsigned size)
|
|
|
|
{
|
|
|
|
}
|
|
|
|
|
|
|
|
static const MemoryRegionOps fusbh200_ehci_mmio_ops = {
|
|
|
|
.read = fusbh200_ehci_read,
|
|
|
|
.write = fusbh200_ehci_write,
|
|
|
|
.valid.min_access_size = 4,
|
|
|
|
.valid.max_access_size = 4,
|
|
|
|
.endianness = DEVICE_LITTLE_ENDIAN,
|
|
|
|
};
|
|
|
|
|
|
|
|
static void fusbh200_ehci_init(Object *obj)
|
|
|
|
{
|
|
|
|
EHCISysBusState *i = SYS_BUS_EHCI(obj);
|
|
|
|
FUSBH200EHCIState *f = FUSBH200_EHCI(obj);
|
|
|
|
EHCIState *s = &i->ehci;
|
|
|
|
|
2013-06-07 03:25:08 +02:00
|
|
|
memory_region_init_io(&f->mem_vendor, OBJECT(f), &fusbh200_ehci_mmio_ops, s,
|
2013-06-06 15:41:13 +02:00
|
|
|
"fusbh200", 0x4c);
|
|
|
|
memory_region_add_subregion(&s->mem,
|
|
|
|
s->opregbase + s->portscbase + 4 * s->portnr,
|
|
|
|
&f->mem_vendor);
|
|
|
|
}
|
|
|
|
|
|
|
|
static void fusbh200_ehci_class_init(ObjectClass *oc, void *data)
|
|
|
|
{
|
|
|
|
SysBusEHCIClass *sec = SYS_BUS_EHCI_CLASS(oc);
|
2013-07-29 16:17:45 +02:00
|
|
|
DeviceClass *dc = DEVICE_CLASS(oc);
|
2013-06-06 15:41:13 +02:00
|
|
|
|
|
|
|
sec->capsbase = 0x0;
|
|
|
|
sec->opregbase = 0x10;
|
|
|
|
sec->portscbase = 0x20;
|
|
|
|
sec->portnr = 1;
|
2013-07-29 16:17:45 +02:00
|
|
|
set_bit(DEVICE_CATEGORY_USB, dc->categories);
|
2013-06-06 15:41:13 +02:00
|
|
|
}
|
|
|
|
|
|
|
|
static const TypeInfo ehci_fusbh200_type_info = {
|
|
|
|
.name = TYPE_FUSBH200_EHCI,
|
|
|
|
.parent = TYPE_SYS_BUS_EHCI,
|
|
|
|
.instance_size = sizeof(FUSBH200EHCIState),
|
|
|
|
.instance_init = fusbh200_ehci_init,
|
|
|
|
.class_init = fusbh200_ehci_class_init,
|
|
|
|
};
|
|
|
|
|
2012-10-30 15:08:37 +01:00
|
|
|
static void ehci_sysbus_register_types(void)
|
|
|
|
{
|
2012-12-16 04:49:43 +01:00
|
|
|
type_register_static(&ehci_type_info);
|
2018-12-29 11:00:57 +01:00
|
|
|
type_register_static(&ehci_platform_type_info);
|
2012-12-16 04:49:45 +01:00
|
|
|
type_register_static(&ehci_exynos4210_type_info);
|
2020-03-11 23:18:40 +01:00
|
|
|
type_register_static(&ehci_aw_h3_type_info);
|
hw/arm/npcm7xx: Add EHCI and OHCI controllers
The NPCM730 and NPCM750 chips have a single USB host port shared between
a USB 2.0 EHCI host controller and a USB 1.1 OHCI host controller. This
adds support for both of them.
Testing notes:
* With -device usb-kbd, qemu will automatically insert a full-speed
hub, and the keyboard becomes controlled by the OHCI controller.
* With -device usb-kbd,bus=usb-bus.0,port=1, the keyboard is directly
attached to the port without any hubs, and the device becomes
controlled by the EHCI controller since it's high speed capable.
* With -device usb-kbd,bus=usb-bus.0,port=1,usb_version=1, the
keyboard is directly attached to the port, but it only advertises
itself as full-speed capable, so it becomes controlled by the OHCI
controller.
In all cases, the keyboard device enumerates correctly.
Reviewed-by: Tyrone Ting <kfting@nuvoton.com>
Reviewed-by: Gerd Hoffmann <kraxel@redhat.com>
Signed-off-by: Havard Skinnemoen <hskinnemoen@google.com>
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2020-10-23 23:06:36 +02:00
|
|
|
type_register_static(&ehci_npcm7xx_type_info);
|
2013-06-06 15:41:11 +02:00
|
|
|
type_register_static(&ehci_tegra2_type_info);
|
2017-09-16 16:02:41 +02:00
|
|
|
type_register_static(&ehci_ppc4xx_type_info);
|
2013-06-06 15:41:13 +02:00
|
|
|
type_register_static(&ehci_fusbh200_type_info);
|
2012-10-30 15:08:37 +01:00
|
|
|
}
|
|
|
|
|
|
|
|
type_init(ehci_sysbus_register_types)
|