2018-02-09 19:51:39 +01:00
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/*
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* QEMU MOS6522 VIA emulation
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*
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* Copyright (c) 2004-2007 Fabrice Bellard
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* Copyright (c) 2007 Jocelyn Mayer
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* Copyright (c) 2018 Mark Cave-Ayland
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*
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* Permission is hereby granted, free of charge, to any person obtaining a copy
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* of this software and associated documentation files (the "Software"), to deal
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* in the Software without restriction, including without limitation the rights
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* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
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* copies of the Software, and to permit persons to whom the Software is
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* furnished to do so, subject to the following conditions:
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*
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* The above copyright notice and this permission notice shall be included in
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* all copies or substantial portions of the Software.
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*
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* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
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* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
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* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
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* THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
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* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
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* OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
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* THE SOFTWARE.
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*/
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2019-05-23 16:35:07 +02:00
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2018-02-09 19:51:39 +01:00
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#include "qemu/osdep.h"
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#include "hw/input/adb.h"
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2019-08-12 07:23:42 +02:00
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#include "hw/irq.h"
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2018-02-09 19:51:39 +01:00
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#include "hw/misc/mos6522.h"
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2019-08-12 07:23:51 +02:00
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#include "hw/qdev-properties.h"
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2019-08-12 07:23:45 +02:00
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#include "migration/vmstate.h"
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2018-02-09 19:51:39 +01:00
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#include "qemu/timer.h"
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#include "qemu/cutils.h"
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#include "qemu/log.h"
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2019-05-23 16:35:07 +02:00
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#include "qemu/module.h"
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2018-02-09 19:51:39 +01:00
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#include "trace.h"
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/* XXX: implement all timer modes */
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2019-11-02 16:49:19 +01:00
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static void mos6522_timer1_update(MOS6522State *s, MOS6522Timer *ti,
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int64_t current_time);
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static void mos6522_timer2_update(MOS6522State *s, MOS6522Timer *ti,
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int64_t current_time);
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2018-02-09 19:51:39 +01:00
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static void mos6522_update_irq(MOS6522State *s)
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{
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2018-06-13 10:30:14 +02:00
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if (s->ifr & s->ier) {
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2018-02-09 19:51:39 +01:00
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qemu_irq_raise(s->irq);
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} else {
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qemu_irq_lower(s->irq);
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}
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}
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static uint64_t get_counter_value(MOS6522State *s, MOS6522Timer *ti)
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{
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MOS6522DeviceClass *mdc = MOS6522_DEVICE_GET_CLASS(s);
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if (ti->index == 0) {
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return mdc->get_timer1_counter_value(s, ti);
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} else {
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return mdc->get_timer2_counter_value(s, ti);
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}
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}
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static uint64_t get_load_time(MOS6522State *s, MOS6522Timer *ti)
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{
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MOS6522DeviceClass *mdc = MOS6522_DEVICE_GET_CLASS(s);
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if (ti->index == 0) {
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return mdc->get_timer1_load_time(s, ti);
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} else {
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return mdc->get_timer2_load_time(s, ti);
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}
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}
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static unsigned int get_counter(MOS6522State *s, MOS6522Timer *ti)
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{
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int64_t d;
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unsigned int counter;
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d = get_counter_value(s, ti);
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if (ti->index == 0) {
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/* the timer goes down from latch to -1 (period of latch + 2) */
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if (d <= (ti->counter_value + 1)) {
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counter = (ti->counter_value - d) & 0xffff;
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} else {
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counter = (d - (ti->counter_value + 1)) % (ti->latch + 2);
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counter = (ti->latch - counter) & 0xffff;
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}
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} else {
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counter = (ti->counter_value - d) & 0xffff;
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}
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return counter;
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}
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static void set_counter(MOS6522State *s, MOS6522Timer *ti, unsigned int val)
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{
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trace_mos6522_set_counter(1 + ti->index, val);
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ti->load_time = get_load_time(s, ti);
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ti->counter_value = val;
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2019-11-02 16:49:19 +01:00
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if (ti->index == 0) {
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mos6522_timer1_update(s, ti, ti->load_time);
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} else {
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mos6522_timer2_update(s, ti, ti->load_time);
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}
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2018-02-09 19:51:39 +01:00
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}
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static int64_t get_next_irq_time(MOS6522State *s, MOS6522Timer *ti,
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int64_t current_time)
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{
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int64_t d, next_time;
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unsigned int counter;
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2019-11-25 15:14:14 +01:00
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if (ti->frequency == 0) {
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return INT64_MAX;
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}
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2018-02-09 19:51:39 +01:00
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/* current counter value */
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d = muldiv64(qemu_clock_get_ns(QEMU_CLOCK_VIRTUAL) - ti->load_time,
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ti->frequency, NANOSECONDS_PER_SECOND);
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/* the timer goes down from latch to -1 (period of latch + 2) */
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if (d <= (ti->counter_value + 1)) {
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counter = (ti->counter_value - d) & 0xffff;
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} else {
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counter = (d - (ti->counter_value + 1)) % (ti->latch + 2);
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counter = (ti->latch - counter) & 0xffff;
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}
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/* Note: we consider the irq is raised on 0 */
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if (counter == 0xffff) {
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next_time = d + ti->latch + 1;
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} else if (counter == 0) {
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next_time = d + ti->latch + 2;
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} else {
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next_time = d + counter;
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}
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trace_mos6522_get_next_irq_time(ti->latch, d, next_time - d);
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next_time = muldiv64(next_time, NANOSECONDS_PER_SECOND, ti->frequency) +
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ti->load_time;
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2019-11-02 16:49:19 +01:00
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2018-02-09 19:51:39 +01:00
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if (next_time <= current_time) {
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next_time = current_time + 1;
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}
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return next_time;
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}
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2019-11-02 16:49:19 +01:00
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static void mos6522_timer1_update(MOS6522State *s, MOS6522Timer *ti,
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int64_t current_time)
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{
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if (!ti->timer) {
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return;
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}
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2019-11-25 15:14:14 +01:00
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ti->next_irq_time = get_next_irq_time(s, ti, current_time);
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2019-11-02 16:49:19 +01:00
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if ((s->ier & T1_INT) == 0 || (s->acr & T1MODE) != T1MODE_CONT) {
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timer_del(ti->timer);
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} else {
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timer_mod(ti->timer, ti->next_irq_time);
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}
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}
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static void mos6522_timer2_update(MOS6522State *s, MOS6522Timer *ti,
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2018-02-09 19:51:39 +01:00
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int64_t current_time)
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{
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if (!ti->timer) {
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return;
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}
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2019-11-25 15:14:14 +01:00
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ti->next_irq_time = get_next_irq_time(s, ti, current_time);
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2019-11-02 16:49:19 +01:00
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if ((s->ier & T2_INT) == 0) {
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2018-02-09 19:51:39 +01:00
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timer_del(ti->timer);
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} else {
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timer_mod(ti->timer, ti->next_irq_time);
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}
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}
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static void mos6522_timer1(void *opaque)
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{
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MOS6522State *s = opaque;
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MOS6522Timer *ti = &s->timers[0];
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2019-11-02 16:49:19 +01:00
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mos6522_timer1_update(s, ti, ti->next_irq_time);
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2018-02-09 19:51:39 +01:00
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s->ifr |= T1_INT;
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mos6522_update_irq(s);
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}
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static void mos6522_timer2(void *opaque)
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{
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MOS6522State *s = opaque;
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MOS6522Timer *ti = &s->timers[1];
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2019-11-02 16:49:19 +01:00
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mos6522_timer2_update(s, ti, ti->next_irq_time);
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2018-02-09 19:51:39 +01:00
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s->ifr |= T2_INT;
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mos6522_update_irq(s);
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}
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static void mos6522_set_sr_int(MOS6522State *s)
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{
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trace_mos6522_set_sr_int();
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s->ifr |= SR_INT;
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mos6522_update_irq(s);
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}
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static uint64_t mos6522_get_counter_value(MOS6522State *s, MOS6522Timer *ti)
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{
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2018-03-23 15:32:02 +01:00
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return muldiv64(qemu_clock_get_ns(QEMU_CLOCK_VIRTUAL) - ti->load_time,
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ti->frequency, NANOSECONDS_PER_SECOND);
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2018-02-09 19:51:39 +01:00
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}
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static uint64_t mos6522_get_load_time(MOS6522State *s, MOS6522Timer *ti)
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{
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uint64_t load_time = qemu_clock_get_ns(QEMU_CLOCK_VIRTUAL);
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return load_time;
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}
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static void mos6522_portA_write(MOS6522State *s)
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{
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2018-06-06 16:59:21 +02:00
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qemu_log_mask(LOG_UNIMP, "portA_write unimplemented\n");
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2018-02-09 19:51:39 +01:00
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}
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static void mos6522_portB_write(MOS6522State *s)
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{
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2018-06-06 16:59:21 +02:00
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qemu_log_mask(LOG_UNIMP, "portB_write unimplemented\n");
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2018-02-09 19:51:39 +01:00
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}
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uint64_t mos6522_read(void *opaque, hwaddr addr, unsigned size)
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{
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MOS6522State *s = opaque;
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uint32_t val;
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2019-11-02 16:49:19 +01:00
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int64_t now = qemu_clock_get_ns(QEMU_CLOCK_VIRTUAL);
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2018-02-09 19:51:39 +01:00
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2019-11-02 16:49:19 +01:00
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if (now >= s->timers[0].next_irq_time) {
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mos6522_timer1_update(s, &s->timers[0], now);
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s->ifr |= T1_INT;
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}
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if (now >= s->timers[1].next_irq_time) {
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mos6522_timer2_update(s, &s->timers[1], now);
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s->ifr |= T2_INT;
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}
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2018-02-09 19:51:39 +01:00
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switch (addr) {
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case VIA_REG_B:
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val = s->b;
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break;
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case VIA_REG_A:
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2019-12-20 22:40:54 +01:00
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qemu_log_mask(LOG_UNIMP, "Read access to register A with handshake");
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/* fall through */
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case VIA_REG_ANH:
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2018-02-09 19:51:39 +01:00
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val = s->a;
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break;
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case VIA_REG_DIRB:
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val = s->dirb;
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break;
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case VIA_REG_DIRA:
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val = s->dira;
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break;
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case VIA_REG_T1CL:
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val = get_counter(s, &s->timers[0]) & 0xff;
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s->ifr &= ~T1_INT;
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mos6522_update_irq(s);
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break;
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case VIA_REG_T1CH:
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val = get_counter(s, &s->timers[0]) >> 8;
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mos6522_update_irq(s);
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break;
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case VIA_REG_T1LL:
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val = s->timers[0].latch & 0xff;
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break;
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case VIA_REG_T1LH:
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/* XXX: check this */
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val = (s->timers[0].latch >> 8) & 0xff;
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break;
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case VIA_REG_T2CL:
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val = get_counter(s, &s->timers[1]) & 0xff;
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s->ifr &= ~T2_INT;
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mos6522_update_irq(s);
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break;
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case VIA_REG_T2CH:
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val = get_counter(s, &s->timers[1]) >> 8;
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break;
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case VIA_REG_SR:
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val = s->sr;
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2018-06-13 10:30:13 +02:00
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s->ifr &= ~SR_INT;
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2018-02-09 19:51:39 +01:00
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mos6522_update_irq(s);
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break;
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case VIA_REG_ACR:
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val = s->acr;
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break;
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case VIA_REG_PCR:
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val = s->pcr;
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break;
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case VIA_REG_IFR:
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val = s->ifr;
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if (s->ifr & s->ier) {
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val |= 0x80;
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}
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break;
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case VIA_REG_IER:
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val = s->ier | 0x80;
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break;
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default:
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2019-12-20 22:40:54 +01:00
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g_assert_not_reached();
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2018-02-09 19:51:39 +01:00
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}
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if (addr != VIA_REG_IFR || val != 0) {
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trace_mos6522_read(addr, val);
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}
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return val;
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}
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void mos6522_write(void *opaque, hwaddr addr, uint64_t val, unsigned size)
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{
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MOS6522State *s = opaque;
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MOS6522DeviceClass *mdc = MOS6522_DEVICE_GET_CLASS(s);
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trace_mos6522_write(addr, val);
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switch (addr) {
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case VIA_REG_B:
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s->b = (s->b & ~s->dirb) | (val & s->dirb);
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mdc->portB_write(s);
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break;
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case VIA_REG_A:
|
2019-12-20 22:40:54 +01:00
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qemu_log_mask(LOG_UNIMP, "Write access to register A with handshake");
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/* fall through */
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case VIA_REG_ANH:
|
2018-02-09 19:51:39 +01:00
|
|
|
s->a = (s->a & ~s->dira) | (val & s->dira);
|
|
|
|
mdc->portA_write(s);
|
|
|
|
break;
|
|
|
|
case VIA_REG_DIRB:
|
|
|
|
s->dirb = val;
|
|
|
|
break;
|
|
|
|
case VIA_REG_DIRA:
|
|
|
|
s->dira = val;
|
|
|
|
break;
|
|
|
|
case VIA_REG_T1CL:
|
|
|
|
s->timers[0].latch = (s->timers[0].latch & 0xff00) | val;
|
2019-11-02 16:49:19 +01:00
|
|
|
mos6522_timer1_update(s, &s->timers[0],
|
|
|
|
qemu_clock_get_ns(QEMU_CLOCK_VIRTUAL));
|
2018-02-09 19:51:39 +01:00
|
|
|
break;
|
|
|
|
case VIA_REG_T1CH:
|
|
|
|
s->timers[0].latch = (s->timers[0].latch & 0xff) | (val << 8);
|
|
|
|
s->ifr &= ~T1_INT;
|
|
|
|
set_counter(s, &s->timers[0], s->timers[0].latch);
|
|
|
|
break;
|
|
|
|
case VIA_REG_T1LL:
|
|
|
|
s->timers[0].latch = (s->timers[0].latch & 0xff00) | val;
|
2019-11-02 16:49:19 +01:00
|
|
|
mos6522_timer1_update(s, &s->timers[0],
|
|
|
|
qemu_clock_get_ns(QEMU_CLOCK_VIRTUAL));
|
2018-02-09 19:51:39 +01:00
|
|
|
break;
|
|
|
|
case VIA_REG_T1LH:
|
|
|
|
s->timers[0].latch = (s->timers[0].latch & 0xff) | (val << 8);
|
|
|
|
s->ifr &= ~T1_INT;
|
2019-11-02 16:49:19 +01:00
|
|
|
mos6522_timer1_update(s, &s->timers[0],
|
|
|
|
qemu_clock_get_ns(QEMU_CLOCK_VIRTUAL));
|
2018-02-09 19:51:39 +01:00
|
|
|
break;
|
|
|
|
case VIA_REG_T2CL:
|
|
|
|
s->timers[1].latch = (s->timers[1].latch & 0xff00) | val;
|
|
|
|
break;
|
|
|
|
case VIA_REG_T2CH:
|
|
|
|
/* To ensure T2 generates an interrupt on zero crossing with the
|
|
|
|
common timer code, write the value directly from the latch to
|
|
|
|
the counter */
|
|
|
|
s->timers[1].latch = (s->timers[1].latch & 0xff) | (val << 8);
|
|
|
|
s->ifr &= ~T2_INT;
|
|
|
|
set_counter(s, &s->timers[1], s->timers[1].latch);
|
|
|
|
break;
|
|
|
|
case VIA_REG_SR:
|
|
|
|
s->sr = val;
|
|
|
|
break;
|
|
|
|
case VIA_REG_ACR:
|
|
|
|
s->acr = val;
|
2019-11-02 16:49:19 +01:00
|
|
|
mos6522_timer1_update(s, &s->timers[0],
|
|
|
|
qemu_clock_get_ns(QEMU_CLOCK_VIRTUAL));
|
2018-02-09 19:51:39 +01:00
|
|
|
break;
|
|
|
|
case VIA_REG_PCR:
|
|
|
|
s->pcr = val;
|
|
|
|
break;
|
|
|
|
case VIA_REG_IFR:
|
|
|
|
/* reset bits */
|
|
|
|
s->ifr &= ~val;
|
|
|
|
mos6522_update_irq(s);
|
|
|
|
break;
|
|
|
|
case VIA_REG_IER:
|
|
|
|
if (val & IER_SET) {
|
|
|
|
/* set bits */
|
|
|
|
s->ier |= val & 0x7f;
|
|
|
|
} else {
|
|
|
|
/* reset bits */
|
|
|
|
s->ier &= ~val;
|
|
|
|
}
|
|
|
|
mos6522_update_irq(s);
|
2019-11-02 16:49:19 +01:00
|
|
|
/* if IER is modified starts needed timers */
|
|
|
|
mos6522_timer1_update(s, &s->timers[0],
|
|
|
|
qemu_clock_get_ns(QEMU_CLOCK_VIRTUAL));
|
|
|
|
mos6522_timer2_update(s, &s->timers[1],
|
|
|
|
qemu_clock_get_ns(QEMU_CLOCK_VIRTUAL));
|
2018-02-09 19:51:39 +01:00
|
|
|
break;
|
|
|
|
default:
|
2019-12-20 22:40:54 +01:00
|
|
|
g_assert_not_reached();
|
2018-02-09 19:51:39 +01:00
|
|
|
}
|
|
|
|
}
|
|
|
|
|
|
|
|
static const MemoryRegionOps mos6522_ops = {
|
|
|
|
.read = mos6522_read,
|
|
|
|
.write = mos6522_write,
|
|
|
|
.endianness = DEVICE_NATIVE_ENDIAN,
|
|
|
|
.valid = {
|
|
|
|
.min_access_size = 1,
|
|
|
|
.max_access_size = 1,
|
|
|
|
},
|
|
|
|
};
|
|
|
|
|
|
|
|
static const VMStateDescription vmstate_mos6522_timer = {
|
|
|
|
.name = "mos6522_timer",
|
|
|
|
.version_id = 0,
|
|
|
|
.minimum_version_id = 0,
|
|
|
|
.fields = (VMStateField[]) {
|
|
|
|
VMSTATE_UINT16(latch, MOS6522Timer),
|
|
|
|
VMSTATE_UINT16(counter_value, MOS6522Timer),
|
|
|
|
VMSTATE_INT64(load_time, MOS6522Timer),
|
|
|
|
VMSTATE_INT64(next_irq_time, MOS6522Timer),
|
2018-06-07 19:17:51 +02:00
|
|
|
VMSTATE_TIMER_PTR(timer, MOS6522Timer),
|
2018-02-09 19:51:39 +01:00
|
|
|
VMSTATE_END_OF_LIST()
|
|
|
|
}
|
|
|
|
};
|
|
|
|
|
2018-06-07 19:17:49 +02:00
|
|
|
const VMStateDescription vmstate_mos6522 = {
|
2018-02-09 19:51:39 +01:00
|
|
|
.name = "mos6522",
|
|
|
|
.version_id = 0,
|
|
|
|
.minimum_version_id = 0,
|
|
|
|
.fields = (VMStateField[]) {
|
|
|
|
VMSTATE_UINT8(a, MOS6522State),
|
|
|
|
VMSTATE_UINT8(b, MOS6522State),
|
|
|
|
VMSTATE_UINT8(dira, MOS6522State),
|
|
|
|
VMSTATE_UINT8(dirb, MOS6522State),
|
|
|
|
VMSTATE_UINT8(sr, MOS6522State),
|
|
|
|
VMSTATE_UINT8(acr, MOS6522State),
|
|
|
|
VMSTATE_UINT8(pcr, MOS6522State),
|
|
|
|
VMSTATE_UINT8(ifr, MOS6522State),
|
|
|
|
VMSTATE_UINT8(ier, MOS6522State),
|
2018-06-07 19:17:48 +02:00
|
|
|
VMSTATE_STRUCT_ARRAY(timers, MOS6522State, 2, 0,
|
2018-02-09 19:51:39 +01:00
|
|
|
vmstate_mos6522_timer, MOS6522Timer),
|
|
|
|
VMSTATE_END_OF_LIST()
|
|
|
|
}
|
|
|
|
};
|
|
|
|
|
|
|
|
static void mos6522_reset(DeviceState *dev)
|
|
|
|
{
|
|
|
|
MOS6522State *s = MOS6522(dev);
|
|
|
|
|
|
|
|
s->b = 0;
|
|
|
|
s->a = 0;
|
|
|
|
s->dirb = 0xff;
|
|
|
|
s->dira = 0;
|
|
|
|
s->sr = 0;
|
|
|
|
s->acr = 0;
|
|
|
|
s->pcr = 0;
|
|
|
|
s->ifr = 0;
|
|
|
|
s->ier = 0;
|
|
|
|
/* s->ier = T1_INT | SR_INT; */
|
|
|
|
|
2018-06-07 19:17:50 +02:00
|
|
|
s->timers[0].frequency = s->frequency;
|
2018-02-09 19:51:39 +01:00
|
|
|
s->timers[0].latch = 0xffff;
|
|
|
|
set_counter(s, &s->timers[0], 0xffff);
|
2019-11-02 16:49:19 +01:00
|
|
|
timer_del(s->timers[0].timer);
|
2018-02-09 19:51:39 +01:00
|
|
|
|
|
|
|
s->timers[1].frequency = s->frequency;
|
2018-06-07 19:17:50 +02:00
|
|
|
s->timers[1].latch = 0xffff;
|
2019-11-02 16:49:19 +01:00
|
|
|
timer_del(s->timers[1].timer);
|
2018-02-09 19:51:39 +01:00
|
|
|
}
|
|
|
|
|
|
|
|
static void mos6522_init(Object *obj)
|
|
|
|
{
|
|
|
|
SysBusDevice *sbd = SYS_BUS_DEVICE(obj);
|
|
|
|
MOS6522State *s = MOS6522(obj);
|
|
|
|
int i;
|
|
|
|
|
|
|
|
memory_region_init_io(&s->mem, obj, &mos6522_ops, s, "mos6522", 0x10);
|
|
|
|
sysbus_init_mmio(sbd, &s->mem);
|
|
|
|
sysbus_init_irq(sbd, &s->irq);
|
|
|
|
|
|
|
|
for (i = 0; i < ARRAY_SIZE(s->timers); i++) {
|
|
|
|
s->timers[i].index = i;
|
|
|
|
}
|
|
|
|
|
|
|
|
s->timers[0].timer = timer_new_ns(QEMU_CLOCK_VIRTUAL, mos6522_timer1, s);
|
|
|
|
s->timers[1].timer = timer_new_ns(QEMU_CLOCK_VIRTUAL, mos6522_timer2, s);
|
|
|
|
}
|
|
|
|
|
|
|
|
static Property mos6522_properties[] = {
|
|
|
|
DEFINE_PROP_UINT64("frequency", MOS6522State, frequency, 0),
|
|
|
|
DEFINE_PROP_END_OF_LIST()
|
|
|
|
};
|
|
|
|
|
|
|
|
static void mos6522_class_init(ObjectClass *oc, void *data)
|
|
|
|
{
|
|
|
|
DeviceClass *dc = DEVICE_CLASS(oc);
|
|
|
|
MOS6522DeviceClass *mdc = MOS6522_DEVICE_CLASS(oc);
|
|
|
|
|
|
|
|
dc->reset = mos6522_reset;
|
|
|
|
dc->vmsd = &vmstate_mos6522;
|
2020-01-10 16:30:32 +01:00
|
|
|
device_class_set_props(dc, mos6522_properties);
|
2018-06-07 19:17:50 +02:00
|
|
|
mdc->parent_reset = dc->reset;
|
2018-02-09 19:51:39 +01:00
|
|
|
mdc->set_sr_int = mos6522_set_sr_int;
|
|
|
|
mdc->portB_write = mos6522_portB_write;
|
|
|
|
mdc->portA_write = mos6522_portA_write;
|
2018-06-13 10:30:15 +02:00
|
|
|
mdc->update_irq = mos6522_update_irq;
|
2018-02-09 19:51:39 +01:00
|
|
|
mdc->get_timer1_counter_value = mos6522_get_counter_value;
|
|
|
|
mdc->get_timer2_counter_value = mos6522_get_counter_value;
|
|
|
|
mdc->get_timer1_load_time = mos6522_get_load_time;
|
|
|
|
mdc->get_timer2_load_time = mos6522_get_load_time;
|
|
|
|
}
|
|
|
|
|
|
|
|
static const TypeInfo mos6522_type_info = {
|
|
|
|
.name = TYPE_MOS6522,
|
|
|
|
.parent = TYPE_SYS_BUS_DEVICE,
|
|
|
|
.instance_size = sizeof(MOS6522State),
|
|
|
|
.instance_init = mos6522_init,
|
|
|
|
.abstract = true,
|
|
|
|
.class_size = sizeof(MOS6522DeviceClass),
|
|
|
|
.class_init = mos6522_class_init,
|
|
|
|
};
|
|
|
|
|
|
|
|
static void mos6522_register_types(void)
|
|
|
|
{
|
|
|
|
type_register_static(&mos6522_type_info);
|
|
|
|
}
|
|
|
|
|
|
|
|
type_init(mos6522_register_types)
|