2009-05-20 19:37:39 +02:00
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/*
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* Microblaze helper routines.
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*
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* Copyright (c) 2009 Edgar E. Iglesias <edgar.iglesias@gmail.com>.
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2012-04-12 06:30:30 +02:00
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* Copyright (c) 2009-2012 PetaLogix Qld Pty Ltd.
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2009-05-20 19:37:39 +02:00
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*
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* This library is free software; you can redistribute it and/or
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* modify it under the terms of the GNU Lesser General Public
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* License as published by the Free Software Foundation; either
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* version 2 of the License, or (at your option) any later version.
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*
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* This library is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
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* Lesser General Public License for more details.
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*
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* You should have received a copy of the GNU Lesser General Public
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2009-07-16 22:47:01 +02:00
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* License along with this library; if not, see <http://www.gnu.org/licenses/>.
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2009-05-20 19:37:39 +02:00
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*/
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2016-01-26 19:05:31 +01:00
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#include "qemu/osdep.h"
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2011-07-13 14:44:15 +02:00
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#include "cpu.h"
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2014-04-08 07:31:41 +02:00
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#include "exec/helper-proto.h"
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2012-12-17 18:20:00 +01:00
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#include "qemu/host-utils.h"
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2016-03-15 13:18:37 +01:00
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#include "exec/exec-all.h"
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2014-03-28 19:42:10 +01:00
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#include "exec/cpu_ldst.h"
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2018-01-19 19:24:22 +01:00
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#include "fpu/softfloat.h"
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2009-05-20 19:37:39 +02:00
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2011-04-12 00:48:33 +02:00
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void helper_put(uint32_t id, uint32_t ctrl, uint32_t data)
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{
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int test = ctrl & STREAM_TEST;
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int atomic = ctrl & STREAM_ATOMIC;
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int control = ctrl & STREAM_CONTROL;
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int nonblock = ctrl & STREAM_NONBLOCK;
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int exception = ctrl & STREAM_EXCEPTION;
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2015-11-13 13:24:57 +01:00
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qemu_log_mask(LOG_UNIMP, "Unhandled stream put to stream-id=%d data=%x %s%s%s%s%s\n",
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2011-04-12 00:48:33 +02:00
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id, data,
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test ? "t" : "",
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nonblock ? "n" : "",
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exception ? "e" : "",
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control ? "c" : "",
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atomic ? "a" : "");
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}
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uint32_t helper_get(uint32_t id, uint32_t ctrl)
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{
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int test = ctrl & STREAM_TEST;
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int atomic = ctrl & STREAM_ATOMIC;
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int control = ctrl & STREAM_CONTROL;
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int nonblock = ctrl & STREAM_NONBLOCK;
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int exception = ctrl & STREAM_EXCEPTION;
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2015-11-13 13:24:57 +01:00
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qemu_log_mask(LOG_UNIMP, "Unhandled stream get from stream-id=%d %s%s%s%s%s\n",
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2011-04-12 00:48:33 +02:00
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id,
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test ? "t" : "",
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nonblock ? "n" : "",
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exception ? "e" : "",
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control ? "c" : "",
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atomic ? "a" : "");
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return 0xdead0000 | id;
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}
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2012-09-02 10:39:22 +02:00
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void helper_raise_exception(CPUMBState *env, uint32_t index)
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2009-05-20 19:37:39 +02:00
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{
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2019-03-23 02:27:36 +01:00
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CPUState *cs = env_cpu(env);
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2013-08-26 08:31:06 +02:00
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cs->exception_index = index;
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2013-08-27 17:52:12 +02:00
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cpu_loop_exit(cs);
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2009-05-20 19:37:39 +02:00
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}
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2020-08-18 08:12:14 +02:00
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static bool check_divz(CPUMBState *env, uint32_t a, uint32_t b, uintptr_t ra)
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2009-05-20 19:37:39 +02:00
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{
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2020-08-18 08:12:14 +02:00
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if (unlikely(b == 0)) {
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2020-08-20 06:41:10 +02:00
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env->msr |= MSR_DZ;
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2009-09-03 12:52:01 +02:00
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2020-08-18 08:12:14 +02:00
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if ((env->msr & MSR_EE) &&
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env_archcpu(env)->cfg.div_zero_exception) {
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CPUState *cs = env_cpu(env);
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|
2020-08-20 06:50:35 +02:00
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env->esr = ESR_EC_DIVZERO;
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2020-08-18 08:12:14 +02:00
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cs->exception_index = EXCP_HW_EXCP;
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cpu_loop_exit_restore(cs, ra);
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2009-09-03 12:52:01 +02:00
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}
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2020-08-18 08:12:14 +02:00
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return false;
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2009-05-20 19:37:39 +02:00
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}
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2020-08-18 08:12:14 +02:00
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return true;
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2009-05-20 19:37:39 +02:00
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}
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2012-09-02 10:39:22 +02:00
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uint32_t helper_divs(CPUMBState *env, uint32_t a, uint32_t b)
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2009-05-20 19:37:39 +02:00
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{
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2020-08-18 08:12:14 +02:00
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if (!check_divz(env, a, b, GETPC())) {
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2009-05-20 19:37:39 +02:00
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return 0;
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2012-09-02 10:39:22 +02:00
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}
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2009-05-20 19:37:39 +02:00
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return (int32_t)a / (int32_t)b;
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}
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2012-09-02 10:39:22 +02:00
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uint32_t helper_divu(CPUMBState *env, uint32_t a, uint32_t b)
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2009-05-20 19:37:39 +02:00
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{
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2020-08-18 08:12:14 +02:00
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if (!check_divz(env, a, b, GETPC())) {
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2009-05-20 19:37:39 +02:00
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return 0;
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2012-09-02 10:39:22 +02:00
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}
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2009-05-20 19:37:39 +02:00
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return a / b;
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}
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2010-09-09 10:20:17 +02:00
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/* raise FPU exception. */
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2012-09-02 10:39:22 +02:00
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static void raise_fpu_exception(CPUMBState *env)
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2010-09-09 10:20:17 +02:00
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{
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2020-08-20 06:50:35 +02:00
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env->esr = ESR_EC_FPU;
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2012-09-02 10:39:22 +02:00
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helper_raise_exception(env, EXCP_HW_EXCP);
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2010-09-09 10:20:17 +02:00
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}
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2012-09-02 10:39:22 +02:00
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static void update_fpu_flags(CPUMBState *env, int flags)
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2010-09-09 10:20:17 +02:00
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{
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int raise = 0;
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if (flags & float_flag_invalid) {
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2020-08-20 06:54:38 +02:00
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env->fsr |= FSR_IO;
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2010-09-09 10:20:17 +02:00
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raise = 1;
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}
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if (flags & float_flag_divbyzero) {
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2020-08-20 06:54:38 +02:00
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env->fsr |= FSR_DZ;
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2010-09-09 10:20:17 +02:00
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raise = 1;
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}
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if (flags & float_flag_overflow) {
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2020-08-20 06:54:38 +02:00
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env->fsr |= FSR_OF;
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2010-09-09 10:20:17 +02:00
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raise = 1;
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}
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if (flags & float_flag_underflow) {
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2020-08-20 06:54:38 +02:00
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env->fsr |= FSR_UF;
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2010-09-09 10:20:17 +02:00
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raise = 1;
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}
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if (raise
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&& (env->pvr.regs[2] & PVR2_FPU_EXC_MASK)
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2020-08-20 06:41:10 +02:00
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&& (env->msr & MSR_EE)) {
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2012-09-02 10:39:22 +02:00
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raise_fpu_exception(env);
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2010-09-09 10:20:17 +02:00
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}
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}
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2012-09-02 10:39:22 +02:00
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uint32_t helper_fadd(CPUMBState *env, uint32_t a, uint32_t b)
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2010-09-09 10:20:17 +02:00
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{
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CPU_FloatU fd, fa, fb;
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int flags;
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set_float_exception_flags(0, &env->fp_status);
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fa.l = a;
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fb.l = b;
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fd.f = float32_add(fa.f, fb.f, &env->fp_status);
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flags = get_float_exception_flags(&env->fp_status);
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2012-09-02 10:39:22 +02:00
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update_fpu_flags(env, flags);
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2010-09-09 10:20:17 +02:00
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return fd.l;
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}
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2012-09-02 10:39:22 +02:00
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uint32_t helper_frsub(CPUMBState *env, uint32_t a, uint32_t b)
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2010-09-09 10:20:17 +02:00
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{
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CPU_FloatU fd, fa, fb;
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int flags;
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set_float_exception_flags(0, &env->fp_status);
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fa.l = a;
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fb.l = b;
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fd.f = float32_sub(fb.f, fa.f, &env->fp_status);
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flags = get_float_exception_flags(&env->fp_status);
|
2012-09-02 10:39:22 +02:00
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update_fpu_flags(env, flags);
|
2010-09-09 10:20:17 +02:00
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|
return fd.l;
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}
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|
2012-09-02 10:39:22 +02:00
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uint32_t helper_fmul(CPUMBState *env, uint32_t a, uint32_t b)
|
2010-09-09 10:20:17 +02:00
|
|
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{
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CPU_FloatU fd, fa, fb;
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int flags;
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set_float_exception_flags(0, &env->fp_status);
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fa.l = a;
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fb.l = b;
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fd.f = float32_mul(fa.f, fb.f, &env->fp_status);
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|
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flags = get_float_exception_flags(&env->fp_status);
|
2012-09-02 10:39:22 +02:00
|
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update_fpu_flags(env, flags);
|
2010-09-09 10:20:17 +02:00
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return fd.l;
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|
}
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|
|
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|
2012-09-02 10:39:22 +02:00
|
|
|
uint32_t helper_fdiv(CPUMBState *env, uint32_t a, uint32_t b)
|
2010-09-09 10:20:17 +02:00
|
|
|
{
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|
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|
CPU_FloatU fd, fa, fb;
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int flags;
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set_float_exception_flags(0, &env->fp_status);
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fa.l = a;
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fb.l = b;
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fd.f = float32_div(fb.f, fa.f, &env->fp_status);
|
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flags = get_float_exception_flags(&env->fp_status);
|
2012-09-02 10:39:22 +02:00
|
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update_fpu_flags(env, flags);
|
2010-09-09 10:20:17 +02:00
|
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return fd.l;
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|
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}
|
|
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|
2012-09-02 10:39:22 +02:00
|
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uint32_t helper_fcmp_un(CPUMBState *env, uint32_t a, uint32_t b)
|
2010-09-09 10:20:17 +02:00
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{
|
2010-09-09 22:05:48 +02:00
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CPU_FloatU fa, fb;
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uint32_t r = 0;
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fa.l = a;
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fb.l = b;
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|
softfloat: Implement run-time-configurable meaning of signaling NaN bit
This patch modifies SoftFloat library so that it can be configured in
run-time in relation to the meaning of signaling NaN bit, while, at the
same time, strictly preserving its behavior on all existing platforms.
Background:
In floating-point calculations, there is a need for denoting undefined or
unrepresentable values. This is achieved by defining certain floating-point
numerical values to be NaNs (which stands for "not a number"). For additional
reasons, virtually all modern floating-point unit implementations use two
kinds of NaNs: quiet and signaling. The binary representations of these two
kinds of NaNs, as a rule, differ only in one bit (that bit is, traditionally,
the first bit of mantissa).
Up to 2008, standards for floating-point did not specify all details about
binary representation of NaNs. More specifically, the meaning of the bit
that is used for distinguishing between signaling and quiet NaNs was not
strictly prescribed. (IEEE 754-2008 was the first floating-point standard
that defined that meaning clearly, see [1], p. 35) As a result, different
platforms took different approaches, and that presented considerable
challenge for multi-platform emulators like QEMU.
Mips platform represents the most complex case among QEMU-supported
platforms regarding signaling NaN bit. Up to the Release 6 of Mips
architecture, "1" in signaling NaN bit denoted signaling NaN, which is
opposite to IEEE 754-2008 standard. From Release 6 on, Mips architecture
adopted IEEE standard prescription, and "0" denotes signaling NaN. On top of
that, Mips architecture for SIMD (also known as MSA, or vector instructions)
also specifies signaling bit in accordance to IEEE standard. MSA unit can be
implemented with both pre-Release 6 and Release 6 main processor units.
QEMU uses SoftFloat library to implement various floating-point-related
instructions on all platforms. The current QEMU implementation allows for
defining meaning of signaling NaN bit during build time, and is implemented
via preprocessor macro called SNAN_BIT_IS_ONE.
On the other hand, the change in this patch enables SoftFloat library to be
configured in run-time. This configuration is meant to occur during CPU
initialization, at the moment when it is definitely known what desired
behavior for particular CPU (or any additional FPUs) is.
The change is implemented so that it is consistent with existing
implementation of similar cases. This means that structure float_status is
used for passing the information about desired signaling NaN bit on each
invocation of SoftFloat functions. The additional field in float_status is
called snan_bit_is_one, which supersedes macro SNAN_BIT_IS_ONE.
IMPORTANT:
This change is not meant to create any change in emulator behavior or
functionality on any platform. It just provides the means for SoftFloat
library to be used in a more flexible way - in other words, it will just
prepare SoftFloat library for usage related to Mips platform and its
specifics regarding signaling bit meaning, which is done in some of
subsequent patches from this series.
Further break down of changes:
1) Added field snan_bit_is_one to the structure float_status, and
correspondent setter function set_snan_bit_is_one().
2) Constants <float16|float32|float64|floatx80|float128>_default_nan
(used both internally and externally) converted to functions
<float16|float32|float64|floatx80|float128>_default_nan(float_status*).
This is necessary since they are dependent on signaling bit meaning.
At the same time, for the sake of code cleanup and simplicity, constants
<floatx80|float128>_default_nan_<low|high> (used only internally within
SoftFloat library) are removed, as not needed.
3) Added a float_status* argument to SoftFloat library functions
XXX_is_quiet_nan(XXX a_), XXX_is_signaling_nan(XXX a_),
XXX_maybe_silence_nan(XXX a_). This argument must be present in
order to enable correct invocation of new version of functions
XXX_default_nan(). (XXX is <float16|float32|float64|floatx80|float128>
here)
4) Updated code for all platforms to reflect changes in SoftFloat library.
This change is twofolds: it includes modifications of SoftFloat library
functions invocations, and an addition of invocation of function
set_snan_bit_is_one() during CPU initialization, with arguments that
are appropriate for each particular platform. It was established that
all platforms zero their main CPU data structures, so snan_bit_is_one(0)
in appropriate places is not added, as it is not needed.
[1] "IEEE Standard for Floating-Point Arithmetic",
IEEE Computer Society, August 29, 2008.
Signed-off-by: Thomas Schwinge <thomas@codesourcery.com>
Signed-off-by: Maciej W. Rozycki <macro@codesourcery.com>
Signed-off-by: Aleksandar Markovic <aleksandar.markovic@imgtec.com>
Tested-by: Bastian Koppelmann <kbastian@mail.uni-paderborn.de>
Reviewed-by: Leon Alrae <leon.alrae@imgtec.com>
Tested-by: Leon Alrae <leon.alrae@imgtec.com>
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
[leon.alrae@imgtec.com:
* cherry-picked 2 chunks from patch #2 to fix compilation warnings]
Signed-off-by: Leon Alrae <leon.alrae@imgtec.com>
2016-06-10 11:57:28 +02:00
|
|
|
if (float32_is_signaling_nan(fa.f, &env->fp_status) ||
|
|
|
|
float32_is_signaling_nan(fb.f, &env->fp_status)) {
|
2012-09-02 10:39:22 +02:00
|
|
|
update_fpu_flags(env, float_flag_invalid);
|
2010-09-09 22:05:48 +02:00
|
|
|
r = 1;
|
|
|
|
}
|
|
|
|
|
softfloat: Implement run-time-configurable meaning of signaling NaN bit
This patch modifies SoftFloat library so that it can be configured in
run-time in relation to the meaning of signaling NaN bit, while, at the
same time, strictly preserving its behavior on all existing platforms.
Background:
In floating-point calculations, there is a need for denoting undefined or
unrepresentable values. This is achieved by defining certain floating-point
numerical values to be NaNs (which stands for "not a number"). For additional
reasons, virtually all modern floating-point unit implementations use two
kinds of NaNs: quiet and signaling. The binary representations of these two
kinds of NaNs, as a rule, differ only in one bit (that bit is, traditionally,
the first bit of mantissa).
Up to 2008, standards for floating-point did not specify all details about
binary representation of NaNs. More specifically, the meaning of the bit
that is used for distinguishing between signaling and quiet NaNs was not
strictly prescribed. (IEEE 754-2008 was the first floating-point standard
that defined that meaning clearly, see [1], p. 35) As a result, different
platforms took different approaches, and that presented considerable
challenge for multi-platform emulators like QEMU.
Mips platform represents the most complex case among QEMU-supported
platforms regarding signaling NaN bit. Up to the Release 6 of Mips
architecture, "1" in signaling NaN bit denoted signaling NaN, which is
opposite to IEEE 754-2008 standard. From Release 6 on, Mips architecture
adopted IEEE standard prescription, and "0" denotes signaling NaN. On top of
that, Mips architecture for SIMD (also known as MSA, or vector instructions)
also specifies signaling bit in accordance to IEEE standard. MSA unit can be
implemented with both pre-Release 6 and Release 6 main processor units.
QEMU uses SoftFloat library to implement various floating-point-related
instructions on all platforms. The current QEMU implementation allows for
defining meaning of signaling NaN bit during build time, and is implemented
via preprocessor macro called SNAN_BIT_IS_ONE.
On the other hand, the change in this patch enables SoftFloat library to be
configured in run-time. This configuration is meant to occur during CPU
initialization, at the moment when it is definitely known what desired
behavior for particular CPU (or any additional FPUs) is.
The change is implemented so that it is consistent with existing
implementation of similar cases. This means that structure float_status is
used for passing the information about desired signaling NaN bit on each
invocation of SoftFloat functions. The additional field in float_status is
called snan_bit_is_one, which supersedes macro SNAN_BIT_IS_ONE.
IMPORTANT:
This change is not meant to create any change in emulator behavior or
functionality on any platform. It just provides the means for SoftFloat
library to be used in a more flexible way - in other words, it will just
prepare SoftFloat library for usage related to Mips platform and its
specifics regarding signaling bit meaning, which is done in some of
subsequent patches from this series.
Further break down of changes:
1) Added field snan_bit_is_one to the structure float_status, and
correspondent setter function set_snan_bit_is_one().
2) Constants <float16|float32|float64|floatx80|float128>_default_nan
(used both internally and externally) converted to functions
<float16|float32|float64|floatx80|float128>_default_nan(float_status*).
This is necessary since they are dependent on signaling bit meaning.
At the same time, for the sake of code cleanup and simplicity, constants
<floatx80|float128>_default_nan_<low|high> (used only internally within
SoftFloat library) are removed, as not needed.
3) Added a float_status* argument to SoftFloat library functions
XXX_is_quiet_nan(XXX a_), XXX_is_signaling_nan(XXX a_),
XXX_maybe_silence_nan(XXX a_). This argument must be present in
order to enable correct invocation of new version of functions
XXX_default_nan(). (XXX is <float16|float32|float64|floatx80|float128>
here)
4) Updated code for all platforms to reflect changes in SoftFloat library.
This change is twofolds: it includes modifications of SoftFloat library
functions invocations, and an addition of invocation of function
set_snan_bit_is_one() during CPU initialization, with arguments that
are appropriate for each particular platform. It was established that
all platforms zero their main CPU data structures, so snan_bit_is_one(0)
in appropriate places is not added, as it is not needed.
[1] "IEEE Standard for Floating-Point Arithmetic",
IEEE Computer Society, August 29, 2008.
Signed-off-by: Thomas Schwinge <thomas@codesourcery.com>
Signed-off-by: Maciej W. Rozycki <macro@codesourcery.com>
Signed-off-by: Aleksandar Markovic <aleksandar.markovic@imgtec.com>
Tested-by: Bastian Koppelmann <kbastian@mail.uni-paderborn.de>
Reviewed-by: Leon Alrae <leon.alrae@imgtec.com>
Tested-by: Leon Alrae <leon.alrae@imgtec.com>
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
[leon.alrae@imgtec.com:
* cherry-picked 2 chunks from patch #2 to fix compilation warnings]
Signed-off-by: Leon Alrae <leon.alrae@imgtec.com>
2016-06-10 11:57:28 +02:00
|
|
|
if (float32_is_quiet_nan(fa.f, &env->fp_status) ||
|
|
|
|
float32_is_quiet_nan(fb.f, &env->fp_status)) {
|
2010-09-09 22:05:48 +02:00
|
|
|
r = 1;
|
|
|
|
}
|
|
|
|
|
|
|
|
return r;
|
2010-09-09 10:20:17 +02:00
|
|
|
}
|
|
|
|
|
2012-09-02 10:39:22 +02:00
|
|
|
uint32_t helper_fcmp_lt(CPUMBState *env, uint32_t a, uint32_t b)
|
2010-09-09 10:20:17 +02:00
|
|
|
{
|
|
|
|
CPU_FloatU fa, fb;
|
|
|
|
int r;
|
|
|
|
int flags;
|
|
|
|
|
|
|
|
set_float_exception_flags(0, &env->fp_status);
|
|
|
|
fa.l = a;
|
|
|
|
fb.l = b;
|
|
|
|
r = float32_lt(fb.f, fa.f, &env->fp_status);
|
|
|
|
flags = get_float_exception_flags(&env->fp_status);
|
2012-09-02 10:39:22 +02:00
|
|
|
update_fpu_flags(env, flags & float_flag_invalid);
|
2010-09-09 10:20:17 +02:00
|
|
|
|
|
|
|
return r;
|
|
|
|
}
|
|
|
|
|
2012-09-02 10:39:22 +02:00
|
|
|
uint32_t helper_fcmp_eq(CPUMBState *env, uint32_t a, uint32_t b)
|
2010-09-09 10:20:17 +02:00
|
|
|
{
|
|
|
|
CPU_FloatU fa, fb;
|
|
|
|
int flags;
|
|
|
|
int r;
|
|
|
|
|
|
|
|
set_float_exception_flags(0, &env->fp_status);
|
|
|
|
fa.l = a;
|
|
|
|
fb.l = b;
|
2011-04-14 00:49:29 +02:00
|
|
|
r = float32_eq_quiet(fa.f, fb.f, &env->fp_status);
|
2010-09-09 10:20:17 +02:00
|
|
|
flags = get_float_exception_flags(&env->fp_status);
|
2012-09-02 10:39:22 +02:00
|
|
|
update_fpu_flags(env, flags & float_flag_invalid);
|
2010-09-09 10:20:17 +02:00
|
|
|
|
|
|
|
return r;
|
|
|
|
}
|
|
|
|
|
2012-09-02 10:39:22 +02:00
|
|
|
uint32_t helper_fcmp_le(CPUMBState *env, uint32_t a, uint32_t b)
|
2010-09-09 10:20:17 +02:00
|
|
|
{
|
|
|
|
CPU_FloatU fa, fb;
|
|
|
|
int flags;
|
|
|
|
int r;
|
|
|
|
|
|
|
|
fa.l = a;
|
|
|
|
fb.l = b;
|
|
|
|
set_float_exception_flags(0, &env->fp_status);
|
|
|
|
r = float32_le(fa.f, fb.f, &env->fp_status);
|
|
|
|
flags = get_float_exception_flags(&env->fp_status);
|
2012-09-02 10:39:22 +02:00
|
|
|
update_fpu_flags(env, flags & float_flag_invalid);
|
2010-09-09 10:20:17 +02:00
|
|
|
|
|
|
|
|
|
|
|
return r;
|
|
|
|
}
|
|
|
|
|
2012-09-02 10:39:22 +02:00
|
|
|
uint32_t helper_fcmp_gt(CPUMBState *env, uint32_t a, uint32_t b)
|
2010-09-09 10:20:17 +02:00
|
|
|
{
|
|
|
|
CPU_FloatU fa, fb;
|
|
|
|
int flags, r;
|
|
|
|
|
|
|
|
fa.l = a;
|
|
|
|
fb.l = b;
|
|
|
|
set_float_exception_flags(0, &env->fp_status);
|
|
|
|
r = float32_lt(fa.f, fb.f, &env->fp_status);
|
|
|
|
flags = get_float_exception_flags(&env->fp_status);
|
2012-09-02 10:39:22 +02:00
|
|
|
update_fpu_flags(env, flags & float_flag_invalid);
|
2010-09-09 10:20:17 +02:00
|
|
|
return r;
|
|
|
|
}
|
|
|
|
|
2012-09-02 10:39:22 +02:00
|
|
|
uint32_t helper_fcmp_ne(CPUMBState *env, uint32_t a, uint32_t b)
|
2010-09-09 10:20:17 +02:00
|
|
|
{
|
|
|
|
CPU_FloatU fa, fb;
|
|
|
|
int flags, r;
|
|
|
|
|
|
|
|
fa.l = a;
|
|
|
|
fb.l = b;
|
|
|
|
set_float_exception_flags(0, &env->fp_status);
|
2011-04-14 00:49:29 +02:00
|
|
|
r = !float32_eq_quiet(fa.f, fb.f, &env->fp_status);
|
2010-09-09 10:20:17 +02:00
|
|
|
flags = get_float_exception_flags(&env->fp_status);
|
2012-09-02 10:39:22 +02:00
|
|
|
update_fpu_flags(env, flags & float_flag_invalid);
|
2010-09-09 10:20:17 +02:00
|
|
|
|
|
|
|
return r;
|
|
|
|
}
|
|
|
|
|
2012-09-02 10:39:22 +02:00
|
|
|
uint32_t helper_fcmp_ge(CPUMBState *env, uint32_t a, uint32_t b)
|
2010-09-09 10:20:17 +02:00
|
|
|
{
|
|
|
|
CPU_FloatU fa, fb;
|
|
|
|
int flags, r;
|
|
|
|
|
|
|
|
fa.l = a;
|
|
|
|
fb.l = b;
|
|
|
|
set_float_exception_flags(0, &env->fp_status);
|
|
|
|
r = !float32_lt(fa.f, fb.f, &env->fp_status);
|
|
|
|
flags = get_float_exception_flags(&env->fp_status);
|
2012-09-02 10:39:22 +02:00
|
|
|
update_fpu_flags(env, flags & float_flag_invalid);
|
2010-09-09 10:20:17 +02:00
|
|
|
|
|
|
|
return r;
|
|
|
|
}
|
|
|
|
|
2012-09-02 10:39:22 +02:00
|
|
|
uint32_t helper_flt(CPUMBState *env, uint32_t a)
|
2010-09-09 10:20:17 +02:00
|
|
|
{
|
|
|
|
CPU_FloatU fd, fa;
|
|
|
|
|
|
|
|
fa.l = a;
|
|
|
|
fd.f = int32_to_float32(fa.l, &env->fp_status);
|
|
|
|
return fd.l;
|
|
|
|
}
|
|
|
|
|
2012-09-02 10:39:22 +02:00
|
|
|
uint32_t helper_fint(CPUMBState *env, uint32_t a)
|
2010-09-09 10:20:17 +02:00
|
|
|
{
|
|
|
|
CPU_FloatU fa;
|
|
|
|
uint32_t r;
|
|
|
|
int flags;
|
|
|
|
|
|
|
|
set_float_exception_flags(0, &env->fp_status);
|
|
|
|
fa.l = a;
|
|
|
|
r = float32_to_int32(fa.f, &env->fp_status);
|
|
|
|
flags = get_float_exception_flags(&env->fp_status);
|
2012-09-02 10:39:22 +02:00
|
|
|
update_fpu_flags(env, flags);
|
2010-09-09 10:20:17 +02:00
|
|
|
|
|
|
|
return r;
|
|
|
|
}
|
|
|
|
|
2012-09-02 10:39:22 +02:00
|
|
|
uint32_t helper_fsqrt(CPUMBState *env, uint32_t a)
|
2010-09-09 10:20:17 +02:00
|
|
|
{
|
|
|
|
CPU_FloatU fd, fa;
|
|
|
|
int flags;
|
|
|
|
|
|
|
|
set_float_exception_flags(0, &env->fp_status);
|
|
|
|
fa.l = a;
|
|
|
|
fd.l = float32_sqrt(fa.f, &env->fp_status);
|
|
|
|
flags = get_float_exception_flags(&env->fp_status);
|
2012-09-02 10:39:22 +02:00
|
|
|
update_fpu_flags(env, flags);
|
2010-09-09 10:20:17 +02:00
|
|
|
|
|
|
|
return fd.l;
|
|
|
|
}
|
|
|
|
|
2009-05-20 19:37:39 +02:00
|
|
|
uint32_t helper_pcmpbf(uint32_t a, uint32_t b)
|
|
|
|
{
|
|
|
|
unsigned int i;
|
|
|
|
uint32_t mask = 0xff000000;
|
|
|
|
|
|
|
|
for (i = 0; i < 4; i++) {
|
|
|
|
if ((a & mask) == (b & mask))
|
|
|
|
return i + 1;
|
|
|
|
mask >>= 8;
|
|
|
|
}
|
|
|
|
return 0;
|
|
|
|
}
|
|
|
|
|
2018-04-13 20:20:25 +02:00
|
|
|
void helper_memalign(CPUMBState *env, target_ulong addr,
|
|
|
|
uint32_t dr, uint32_t wr,
|
2012-09-02 10:39:22 +02:00
|
|
|
uint32_t mask)
|
2009-09-03 12:59:46 +02:00
|
|
|
{
|
|
|
|
if (addr & mask) {
|
2009-09-11 10:27:38 +02:00
|
|
|
qemu_log_mask(CPU_LOG_INT,
|
2018-04-13 20:20:25 +02:00
|
|
|
"unaligned access addr=" TARGET_FMT_lx
|
|
|
|
" mask=%x, wr=%d dr=r%d\n",
|
2009-09-11 10:27:38 +02:00
|
|
|
addr, mask, wr, dr);
|
2020-08-20 06:46:10 +02:00
|
|
|
env->ear = addr;
|
2020-08-20 06:50:35 +02:00
|
|
|
env->esr = ESR_EC_UNALIGNED_DATA | (wr << 10) | (dr & 31) << 5;
|
2009-09-03 22:28:21 +02:00
|
|
|
if (mask == 3) {
|
2020-08-20 06:50:35 +02:00
|
|
|
env->esr |= 1 << 11;
|
2009-09-03 12:59:46 +02:00
|
|
|
}
|
2020-08-20 06:41:10 +02:00
|
|
|
if (!(env->msr & MSR_EE)) {
|
2009-09-11 10:27:38 +02:00
|
|
|
return;
|
|
|
|
}
|
2012-09-02 10:39:22 +02:00
|
|
|
helper_raise_exception(env, EXCP_HW_EXCP);
|
2009-09-03 12:59:46 +02:00
|
|
|
}
|
|
|
|
}
|
|
|
|
|
2018-04-13 20:20:25 +02:00
|
|
|
void helper_stackprot(CPUMBState *env, target_ulong addr)
|
2012-01-10 10:27:11 +01:00
|
|
|
{
|
|
|
|
if (addr < env->slr || addr > env->shr) {
|
2018-04-13 20:20:25 +02:00
|
|
|
qemu_log_mask(CPU_LOG_INT, "Stack protector violation at "
|
|
|
|
TARGET_FMT_lx " %x %x\n",
|
2015-11-13 13:24:57 +01:00
|
|
|
addr, env->slr, env->shr);
|
2020-08-20 06:46:10 +02:00
|
|
|
env->ear = addr;
|
2020-08-20 06:50:35 +02:00
|
|
|
env->esr = ESR_EC_STACKPROT;
|
2015-05-29 08:29:28 +02:00
|
|
|
helper_raise_exception(env, EXCP_HW_EXCP);
|
2012-01-10 10:27:11 +01:00
|
|
|
}
|
|
|
|
}
|
|
|
|
|
2009-05-20 19:37:39 +02:00
|
|
|
#if !defined(CONFIG_USER_ONLY)
|
|
|
|
/* Writes/reads to the MMU's special regs end up here. */
|
2018-04-16 21:25:01 +02:00
|
|
|
uint32_t helper_mmu_read(CPUMBState *env, uint32_t ext, uint32_t rn)
|
2009-05-20 19:37:39 +02:00
|
|
|
{
|
2018-04-16 21:25:01 +02:00
|
|
|
return mmu_read(env, ext, rn);
|
2009-05-20 19:37:39 +02:00
|
|
|
}
|
|
|
|
|
2018-04-16 21:25:01 +02:00
|
|
|
void helper_mmu_write(CPUMBState *env, uint32_t ext, uint32_t rn, uint32_t v)
|
2009-05-20 19:37:39 +02:00
|
|
|
{
|
2018-04-16 21:25:01 +02:00
|
|
|
mmu_write(env, ext, rn, v);
|
2009-05-20 19:37:39 +02:00
|
|
|
}
|
2009-09-03 13:25:09 +02:00
|
|
|
|
2018-12-10 18:56:30 +01:00
|
|
|
void mb_cpu_transaction_failed(CPUState *cs, hwaddr physaddr, vaddr addr,
|
|
|
|
unsigned size, MMUAccessType access_type,
|
|
|
|
int mmu_idx, MemTxAttrs attrs,
|
|
|
|
MemTxResult response, uintptr_t retaddr)
|
2009-09-03 13:25:09 +02:00
|
|
|
{
|
2013-05-27 06:49:53 +02:00
|
|
|
MicroBlazeCPU *cpu;
|
|
|
|
CPUMBState *env;
|
2018-12-10 18:56:30 +01:00
|
|
|
qemu_log_mask(CPU_LOG_INT, "Transaction failed: vaddr 0x%" VADDR_PRIx
|
|
|
|
" physaddr 0x" TARGET_FMT_plx " size %d access type %s\n",
|
|
|
|
addr, physaddr, size,
|
|
|
|
access_type == MMU_INST_FETCH ? "INST_FETCH" :
|
|
|
|
(access_type == MMU_DATA_LOAD ? "DATA_LOAD" : "DATA_STORE"));
|
2013-05-27 06:49:53 +02:00
|
|
|
cpu = MICROBLAZE_CPU(cs);
|
|
|
|
env = &cpu->env;
|
2018-12-10 18:56:30 +01:00
|
|
|
|
|
|
|
cpu_restore_state(cs, retaddr, true);
|
2020-08-20 06:41:10 +02:00
|
|
|
if (!(env->msr & MSR_EE)) {
|
2009-09-03 13:25:09 +02:00
|
|
|
return;
|
|
|
|
}
|
|
|
|
|
2020-08-20 06:46:10 +02:00
|
|
|
env->ear = addr;
|
2018-12-10 18:56:30 +01:00
|
|
|
if (access_type == MMU_INST_FETCH) {
|
2009-09-11 10:27:38 +02:00
|
|
|
if ((env->pvr.regs[2] & PVR2_IOPB_BUS_EXC_MASK)) {
|
2020-08-20 06:50:35 +02:00
|
|
|
env->esr = ESR_EC_INSN_BUS;
|
2012-09-02 10:39:22 +02:00
|
|
|
helper_raise_exception(env, EXCP_HW_EXCP);
|
2009-09-03 13:25:09 +02:00
|
|
|
}
|
|
|
|
} else {
|
2009-09-11 10:27:38 +02:00
|
|
|
if ((env->pvr.regs[2] & PVR2_DOPB_BUS_EXC_MASK)) {
|
2020-08-20 06:50:35 +02:00
|
|
|
env->esr = ESR_EC_DATA_BUS;
|
2012-09-02 10:39:22 +02:00
|
|
|
helper_raise_exception(env, EXCP_HW_EXCP);
|
2009-09-03 13:25:09 +02:00
|
|
|
}
|
|
|
|
}
|
|
|
|
}
|
2010-03-01 05:11:28 +01:00
|
|
|
#endif
|