2012-01-26 12:43:49 +01:00
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/*
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* Calxeda Highbank SoC emulation
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*
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* Copyright (c) 2010-2012 Calxeda
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*
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* This program is free software; you can redistribute it and/or modify it
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* under the terms and conditions of the GNU General Public License,
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* version 2 or later, as published by the Free Software Foundation.
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*
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* This program is distributed in the hope it will be useful, but WITHOUT
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* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
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* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
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* more details.
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*
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* You should have received a copy of the GNU General Public License along with
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* this program. If not, see <http://www.gnu.org/licenses/>.
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*
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*/
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2013-02-04 15:40:22 +01:00
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#include "hw/sysbus.h"
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2013-04-09 16:26:55 +02:00
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#include "hw/arm/arm.h"
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#include "hw/devices.h"
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2013-02-04 15:40:22 +01:00
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#include "hw/loader.h"
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2012-10-24 08:43:34 +02:00
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#include "net/net.h"
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2012-12-17 18:20:04 +01:00
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#include "sysemu/sysemu.h"
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2013-02-04 15:40:22 +01:00
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#include "hw/boards.h"
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2014-10-07 13:59:18 +02:00
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#include "sysemu/block-backend.h"
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2012-12-17 18:19:49 +01:00
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#include "exec/address-spaces.h"
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2013-12-17 20:42:28 +01:00
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#include "qemu/error-report.h"
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2012-01-26 12:43:49 +01:00
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2013-12-17 20:42:29 +01:00
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#define SMP_BOOT_ADDR 0x100
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#define SMP_BOOT_REG 0x40
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#define MPCORE_PERIPHBASE 0xfff10000
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2012-01-26 12:43:49 +01:00
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2013-12-17 20:42:29 +01:00
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#define NIRQ_GIC 160
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2012-01-26 12:43:49 +01:00
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/* Board init. */
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2012-05-14 00:08:10 +02:00
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static void hb_write_secondary(ARMCPU *cpu, const struct arm_boot_info *info)
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2012-01-26 12:43:49 +01:00
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{
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int n;
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uint32_t smpboot[] = {
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0xee100fb0, /* mrc p15, 0, r0, c0, c0, 5 - read current core id */
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0xe210000f, /* ands r0, r0, #0x0f */
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0xe3a03040, /* mov r3, #0x40 - jump address is 0x40 + 0x10 * core id */
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0xe0830200, /* add r0, r3, r0, lsl #4 */
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2012-12-11 12:30:37 +01:00
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0xe59f2024, /* ldr r2, privbase */
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2012-01-26 12:43:49 +01:00
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0xe3a01001, /* mov r1, #1 */
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2012-12-11 12:30:37 +01:00
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0xe5821100, /* str r1, [r2, #256] - set GICC_CTLR.Enable */
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0xe3a010ff, /* mov r1, #0xff */
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0xe5821104, /* str r1, [r2, #260] - set GICC_PMR.Priority to 0xff */
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0xf57ff04f, /* dsb */
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2012-01-26 12:43:49 +01:00
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0xe320f003, /* wfi */
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0xe5901000, /* ldr r1, [r0] */
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0xe1110001, /* tst r1, r1 */
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0x0afffffb, /* beq <wfi> */
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0xe12fff11, /* bx r1 */
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2013-12-17 20:42:29 +01:00
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MPCORE_PERIPHBASE /* privbase: MPCore peripheral base address. */
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2012-01-26 12:43:49 +01:00
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};
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for (n = 0; n < ARRAY_SIZE(smpboot); n++) {
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smpboot[n] = tswap32(smpboot[n]);
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}
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rom_add_blob_fixed("smpboot", smpboot, sizeof(smpboot), SMP_BOOT_ADDR);
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}
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2012-05-14 01:05:40 +02:00
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static void hb_reset_secondary(ARMCPU *cpu, const struct arm_boot_info *info)
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2012-01-26 12:43:49 +01:00
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{
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2012-05-14 01:05:40 +02:00
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CPUARMState *env = &cpu->env;
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2012-01-26 12:43:49 +01:00
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switch (info->nb_cpus) {
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case 4:
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Switch non-CPU callers from ld/st*_phys to address_space_ld/st*
Switch all the uses of ld/st*_phys to address_space_ld/st*,
except for those cases where the address space is the CPU's
(ie cs->as). This was done with the following script which
generates a Coccinelle patch.
A few over-80-columns lines in the result were rewrapped by
hand where Coccinelle failed to do the wrapping automatically,
as well as one location where it didn't put a line-continuation
'\' when wrapping lines on a change made to a match inside
a macro definition.
===begin===
#!/bin/sh -e
# Usage:
# ./ldst-phys.spatch.sh > ldst-phys.spatch
# spatch -sp_file ldst-phys.spatch -dir . | sed -e '/^+/s/\t/ /g' > out.patch
# patch -p1 < out.patch
for FN in ub uw_le uw_be l_le l_be q_le q_be uw l q; do
cat <<EOF
@ cpu_matches_ld_${FN} @
expression E1,E2;
identifier as;
@@
ld${FN}_phys(E1->as,E2)
@ other_matches_ld_${FN} depends on !cpu_matches_ld_${FN} @
expression E1,E2;
@@
-ld${FN}_phys(E1,E2)
+address_space_ld${FN}(E1,E2, MEMTXATTRS_UNSPECIFIED, NULL)
EOF
done
for FN in b w_le w_be l_le l_be q_le q_be w l q; do
cat <<EOF
@ cpu_matches_st_${FN} @
expression E1,E2,E3;
identifier as;
@@
st${FN}_phys(E1->as,E2,E3)
@ other_matches_st_${FN} depends on !cpu_matches_st_${FN} @
expression E1,E2,E3;
@@
-st${FN}_phys(E1,E2,E3)
+address_space_st${FN}(E1,E2,E3, MEMTXATTRS_UNSPECIFIED, NULL)
EOF
done
===endit===
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Reviewed-by: Edgar E. Iglesias <edgar.iglesias@xilinx.com>
Reviewed-by: Alex Bennée <alex.bennee@linaro.org>
2015-04-26 17:49:24 +02:00
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address_space_stl_notdirty(&address_space_memory,
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SMP_BOOT_REG + 0x30, 0,
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MEMTXATTRS_UNSPECIFIED, NULL);
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2012-01-26 12:43:49 +01:00
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case 3:
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Switch non-CPU callers from ld/st*_phys to address_space_ld/st*
Switch all the uses of ld/st*_phys to address_space_ld/st*,
except for those cases where the address space is the CPU's
(ie cs->as). This was done with the following script which
generates a Coccinelle patch.
A few over-80-columns lines in the result were rewrapped by
hand where Coccinelle failed to do the wrapping automatically,
as well as one location where it didn't put a line-continuation
'\' when wrapping lines on a change made to a match inside
a macro definition.
===begin===
#!/bin/sh -e
# Usage:
# ./ldst-phys.spatch.sh > ldst-phys.spatch
# spatch -sp_file ldst-phys.spatch -dir . | sed -e '/^+/s/\t/ /g' > out.patch
# patch -p1 < out.patch
for FN in ub uw_le uw_be l_le l_be q_le q_be uw l q; do
cat <<EOF
@ cpu_matches_ld_${FN} @
expression E1,E2;
identifier as;
@@
ld${FN}_phys(E1->as,E2)
@ other_matches_ld_${FN} depends on !cpu_matches_ld_${FN} @
expression E1,E2;
@@
-ld${FN}_phys(E1,E2)
+address_space_ld${FN}(E1,E2, MEMTXATTRS_UNSPECIFIED, NULL)
EOF
done
for FN in b w_le w_be l_le l_be q_le q_be w l q; do
cat <<EOF
@ cpu_matches_st_${FN} @
expression E1,E2,E3;
identifier as;
@@
st${FN}_phys(E1->as,E2,E3)
@ other_matches_st_${FN} depends on !cpu_matches_st_${FN} @
expression E1,E2,E3;
@@
-st${FN}_phys(E1,E2,E3)
+address_space_st${FN}(E1,E2,E3, MEMTXATTRS_UNSPECIFIED, NULL)
EOF
done
===endit===
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Reviewed-by: Edgar E. Iglesias <edgar.iglesias@xilinx.com>
Reviewed-by: Alex Bennée <alex.bennee@linaro.org>
2015-04-26 17:49:24 +02:00
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address_space_stl_notdirty(&address_space_memory,
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SMP_BOOT_REG + 0x20, 0,
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MEMTXATTRS_UNSPECIFIED, NULL);
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2012-01-26 12:43:49 +01:00
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case 2:
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Switch non-CPU callers from ld/st*_phys to address_space_ld/st*
Switch all the uses of ld/st*_phys to address_space_ld/st*,
except for those cases where the address space is the CPU's
(ie cs->as). This was done with the following script which
generates a Coccinelle patch.
A few over-80-columns lines in the result were rewrapped by
hand where Coccinelle failed to do the wrapping automatically,
as well as one location where it didn't put a line-continuation
'\' when wrapping lines on a change made to a match inside
a macro definition.
===begin===
#!/bin/sh -e
# Usage:
# ./ldst-phys.spatch.sh > ldst-phys.spatch
# spatch -sp_file ldst-phys.spatch -dir . | sed -e '/^+/s/\t/ /g' > out.patch
# patch -p1 < out.patch
for FN in ub uw_le uw_be l_le l_be q_le q_be uw l q; do
cat <<EOF
@ cpu_matches_ld_${FN} @
expression E1,E2;
identifier as;
@@
ld${FN}_phys(E1->as,E2)
@ other_matches_ld_${FN} depends on !cpu_matches_ld_${FN} @
expression E1,E2;
@@
-ld${FN}_phys(E1,E2)
+address_space_ld${FN}(E1,E2, MEMTXATTRS_UNSPECIFIED, NULL)
EOF
done
for FN in b w_le w_be l_le l_be q_le q_be w l q; do
cat <<EOF
@ cpu_matches_st_${FN} @
expression E1,E2,E3;
identifier as;
@@
st${FN}_phys(E1->as,E2,E3)
@ other_matches_st_${FN} depends on !cpu_matches_st_${FN} @
expression E1,E2,E3;
@@
-st${FN}_phys(E1,E2,E3)
+address_space_st${FN}(E1,E2,E3, MEMTXATTRS_UNSPECIFIED, NULL)
EOF
done
===endit===
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Reviewed-by: Edgar E. Iglesias <edgar.iglesias@xilinx.com>
Reviewed-by: Alex Bennée <alex.bennee@linaro.org>
2015-04-26 17:49:24 +02:00
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address_space_stl_notdirty(&address_space_memory,
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SMP_BOOT_REG + 0x10, 0,
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MEMTXATTRS_UNSPECIFIED, NULL);
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2012-01-26 12:43:49 +01:00
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env->regs[15] = SMP_BOOT_ADDR;
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break;
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default:
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break;
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}
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}
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#define NUM_REGS 0x200
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2012-10-23 12:30:10 +02:00
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static void hb_regs_write(void *opaque, hwaddr offset,
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2012-01-26 12:43:49 +01:00
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uint64_t value, unsigned size)
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{
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uint32_t *regs = opaque;
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if (offset == 0xf00) {
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if (value == 1 || value == 2) {
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qemu_system_reset_request();
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} else if (value == 3) {
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qemu_system_shutdown_request();
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}
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}
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regs[offset/4] = value;
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}
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2012-10-23 12:30:10 +02:00
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static uint64_t hb_regs_read(void *opaque, hwaddr offset,
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2012-01-26 12:43:49 +01:00
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unsigned size)
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{
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uint32_t *regs = opaque;
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uint32_t value = regs[offset/4];
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if ((offset == 0x100) || (offset == 0x108) || (offset == 0x10C)) {
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value |= 0x30000000;
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}
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return value;
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}
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static const MemoryRegionOps hb_mem_ops = {
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.read = hb_regs_read,
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.write = hb_regs_write,
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.endianness = DEVICE_NATIVE_ENDIAN,
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};
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2013-07-24 00:52:40 +02:00
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#define TYPE_HIGHBANK_REGISTERS "highbank-regs"
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#define HIGHBANK_REGISTERS(obj) \
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OBJECT_CHECK(HighbankRegsState, (obj), TYPE_HIGHBANK_REGISTERS)
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2012-01-26 12:43:49 +01:00
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typedef struct {
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2013-07-24 00:52:40 +02:00
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/*< private >*/
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SysBusDevice parent_obj;
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/*< public >*/
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2013-12-06 19:43:30 +01:00
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MemoryRegion iomem;
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2012-01-26 12:43:49 +01:00
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uint32_t regs[NUM_REGS];
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} HighbankRegsState;
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static VMStateDescription vmstate_highbank_regs = {
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.name = "highbank-regs",
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.version_id = 0,
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.minimum_version_id = 0,
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.fields = (VMStateField[]) {
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VMSTATE_UINT32_ARRAY(regs, HighbankRegsState, NUM_REGS),
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VMSTATE_END_OF_LIST(),
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},
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};
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static void highbank_regs_reset(DeviceState *dev)
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{
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2013-07-24 00:52:40 +02:00
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HighbankRegsState *s = HIGHBANK_REGISTERS(dev);
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2012-01-26 12:43:49 +01:00
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s->regs[0x40] = 0x05F20121;
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s->regs[0x41] = 0x2;
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s->regs[0x42] = 0x05F30121;
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s->regs[0x43] = 0x05F40121;
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}
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static int highbank_regs_init(SysBusDevice *dev)
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{
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2013-07-24 00:52:40 +02:00
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HighbankRegsState *s = HIGHBANK_REGISTERS(dev);
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2012-01-26 12:43:49 +01:00
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2013-12-06 19:43:30 +01:00
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memory_region_init_io(&s->iomem, OBJECT(s), &hb_mem_ops, s->regs,
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2013-06-07 03:25:08 +02:00
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"highbank_regs", 0x1000);
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2013-12-06 19:43:30 +01:00
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sysbus_init_mmio(dev, &s->iomem);
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2012-01-26 12:43:49 +01:00
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return 0;
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}
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2012-01-24 20:12:29 +01:00
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static void highbank_regs_class_init(ObjectClass *klass, void *data)
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{
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SysBusDeviceClass *sbc = SYS_BUS_DEVICE_CLASS(klass);
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2011-12-08 04:34:16 +01:00
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DeviceClass *dc = DEVICE_CLASS(klass);
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2012-01-24 20:12:29 +01:00
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sbc->init = highbank_regs_init;
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2011-12-08 04:34:16 +01:00
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dc->desc = "Calxeda Highbank registers";
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dc->vmsd = &vmstate_highbank_regs;
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dc->reset = highbank_regs_reset;
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2012-01-24 20:12:29 +01:00
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}
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2013-01-10 16:19:07 +01:00
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static const TypeInfo highbank_regs_info = {
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2013-07-24 00:52:40 +02:00
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.name = TYPE_HIGHBANK_REGISTERS,
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2011-12-08 04:34:16 +01:00
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.parent = TYPE_SYS_BUS_DEVICE,
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.instance_size = sizeof(HighbankRegsState),
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.class_init = highbank_regs_class_init,
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2012-01-26 12:43:49 +01:00
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};
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2012-02-09 15:20:55 +01:00
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static void highbank_regs_register_types(void)
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2012-01-26 12:43:49 +01:00
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{
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2011-12-08 04:34:16 +01:00
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type_register_static(&highbank_regs_info);
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2012-01-26 12:43:49 +01:00
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}
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2012-02-09 15:20:55 +01:00
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type_init(highbank_regs_register_types)
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2012-01-26 12:43:49 +01:00
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static struct arm_boot_info highbank_binfo;
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2013-07-05 14:21:36 +02:00
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enum cxmachines {
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CALXEDA_HIGHBANK,
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2013-07-05 14:21:37 +02:00
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CALXEDA_MIDWAY,
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2013-07-05 14:21:36 +02:00
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};
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2012-01-26 12:43:49 +01:00
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/* ram_size must be set to match the upper bound of memory in the
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* device tree (linux/arch/arm/boot/dts/highbank.dts), which is
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* normally 0xff900000 or -m 4089. When running this board on a
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* 32-bit host, set the reg value of memory to 0xf7ff00000 in the
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* device tree and pass -m 2047 to QEMU.
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*/
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2014-05-07 16:42:57 +02:00
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static void calxeda_init(MachineState *machine, enum cxmachines machine_id)
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2012-01-26 12:43:49 +01:00
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{
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2014-05-07 16:42:57 +02:00
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ram_addr_t ram_size = machine->ram_size;
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const char *cpu_model = machine->cpu_model;
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const char *kernel_filename = machine->kernel_filename;
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const char *kernel_cmdline = machine->kernel_cmdline;
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const char *initrd_filename = machine->initrd_filename;
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2013-07-05 14:21:36 +02:00
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DeviceState *dev = NULL;
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2012-01-26 12:43:49 +01:00
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SysBusDevice *busdev;
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qemu_irq pic[128];
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|
|
|
int n;
|
|
|
|
qemu_irq cpu_irq[4];
|
2015-05-12 12:57:19 +02:00
|
|
|
qemu_irq cpu_fiq[4];
|
2012-01-26 12:43:49 +01:00
|
|
|
MemoryRegion *sysram;
|
|
|
|
MemoryRegion *dram;
|
|
|
|
MemoryRegion *sysmem;
|
|
|
|
char *sysboot_filename;
|
|
|
|
|
|
|
|
if (!cpu_model) {
|
2014-05-07 16:42:57 +02:00
|
|
|
switch (machine_id) {
|
2013-07-05 14:21:36 +02:00
|
|
|
case CALXEDA_HIGHBANK:
|
|
|
|
cpu_model = "cortex-a9";
|
|
|
|
break;
|
2013-07-05 14:21:37 +02:00
|
|
|
case CALXEDA_MIDWAY:
|
|
|
|
cpu_model = "cortex-a15";
|
|
|
|
break;
|
2013-07-05 14:21:36 +02:00
|
|
|
}
|
2012-01-26 12:43:49 +01:00
|
|
|
}
|
|
|
|
|
|
|
|
for (n = 0; n < smp_cpus; n++) {
|
2013-12-17 20:42:28 +01:00
|
|
|
ObjectClass *oc = cpu_class_by_name(TYPE_ARM_CPU, cpu_model);
|
2014-04-04 18:42:34 +02:00
|
|
|
Object *cpuobj;
|
2012-04-20 09:39:15 +02:00
|
|
|
ARMCPU *cpu;
|
2013-12-17 20:42:28 +01:00
|
|
|
Error *err = NULL;
|
|
|
|
|
2014-04-04 18:42:33 +02:00
|
|
|
if (!oc) {
|
|
|
|
error_report("Unable to find CPU definition");
|
|
|
|
exit(1);
|
|
|
|
}
|
|
|
|
|
2014-04-04 18:42:34 +02:00
|
|
|
cpuobj = object_new(object_class_get_name(oc));
|
|
|
|
cpu = ARM_CPU(cpuobj);
|
2013-12-17 20:42:28 +01:00
|
|
|
|
2014-12-16 00:09:51 +01:00
|
|
|
/* By default A9 and A15 CPUs have EL3 enabled. This board does not
|
|
|
|
* currently support EL3 so the CPU EL3 property is disabled before
|
|
|
|
* realization.
|
|
|
|
*/
|
|
|
|
if (object_property_find(cpuobj, "has_el3", NULL)) {
|
|
|
|
object_property_set_bool(cpuobj, false, "has_el3", &err);
|
|
|
|
if (err) {
|
2015-02-12 13:55:05 +01:00
|
|
|
error_report_err(err);
|
2014-12-16 00:09:51 +01:00
|
|
|
exit(1);
|
|
|
|
}
|
|
|
|
}
|
|
|
|
|
2014-04-04 18:42:34 +02:00
|
|
|
if (object_property_find(cpuobj, "reset-cbar", NULL)) {
|
|
|
|
object_property_set_int(cpuobj, MPCORE_PERIPHBASE,
|
|
|
|
"reset-cbar", &error_abort);
|
2013-12-17 20:42:28 +01:00
|
|
|
}
|
2014-04-04 18:42:34 +02:00
|
|
|
object_property_set_bool(cpuobj, true, "realized", &err);
|
2013-12-17 20:42:28 +01:00
|
|
|
if (err) {
|
2015-02-12 13:55:05 +01:00
|
|
|
error_report_err(err);
|
2012-01-26 12:43:49 +01:00
|
|
|
exit(1);
|
|
|
|
}
|
2013-08-20 15:54:29 +02:00
|
|
|
cpu_irq[n] = qdev_get_gpio_in(DEVICE(cpu), ARM_CPU_IRQ);
|
2015-05-12 12:57:19 +02:00
|
|
|
cpu_fiq[n] = qdev_get_gpio_in(DEVICE(cpu), ARM_CPU_FIQ);
|
2012-01-26 12:43:49 +01:00
|
|
|
}
|
|
|
|
|
|
|
|
sysmem = get_system_memory();
|
|
|
|
dram = g_new(MemoryRegion, 1);
|
2015-04-04 14:24:38 +02:00
|
|
|
memory_region_allocate_system_memory(dram, NULL, "highbank.dram", ram_size);
|
2012-01-26 12:43:49 +01:00
|
|
|
/* SDRAM at address zero. */
|
|
|
|
memory_region_add_subregion(sysmem, 0, dram);
|
|
|
|
|
|
|
|
sysram = g_new(MemoryRegion, 1);
|
2014-09-09 07:27:55 +02:00
|
|
|
memory_region_init_ram(sysram, NULL, "highbank.sysram", 0x8000,
|
Fix bad error handling after memory_region_init_ram()
Symptom:
$ qemu-system-x86_64 -m 10000000
Unexpected error in ram_block_add() at /work/armbru/qemu/exec.c:1456:
upstream-qemu: cannot set up guest memory 'pc.ram': Cannot allocate memory
Aborted (core dumped)
Root cause: commit ef701d7 screwed up handling of out-of-memory
conditions. Before the commit, we report the error and exit(1), in
one place, ram_block_add(). The commit lifts the error handling up
the call chain some, to three places. Fine. Except it uses
&error_abort in these places, changing the behavior from exit(1) to
abort(), and thus undoing the work of commit 3922825 "exec: Don't
abort when we can't allocate guest memory".
The three places are:
* memory_region_init_ram()
Commit 4994653 (right after commit ef701d7) lifted the error
handling further, through memory_region_init_ram(), multiplying the
incorrect use of &error_abort. Later on, imitation of existing
(bad) code may have created more.
* memory_region_init_ram_ptr()
The &error_abort is still there.
* memory_region_init_rom_device()
Doesn't need fixing, because commit 33e0eb5 (soon after commit
ef701d7) lifted the error handling further, and in the process
changed it from &error_abort to passing it up the call chain.
Correct, because the callers are realize() methods.
Fix the error handling after memory_region_init_ram() with a
Coccinelle semantic patch:
@r@
expression mr, owner, name, size, err;
position p;
@@
memory_region_init_ram(mr, owner, name, size,
(
- &error_abort
+ &error_fatal
|
err@p
)
);
@script:python@
p << r.p;
@@
print "%s:%s:%s" % (p[0].file, p[0].line, p[0].column)
When the last argument is &error_abort, it gets replaced by
&error_fatal. This is the fix.
If the last argument is anything else, its position is reported. This
lets us check the fix is complete. Four positions get reported:
* ram_backend_memory_alloc()
Error is passed up the call chain, ultimately through
user_creatable_complete(). As far as I can tell, it's callers all
handle the error sanely.
* fsl_imx25_realize(), fsl_imx31_realize(), dp8393x_realize()
DeviceClass.realize() methods, errors handled sanely further up the
call chain.
We're good. Test case again behaves:
$ qemu-system-x86_64 -m 10000000
qemu-system-x86_64: cannot set up guest memory 'pc.ram': Cannot allocate memory
[Exit 1 ]
The next commits will repair the rest of commit ef701d7's damage.
Signed-off-by: Markus Armbruster <armbru@redhat.com>
Message-Id: <1441983105-26376-3-git-send-email-armbru@redhat.com>
Reviewed-by: Peter Crosthwaite <crosthwaite.peter@gmail.com>
2015-09-11 16:51:43 +02:00
|
|
|
&error_fatal);
|
2012-01-26 12:43:49 +01:00
|
|
|
memory_region_add_subregion(sysmem, 0xfff88000, sysram);
|
|
|
|
if (bios_name != NULL) {
|
|
|
|
sysboot_filename = qemu_find_file(QEMU_FILE_TYPE_BIOS, bios_name);
|
|
|
|
if (sysboot_filename != NULL) {
|
2015-04-01 18:57:29 +02:00
|
|
|
if (load_image_targphys(sysboot_filename, 0xfff88000, 0x8000) < 0) {
|
2012-01-26 12:43:49 +01:00
|
|
|
hw_error("Unable to load %s\n", bios_name);
|
|
|
|
}
|
2015-03-05 03:58:32 +01:00
|
|
|
g_free(sysboot_filename);
|
2012-01-26 12:43:49 +01:00
|
|
|
} else {
|
|
|
|
hw_error("Unable to find %s\n", bios_name);
|
|
|
|
}
|
|
|
|
}
|
|
|
|
|
2014-05-07 16:42:57 +02:00
|
|
|
switch (machine_id) {
|
2013-07-05 14:21:36 +02:00
|
|
|
case CALXEDA_HIGHBANK:
|
2013-07-05 14:21:37 +02:00
|
|
|
dev = qdev_create(NULL, "l2x0");
|
|
|
|
qdev_init_nofail(dev);
|
|
|
|
busdev = SYS_BUS_DEVICE(dev);
|
|
|
|
sysbus_mmio_map(busdev, 0, 0xfff12000);
|
|
|
|
|
2013-07-05 14:21:36 +02:00
|
|
|
dev = qdev_create(NULL, "a9mpcore_priv");
|
|
|
|
break;
|
2013-07-05 14:21:37 +02:00
|
|
|
case CALXEDA_MIDWAY:
|
|
|
|
dev = qdev_create(NULL, "a15mpcore_priv");
|
|
|
|
break;
|
2013-07-05 14:21:36 +02:00
|
|
|
}
|
2012-01-26 12:43:49 +01:00
|
|
|
qdev_prop_set_uint32(dev, "num-cpu", smp_cpus);
|
|
|
|
qdev_prop_set_uint32(dev, "num-irq", NIRQ_GIC);
|
|
|
|
qdev_init_nofail(dev);
|
2013-01-20 02:47:33 +01:00
|
|
|
busdev = SYS_BUS_DEVICE(dev);
|
2013-12-17 20:42:29 +01:00
|
|
|
sysbus_mmio_map(busdev, 0, MPCORE_PERIPHBASE);
|
2012-01-26 12:43:49 +01:00
|
|
|
for (n = 0; n < smp_cpus; n++) {
|
|
|
|
sysbus_connect_irq(busdev, n, cpu_irq[n]);
|
2015-05-12 12:57:19 +02:00
|
|
|
sysbus_connect_irq(busdev, n + smp_cpus, cpu_fiq[n]);
|
2012-01-26 12:43:49 +01:00
|
|
|
}
|
|
|
|
|
|
|
|
for (n = 0; n < 128; n++) {
|
|
|
|
pic[n] = qdev_get_gpio_in(dev, n);
|
|
|
|
}
|
|
|
|
|
|
|
|
dev = qdev_create(NULL, "sp804");
|
|
|
|
qdev_prop_set_uint32(dev, "freq0", 150000000);
|
|
|
|
qdev_prop_set_uint32(dev, "freq1", 150000000);
|
|
|
|
qdev_init_nofail(dev);
|
2013-01-20 02:47:33 +01:00
|
|
|
busdev = SYS_BUS_DEVICE(dev);
|
2012-01-26 12:43:49 +01:00
|
|
|
sysbus_mmio_map(busdev, 0, 0xfff34000);
|
|
|
|
sysbus_connect_irq(busdev, 0, pic[18]);
|
|
|
|
sysbus_create_simple("pl011", 0xfff36000, pic[20]);
|
|
|
|
|
|
|
|
dev = qdev_create(NULL, "highbank-regs");
|
|
|
|
qdev_init_nofail(dev);
|
2013-01-20 02:47:33 +01:00
|
|
|
busdev = SYS_BUS_DEVICE(dev);
|
2012-01-26 12:43:49 +01:00
|
|
|
sysbus_mmio_map(busdev, 0, 0xfff3c000);
|
|
|
|
|
|
|
|
sysbus_create_simple("pl061", 0xfff30000, pic[14]);
|
|
|
|
sysbus_create_simple("pl061", 0xfff31000, pic[15]);
|
|
|
|
sysbus_create_simple("pl061", 0xfff32000, pic[16]);
|
|
|
|
sysbus_create_simple("pl061", 0xfff33000, pic[17]);
|
|
|
|
sysbus_create_simple("pl031", 0xfff35000, pic[19]);
|
|
|
|
sysbus_create_simple("pl022", 0xfff39000, pic[23]);
|
|
|
|
|
|
|
|
sysbus_create_simple("sysbus-ahci", 0xffe08000, pic[83]);
|
|
|
|
|
2012-07-24 17:35:11 +02:00
|
|
|
if (nd_table[0].used) {
|
2012-01-26 12:43:49 +01:00
|
|
|
qemu_check_nic_model(&nd_table[0], "xgmac");
|
|
|
|
dev = qdev_create(NULL, "xgmac");
|
|
|
|
qdev_set_nic_properties(dev, &nd_table[0]);
|
|
|
|
qdev_init_nofail(dev);
|
2013-01-20 02:47:33 +01:00
|
|
|
sysbus_mmio_map(SYS_BUS_DEVICE(dev), 0, 0xfff50000);
|
|
|
|
sysbus_connect_irq(SYS_BUS_DEVICE(dev), 0, pic[77]);
|
|
|
|
sysbus_connect_irq(SYS_BUS_DEVICE(dev), 1, pic[78]);
|
|
|
|
sysbus_connect_irq(SYS_BUS_DEVICE(dev), 2, pic[79]);
|
2012-01-26 12:43:49 +01:00
|
|
|
|
|
|
|
qemu_check_nic_model(&nd_table[1], "xgmac");
|
|
|
|
dev = qdev_create(NULL, "xgmac");
|
|
|
|
qdev_set_nic_properties(dev, &nd_table[1]);
|
|
|
|
qdev_init_nofail(dev);
|
2013-01-20 02:47:33 +01:00
|
|
|
sysbus_mmio_map(SYS_BUS_DEVICE(dev), 0, 0xfff51000);
|
|
|
|
sysbus_connect_irq(SYS_BUS_DEVICE(dev), 0, pic[80]);
|
|
|
|
sysbus_connect_irq(SYS_BUS_DEVICE(dev), 1, pic[81]);
|
|
|
|
sysbus_connect_irq(SYS_BUS_DEVICE(dev), 2, pic[82]);
|
2012-01-26 12:43:49 +01:00
|
|
|
}
|
|
|
|
|
|
|
|
highbank_binfo.ram_size = ram_size;
|
|
|
|
highbank_binfo.kernel_filename = kernel_filename;
|
|
|
|
highbank_binfo.kernel_cmdline = kernel_cmdline;
|
|
|
|
highbank_binfo.initrd_filename = initrd_filename;
|
|
|
|
/* highbank requires a dtb in order to boot, and the dtb will override
|
|
|
|
* the board ID. The following value is ignored, so set it to -1 to be
|
|
|
|
* clear that the value is meaningless.
|
|
|
|
*/
|
|
|
|
highbank_binfo.board_id = -1;
|
|
|
|
highbank_binfo.nb_cpus = smp_cpus;
|
|
|
|
highbank_binfo.loader_start = 0;
|
|
|
|
highbank_binfo.write_secondary_boot = hb_write_secondary;
|
|
|
|
highbank_binfo.secondary_cpu_reset_hook = hb_reset_secondary;
|
2013-05-29 22:29:20 +02:00
|
|
|
arm_load_kernel(ARM_CPU(first_cpu), &highbank_binfo);
|
2012-01-26 12:43:49 +01:00
|
|
|
}
|
|
|
|
|
2014-05-07 16:42:57 +02:00
|
|
|
static void highbank_init(MachineState *machine)
|
2013-07-05 14:21:36 +02:00
|
|
|
{
|
2014-05-07 16:42:57 +02:00
|
|
|
calxeda_init(machine, CALXEDA_HIGHBANK);
|
2013-07-05 14:21:36 +02:00
|
|
|
}
|
|
|
|
|
2014-05-07 16:42:57 +02:00
|
|
|
static void midway_init(MachineState *machine)
|
2013-07-05 14:21:37 +02:00
|
|
|
{
|
2014-05-07 16:42:57 +02:00
|
|
|
calxeda_init(machine, CALXEDA_MIDWAY);
|
2013-07-05 14:21:37 +02:00
|
|
|
}
|
|
|
|
|
2015-09-04 20:37:08 +02:00
|
|
|
static void highbank_machine_init(MachineClass *mc)
|
|
|
|
{
|
|
|
|
mc->desc = "Calxeda Highbank (ECX-1000)";
|
|
|
|
mc->init = highbank_init;
|
|
|
|
mc->block_default_type = IF_SCSI;
|
|
|
|
mc->max_cpus = 4;
|
|
|
|
}
|
2012-01-26 12:43:49 +01:00
|
|
|
|
2015-09-04 20:37:08 +02:00
|
|
|
DEFINE_MACHINE("highbank", highbank_machine_init)
|
2013-07-05 14:21:37 +02:00
|
|
|
|
2015-09-04 20:37:08 +02:00
|
|
|
static void midway_machine_init(MachineClass *mc)
|
2012-01-26 12:43:49 +01:00
|
|
|
{
|
2015-09-04 20:37:08 +02:00
|
|
|
mc->desc = "Calxeda Midway (ECX-2000)";
|
|
|
|
mc->init = midway_init;
|
|
|
|
mc->block_default_type = IF_SCSI;
|
|
|
|
mc->max_cpus = 4;
|
2012-01-26 12:43:49 +01:00
|
|
|
}
|
|
|
|
|
2015-09-04 20:37:08 +02:00
|
|
|
DEFINE_MACHINE("midway", midway_machine_init)
|