2007-04-05 08:58:33 +02:00
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/*
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* Alpha emulation cpu helpers for qemu.
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2007-09-16 23:08:06 +02:00
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*
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2007-04-05 08:58:33 +02:00
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* Copyright (c) 2007 Jocelyn Mayer
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*
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* This library is free software; you can redistribute it and/or
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* modify it under the terms of the GNU Lesser General Public
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* License as published by the Free Software Foundation; either
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* version 2 of the License, or (at your option) any later version.
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*
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* This library is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
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* Lesser General Public License for more details.
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*
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* You should have received a copy of the GNU Lesser General Public
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2009-07-16 22:47:01 +02:00
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* License along with this library; if not, see <http://www.gnu.org/licenses/>.
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2007-04-05 08:58:33 +02:00
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*/
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2016-01-26 19:17:04 +01:00
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#include "qemu/osdep.h"
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2007-04-05 08:58:33 +02:00
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#include "cpu.h"
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2016-03-15 13:18:37 +01:00
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#include "exec/exec-all.h"
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2019-08-08 18:30:35 +02:00
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#include "fpu/softfloat-types.h"
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2014-04-08 07:31:41 +02:00
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#include "exec/helper-proto.h"
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2019-04-17 21:18:02 +02:00
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#include "qemu/qemu-print.h"
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2009-12-10 00:56:29 +01:00
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2009-12-31 21:41:07 +01:00
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2014-08-09 00:17:07 +02:00
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#define CONVERT_BIT(X, SRC, DST) \
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(SRC > DST ? (X) / (SRC / DST) & (DST) : ((X) & SRC) * (DST / SRC))
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2009-12-31 21:41:07 +01:00
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2019-04-27 00:20:51 +02:00
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uint64_t cpu_alpha_load_fpcr(CPUAlphaState *env)
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2014-08-09 00:17:07 +02:00
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{
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return (uint64_t)env->fpcr << 32;
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2009-12-10 00:56:29 +01:00
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}
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2019-04-27 00:20:51 +02:00
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void cpu_alpha_store_fpcr(CPUAlphaState *env, uint64_t val)
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2009-12-10 00:56:29 +01:00
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{
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2014-08-09 00:17:07 +02:00
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uint32_t fpcr = val >> 32;
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uint32_t t = 0;
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2009-12-31 21:41:07 +01:00
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2014-08-09 00:17:07 +02:00
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t |= CONVERT_BIT(fpcr, FPCR_INED, FPCR_INE);
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t |= CONVERT_BIT(fpcr, FPCR_UNFD, FPCR_UNF);
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t |= CONVERT_BIT(fpcr, FPCR_OVFD, FPCR_OVF);
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t |= CONVERT_BIT(fpcr, FPCR_DZED, FPCR_DZE);
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t |= CONVERT_BIT(fpcr, FPCR_INVD, FPCR_INV);
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2009-12-31 21:41:07 +01:00
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2014-08-09 00:17:07 +02:00
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env->fpcr = fpcr;
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env->fpcr_exc_enable = ~t & FPCR_STATUS_MASK;
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2009-12-31 21:41:07 +01:00
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2014-08-09 00:17:07 +02:00
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switch (fpcr & FPCR_DYN_MASK) {
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case FPCR_DYN_NORMAL:
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default:
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t = float_round_nearest_even;
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break;
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2009-12-31 21:41:07 +01:00
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case FPCR_DYN_CHOPPED:
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t = float_round_to_zero;
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2009-12-10 00:56:29 +01:00
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break;
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2009-12-31 21:41:07 +01:00
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case FPCR_DYN_MINUS:
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t = float_round_down;
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2009-12-10 00:56:29 +01:00
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break;
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2009-12-31 21:41:07 +01:00
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case FPCR_DYN_PLUS:
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t = float_round_up;
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2009-12-10 00:56:29 +01:00
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break;
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}
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2009-12-31 21:41:07 +01:00
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env->fpcr_dyn_round = t;
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2014-08-09 00:17:07 +02:00
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env->fpcr_flush_to_zero = (fpcr & FPCR_UNFD) && (fpcr & FPCR_UNDZ);
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env->fp_status.flush_inputs_to_zero = (fpcr & FPCR_DNZ) != 0;
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2019-04-27 00:20:51 +02:00
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#ifdef CONFIG_USER_ONLY
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/*
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* Override some of these bits with the contents of ENV->SWCR.
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* In system mode, some of these would trap to the kernel, at
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* which point the kernel's handler would emulate and apply
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* the software exception mask.
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*/
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if (env->swcr & SWCR_MAP_DMZ) {
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env->fp_status.flush_inputs_to_zero = 1;
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}
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if (env->swcr & SWCR_MAP_UMZ) {
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env->fp_status.flush_to_zero = 1;
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}
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env->fpcr_exc_enable &= ~(alpha_ieee_swcr_to_fpcr(env->swcr) >> 32);
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#endif
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2009-12-10 00:56:29 +01:00
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}
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2007-04-05 08:58:33 +02:00
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2012-03-24 17:51:10 +01:00
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uint64_t helper_load_fpcr(CPUAlphaState *env)
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{
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return cpu_alpha_load_fpcr(env);
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}
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void helper_store_fpcr(CPUAlphaState *env, uint64_t val)
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{
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cpu_alpha_store_fpcr(env, val);
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}
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2014-09-16 21:16:38 +02:00
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static uint64_t *cpu_alpha_addr_gr(CPUAlphaState *env, unsigned reg)
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{
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#ifndef CONFIG_USER_ONLY
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2017-07-06 21:45:07 +02:00
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if (env->flags & ENV_FLAG_PAL_MODE) {
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2014-09-16 21:16:38 +02:00
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if (reg >= 8 && reg <= 14) {
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return &env->shadow[reg - 8];
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} else if (reg == 25) {
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return &env->shadow[7];
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}
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}
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#endif
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return &env->ir[reg];
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}
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uint64_t cpu_alpha_load_gr(CPUAlphaState *env, unsigned reg)
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{
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return *cpu_alpha_addr_gr(env, reg);
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}
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void cpu_alpha_store_gr(CPUAlphaState *env, unsigned reg, uint64_t val)
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{
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*cpu_alpha_addr_gr(env, reg) = val;
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}
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2007-09-16 23:08:06 +02:00
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#if defined(CONFIG_USER_ONLY)
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2019-04-02 09:51:11 +02:00
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bool alpha_cpu_tlb_fill(CPUState *cs, vaddr address, int size,
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MMUAccessType access_type, int mmu_idx,
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bool probe, uintptr_t retaddr)
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2007-04-05 08:58:33 +02:00
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{
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2013-08-26 03:01:33 +02:00
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AlphaCPU *cpu = ALPHA_CPU(cs);
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2013-08-26 08:31:06 +02:00
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cs->exception_index = EXCP_MMFAULT;
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2013-08-26 03:01:33 +02:00
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cpu->env.trap_arg0 = address;
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2019-04-02 09:51:11 +02:00
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cpu_loop_exit_restore(cs, retaddr);
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2007-04-05 08:58:33 +02:00
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}
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#else
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2011-04-19 00:59:21 +02:00
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/* Returns the OSF/1 entMM failure indication, or -1 on success. */
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2012-03-14 01:38:21 +01:00
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static int get_physical_address(CPUAlphaState *env, target_ulong addr,
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2011-04-19 00:59:21 +02:00
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int prot_need, int mmu_idx,
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target_ulong *pphys, int *pprot)
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2007-04-05 08:58:33 +02:00
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{
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2019-03-23 01:26:58 +01:00
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CPUState *cs = env_cpu(env);
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2011-04-19 00:59:21 +02:00
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target_long saddr = addr;
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target_ulong phys = 0;
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target_ulong L1pte, L2pte, L3pte;
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target_ulong pt, index;
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int prot = 0;
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int ret = MM_K_ACV;
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|
2016-09-03 20:32:35 +02:00
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/* Handle physical accesses. */
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if (mmu_idx == MMU_PHYS_IDX) {
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phys = addr;
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prot = PAGE_READ | PAGE_WRITE | PAGE_EXEC;
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ret = -1;
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goto exit;
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}
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2011-04-19 00:59:21 +02:00
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/* Ensure that the virtual address is properly sign-extended from
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the last implemented virtual address bit. */
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if (saddr >> TARGET_VIRT_ADDR_SPACE_BITS != saddr >> 63) {
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goto exit;
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}
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/* Translate the superpage. */
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/* ??? When we do more than emulate Unix PALcode, we'll need to
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2011-04-27 18:22:18 +02:00
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determine which KSEG is actually active. */
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if (saddr < 0 && ((saddr >> 41) & 3) == 2) {
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/* User-space cannot access KSEG addresses. */
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2011-04-19 00:59:21 +02:00
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if (mmu_idx != MMU_KERNEL_IDX) {
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goto exit;
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}
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|
2011-04-27 18:22:18 +02:00
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/* For the benefit of the Typhoon chipset, move bit 40 to bit 43.
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We would not do this if the 48-bit KSEG is enabled. */
|
2011-04-19 00:59:21 +02:00
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phys = saddr & ((1ull << 40) - 1);
|
2011-04-27 18:22:18 +02:00
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phys |= (saddr & (1ull << 40)) << 3;
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|
2011-04-19 00:59:21 +02:00
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prot = PAGE_READ | PAGE_WRITE | PAGE_EXEC;
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ret = -1;
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goto exit;
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}
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/* Interpret the page table exactly like PALcode does. */
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pt = env->ptbr;
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|
2017-08-08 14:42:52 +02:00
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|
/* TODO: rather than using ldq_phys() to read the page table we should
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|
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* use address_space_ldq() so that we can handle the case when
|
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* the page table read gives a bus fault, rather than ignoring it.
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* For the existing code the zero data that ldq_phys will return for
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|
|
* an access to invalid memory will result in our treating the page
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* table as invalid, which may even be the right behaviour.
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*/
|
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|
2011-04-19 00:59:21 +02:00
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/* L1 page table read. */
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index = (addr >> (TARGET_PAGE_BITS + 20)) & 0x3ff;
|
2013-12-17 05:05:40 +01:00
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|
L1pte = ldq_phys(cs->as, pt + index*8);
|
2011-04-19 00:59:21 +02:00
|
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|
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if (unlikely((L1pte & PTE_VALID) == 0)) {
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|
ret = MM_K_TNV;
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goto exit;
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}
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|
if (unlikely((L1pte & PTE_KRE) == 0)) {
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goto exit;
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}
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pt = L1pte >> 32 << TARGET_PAGE_BITS;
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|
|
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/* L2 page table read. */
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index = (addr >> (TARGET_PAGE_BITS + 10)) & 0x3ff;
|
2013-12-17 05:05:40 +01:00
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L2pte = ldq_phys(cs->as, pt + index*8);
|
2011-04-19 00:59:21 +02:00
|
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if (unlikely((L2pte & PTE_VALID) == 0)) {
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ret = MM_K_TNV;
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goto exit;
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}
|
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if (unlikely((L2pte & PTE_KRE) == 0)) {
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goto exit;
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}
|
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pt = L2pte >> 32 << TARGET_PAGE_BITS;
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|
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/* L3 page table read. */
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index = (addr >> TARGET_PAGE_BITS) & 0x3ff;
|
2013-12-17 05:05:40 +01:00
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L3pte = ldq_phys(cs->as, pt + index*8);
|
2011-04-19 00:59:21 +02:00
|
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phys = L3pte >> 32 << TARGET_PAGE_BITS;
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if (unlikely((L3pte & PTE_VALID) == 0)) {
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ret = MM_K_TNV;
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goto exit;
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}
|
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#if PAGE_READ != 1 || PAGE_WRITE != 2 || PAGE_EXEC != 4
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# error page bits out of date
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#endif
|
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|
|
|
|
|
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/* Check access violations. */
|
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|
|
if (L3pte & (PTE_KRE << mmu_idx)) {
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prot |= PAGE_READ | PAGE_EXEC;
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}
|
|
|
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if (L3pte & (PTE_KWE << mmu_idx)) {
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|
prot |= PAGE_WRITE;
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|
}
|
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|
|
if (unlikely((prot & prot_need) == 0 && prot_need)) {
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|
goto exit;
|
|
|
|
}
|
|
|
|
|
|
|
|
/* Check fault-on-operation violations. */
|
|
|
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prot &= ~(L3pte >> 1);
|
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|
|
ret = -1;
|
|
|
|
if (unlikely((prot & prot_need) == 0)) {
|
|
|
|
ret = (prot_need & PAGE_EXEC ? MM_K_FOE :
|
|
|
|
prot_need & PAGE_WRITE ? MM_K_FOW :
|
|
|
|
prot_need & PAGE_READ ? MM_K_FOR : -1);
|
|
|
|
}
|
|
|
|
|
|
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|
exit:
|
|
|
|
*pphys = phys;
|
|
|
|
*pprot = prot;
|
|
|
|
return ret;
|
2007-04-05 08:58:33 +02:00
|
|
|
}
|
|
|
|
|
2013-06-29 18:55:54 +02:00
|
|
|
hwaddr alpha_cpu_get_phys_page_debug(CPUState *cs, vaddr addr)
|
2007-04-05 08:58:33 +02:00
|
|
|
{
|
2013-06-29 18:55:54 +02:00
|
|
|
AlphaCPU *cpu = ALPHA_CPU(cs);
|
2011-04-19 00:59:21 +02:00
|
|
|
target_ulong phys;
|
|
|
|
int prot, fail;
|
|
|
|
|
2013-06-29 18:55:54 +02:00
|
|
|
fail = get_physical_address(&cpu->env, addr, 0, 0, &phys, &prot);
|
2011-04-19 00:59:21 +02:00
|
|
|
return (fail >= 0 ? -1 : phys);
|
|
|
|
}
|
|
|
|
|
2019-04-02 09:51:11 +02:00
|
|
|
bool alpha_cpu_tlb_fill(CPUState *cs, vaddr addr, int size,
|
|
|
|
MMUAccessType access_type, int mmu_idx,
|
|
|
|
bool probe, uintptr_t retaddr)
|
2011-04-19 00:59:21 +02:00
|
|
|
{
|
2013-08-26 03:01:33 +02:00
|
|
|
AlphaCPU *cpu = ALPHA_CPU(cs);
|
|
|
|
CPUAlphaState *env = &cpu->env;
|
2011-04-19 00:59:21 +02:00
|
|
|
target_ulong phys;
|
|
|
|
int prot, fail;
|
|
|
|
|
2019-04-02 09:51:11 +02:00
|
|
|
fail = get_physical_address(env, addr, 1 << access_type,
|
|
|
|
mmu_idx, &phys, &prot);
|
2011-04-19 00:59:21 +02:00
|
|
|
if (unlikely(fail >= 0)) {
|
2019-04-02 09:51:11 +02:00
|
|
|
if (probe) {
|
|
|
|
return false;
|
|
|
|
}
|
2013-08-26 08:31:06 +02:00
|
|
|
cs->exception_index = EXCP_MMFAULT;
|
2011-04-19 00:59:21 +02:00
|
|
|
env->trap_arg0 = addr;
|
|
|
|
env->trap_arg1 = fail;
|
2019-08-22 19:45:14 +02:00
|
|
|
env->trap_arg2 = (access_type == MMU_DATA_LOAD ? 0ull :
|
|
|
|
access_type == MMU_DATA_STORE ? 1ull :
|
|
|
|
/* access_type == MMU_INST_FETCH */ -1ull);
|
2019-04-02 09:51:11 +02:00
|
|
|
cpu_loop_exit_restore(cs, retaddr);
|
2011-04-19 00:59:21 +02:00
|
|
|
}
|
|
|
|
|
2013-09-03 13:59:37 +02:00
|
|
|
tlb_set_page(cs, addr & TARGET_PAGE_MASK, phys & TARGET_PAGE_MASK,
|
2011-04-19 00:59:21 +02:00
|
|
|
prot, mmu_idx, TARGET_PAGE_SIZE);
|
2019-04-02 09:51:11 +02:00
|
|
|
return true;
|
|
|
|
}
|
2011-04-18 23:05:35 +02:00
|
|
|
#endif /* USER_ONLY */
|
2007-04-05 08:58:33 +02:00
|
|
|
|
2013-02-02 10:57:51 +01:00
|
|
|
void alpha_cpu_do_interrupt(CPUState *cs)
|
2007-04-05 08:58:33 +02:00
|
|
|
{
|
2013-02-02 10:57:51 +01:00
|
|
|
AlphaCPU *cpu = ALPHA_CPU(cs);
|
|
|
|
CPUAlphaState *env = &cpu->env;
|
2013-08-26 08:31:06 +02:00
|
|
|
int i = cs->exception_index;
|
2011-04-18 23:05:35 +02:00
|
|
|
|
|
|
|
if (qemu_loglevel_mask(CPU_LOG_INT)) {
|
|
|
|
static int count;
|
|
|
|
const char *name = "<unknown>";
|
|
|
|
|
|
|
|
switch (i) {
|
|
|
|
case EXCP_RESET:
|
|
|
|
name = "reset";
|
|
|
|
break;
|
|
|
|
case EXCP_MCHK:
|
|
|
|
name = "mchk";
|
|
|
|
break;
|
|
|
|
case EXCP_SMP_INTERRUPT:
|
|
|
|
name = "smp_interrupt";
|
|
|
|
break;
|
|
|
|
case EXCP_CLK_INTERRUPT:
|
|
|
|
name = "clk_interrupt";
|
|
|
|
break;
|
|
|
|
case EXCP_DEV_INTERRUPT:
|
|
|
|
name = "dev_interrupt";
|
|
|
|
break;
|
|
|
|
case EXCP_MMFAULT:
|
|
|
|
name = "mmfault";
|
|
|
|
break;
|
|
|
|
case EXCP_UNALIGN:
|
|
|
|
name = "unalign";
|
|
|
|
break;
|
|
|
|
case EXCP_OPCDEC:
|
|
|
|
name = "opcdec";
|
|
|
|
break;
|
|
|
|
case EXCP_ARITH:
|
|
|
|
name = "arith";
|
|
|
|
break;
|
|
|
|
case EXCP_FEN:
|
|
|
|
name = "fen";
|
|
|
|
break;
|
|
|
|
case EXCP_CALL_PAL:
|
|
|
|
name = "call_pal";
|
|
|
|
break;
|
|
|
|
}
|
2016-11-13 19:41:13 +01:00
|
|
|
qemu_log("INT %6d: %s(%#x) cpu=%d pc=%016"
|
|
|
|
PRIx64 " sp=%016" PRIx64 "\n",
|
|
|
|
++count, name, env->error_code, cs->cpu_index,
|
|
|
|
env->pc, env->ir[IR_SP]);
|
2011-04-18 23:05:35 +02:00
|
|
|
}
|
|
|
|
|
2013-08-26 08:31:06 +02:00
|
|
|
cs->exception_index = -1;
|
2011-04-18 23:05:35 +02:00
|
|
|
|
|
|
|
#if !defined(CONFIG_USER_ONLY)
|
|
|
|
switch (i) {
|
|
|
|
case EXCP_RESET:
|
|
|
|
i = 0x0000;
|
|
|
|
break;
|
|
|
|
case EXCP_MCHK:
|
|
|
|
i = 0x0080;
|
|
|
|
break;
|
|
|
|
case EXCP_SMP_INTERRUPT:
|
|
|
|
i = 0x0100;
|
|
|
|
break;
|
|
|
|
case EXCP_CLK_INTERRUPT:
|
|
|
|
i = 0x0180;
|
|
|
|
break;
|
|
|
|
case EXCP_DEV_INTERRUPT:
|
|
|
|
i = 0x0200;
|
|
|
|
break;
|
|
|
|
case EXCP_MMFAULT:
|
|
|
|
i = 0x0280;
|
|
|
|
break;
|
|
|
|
case EXCP_UNALIGN:
|
|
|
|
i = 0x0300;
|
|
|
|
break;
|
|
|
|
case EXCP_OPCDEC:
|
|
|
|
i = 0x0380;
|
|
|
|
break;
|
|
|
|
case EXCP_ARITH:
|
|
|
|
i = 0x0400;
|
|
|
|
break;
|
|
|
|
case EXCP_FEN:
|
|
|
|
i = 0x0480;
|
|
|
|
break;
|
|
|
|
case EXCP_CALL_PAL:
|
|
|
|
i = env->error_code;
|
|
|
|
/* There are 64 entry points for both privileged and unprivileged,
|
|
|
|
with bit 0x80 indicating unprivileged. Each entry point gets
|
|
|
|
64 bytes to do its job. */
|
|
|
|
if (i & 0x80) {
|
|
|
|
i = 0x2000 + (i - 0x80) * 64;
|
|
|
|
} else {
|
|
|
|
i = 0x1000 + i * 64;
|
|
|
|
}
|
|
|
|
break;
|
|
|
|
default:
|
2013-09-03 17:38:47 +02:00
|
|
|
cpu_abort(cs, "Unhandled CPU exception");
|
2011-04-18 23:05:35 +02:00
|
|
|
}
|
|
|
|
|
|
|
|
/* Remember where the exception happened. Emulate real hardware in
|
|
|
|
that the low bit of the PC indicates PALmode. */
|
2017-07-06 21:45:07 +02:00
|
|
|
env->exc_addr = env->pc | (env->flags & ENV_FLAG_PAL_MODE);
|
2011-04-18 23:05:35 +02:00
|
|
|
|
|
|
|
/* Continue execution at the PALcode entry point. */
|
|
|
|
env->pc = env->palbr + i;
|
|
|
|
|
|
|
|
/* Switch to PALmode. */
|
2017-07-06 21:45:07 +02:00
|
|
|
env->flags |= ENV_FLAG_PAL_MODE;
|
2011-04-18 23:05:35 +02:00
|
|
|
#endif /* !USER_ONLY */
|
2007-04-05 08:58:33 +02:00
|
|
|
}
|
|
|
|
|
2014-09-13 18:45:22 +02:00
|
|
|
bool alpha_cpu_exec_interrupt(CPUState *cs, int interrupt_request)
|
|
|
|
{
|
|
|
|
AlphaCPU *cpu = ALPHA_CPU(cs);
|
|
|
|
CPUAlphaState *env = &cpu->env;
|
|
|
|
int idx = -1;
|
|
|
|
|
|
|
|
/* We never take interrupts while in PALmode. */
|
2017-07-06 21:45:07 +02:00
|
|
|
if (env->flags & ENV_FLAG_PAL_MODE) {
|
2014-09-13 18:45:22 +02:00
|
|
|
return false;
|
|
|
|
}
|
|
|
|
|
|
|
|
/* Fall through the switch, collecting the highest priority
|
|
|
|
interrupt that isn't masked by the processor status IPL. */
|
|
|
|
/* ??? This hard-codes the OSF/1 interrupt levels. */
|
2017-07-06 21:45:07 +02:00
|
|
|
switch ((env->flags >> ENV_FLAG_PS_SHIFT) & PS_INT_MASK) {
|
2014-09-13 18:45:22 +02:00
|
|
|
case 0 ... 3:
|
|
|
|
if (interrupt_request & CPU_INTERRUPT_HARD) {
|
|
|
|
idx = EXCP_DEV_INTERRUPT;
|
|
|
|
}
|
|
|
|
/* FALLTHRU */
|
|
|
|
case 4:
|
|
|
|
if (interrupt_request & CPU_INTERRUPT_TIMER) {
|
|
|
|
idx = EXCP_CLK_INTERRUPT;
|
|
|
|
}
|
|
|
|
/* FALLTHRU */
|
|
|
|
case 5:
|
|
|
|
if (interrupt_request & CPU_INTERRUPT_SMP) {
|
|
|
|
idx = EXCP_SMP_INTERRUPT;
|
|
|
|
}
|
|
|
|
/* FALLTHRU */
|
|
|
|
case 6:
|
|
|
|
if (interrupt_request & CPU_INTERRUPT_MCHK) {
|
|
|
|
idx = EXCP_MCHK;
|
|
|
|
}
|
|
|
|
}
|
|
|
|
if (idx >= 0) {
|
|
|
|
cs->exception_index = idx;
|
|
|
|
env->error_code = 0;
|
|
|
|
alpha_cpu_do_interrupt(cs);
|
|
|
|
return true;
|
|
|
|
}
|
|
|
|
return false;
|
|
|
|
}
|
|
|
|
|
2019-04-17 21:18:02 +02:00
|
|
|
void alpha_cpu_dump_state(CPUState *cs, FILE *f, int flags)
|
2007-04-05 08:58:33 +02:00
|
|
|
{
|
2019-04-26 22:33:13 +02:00
|
|
|
static const char linux_reg_names[31][4] = {
|
|
|
|
"v0", "t0", "t1", "t2", "t3", "t4", "t5", "t6",
|
|
|
|
"t7", "s0", "s1", "s2", "s3", "s4", "s5", "fp",
|
|
|
|
"a0", "a1", "a2", "a3", "a4", "a5", "t8", "t9",
|
|
|
|
"t10", "t11", "ra", "t12", "at", "gp", "sp"
|
2007-04-05 08:58:33 +02:00
|
|
|
};
|
2013-05-27 01:33:50 +02:00
|
|
|
AlphaCPU *cpu = ALPHA_CPU(cs);
|
|
|
|
CPUAlphaState *env = &cpu->env;
|
2007-04-05 08:58:33 +02:00
|
|
|
int i;
|
|
|
|
|
2019-04-26 22:33:13 +02:00
|
|
|
qemu_fprintf(f, "PC " TARGET_FMT_lx " PS %02x\n",
|
2019-04-17 21:18:02 +02:00
|
|
|
env->pc, extract32(env->flags, ENV_FLAG_PS_SHIFT, 8));
|
2007-04-05 08:58:33 +02:00
|
|
|
for (i = 0; i < 31; i++) {
|
2019-04-26 22:33:13 +02:00
|
|
|
qemu_fprintf(f, "%-8s" TARGET_FMT_lx "%c",
|
2019-04-17 21:18:02 +02:00
|
|
|
linux_reg_names[i], cpu_alpha_load_gr(env, i),
|
|
|
|
(i % 3) == 2 ? '\n' : ' ');
|
2007-04-05 08:58:33 +02:00
|
|
|
}
|
2010-04-08 00:42:26 +02:00
|
|
|
|
2019-04-26 22:33:13 +02:00
|
|
|
qemu_fprintf(f, "lock_a " TARGET_FMT_lx " lock_v " TARGET_FMT_lx "\n",
|
2019-04-17 21:18:02 +02:00
|
|
|
env->lock_addr, env->lock_value);
|
2010-04-08 00:42:26 +02:00
|
|
|
|
2018-05-11 05:01:46 +02:00
|
|
|
if (flags & CPU_DUMP_FPU) {
|
|
|
|
for (i = 0; i < 31; i++) {
|
2019-04-26 22:33:13 +02:00
|
|
|
qemu_fprintf(f, "f%-7d%016" PRIx64 "%c", i, env->fir[i],
|
2019-04-17 21:18:02 +02:00
|
|
|
(i % 3) == 2 ? '\n' : ' ');
|
2018-05-11 05:01:46 +02:00
|
|
|
}
|
2019-04-26 22:33:13 +02:00
|
|
|
qemu_fprintf(f, "fpcr %016" PRIx64 "\n", cpu_alpha_load_fpcr(env));
|
2007-04-05 08:58:33 +02:00
|
|
|
}
|
2019-04-17 21:18:02 +02:00
|
|
|
qemu_fprintf(f, "\n");
|
2007-04-05 08:58:33 +02:00
|
|
|
}
|
2012-03-24 17:51:08 +01:00
|
|
|
|
|
|
|
/* This should only be called from translate, via gen_excp.
|
|
|
|
We expect that ENV->PC has already been updated. */
|
|
|
|
void QEMU_NORETURN helper_excp(CPUAlphaState *env, int excp, int error)
|
|
|
|
{
|
2019-03-23 01:26:58 +01:00
|
|
|
CPUState *cs = env_cpu(env);
|
2013-08-26 08:31:06 +02:00
|
|
|
|
|
|
|
cs->exception_index = excp;
|
2012-03-24 17:51:08 +01:00
|
|
|
env->error_code = error;
|
2013-08-27 17:52:12 +02:00
|
|
|
cpu_loop_exit(cs);
|
2012-03-24 17:51:08 +01:00
|
|
|
}
|
|
|
|
|
|
|
|
/* This may be called from any of the helpers to set up EXCEPTION_INDEX. */
|
2012-04-09 16:20:20 +02:00
|
|
|
void QEMU_NORETURN dynamic_excp(CPUAlphaState *env, uintptr_t retaddr,
|
2012-03-24 17:51:08 +01:00
|
|
|
int excp, int error)
|
|
|
|
{
|
2019-03-23 01:26:58 +01:00
|
|
|
CPUState *cs = env_cpu(env);
|
2013-08-26 08:31:06 +02:00
|
|
|
|
|
|
|
cs->exception_index = excp;
|
2012-03-24 17:51:08 +01:00
|
|
|
env->error_code = error;
|
2012-12-04 21:16:07 +01:00
|
|
|
if (retaddr) {
|
2018-04-09 11:13:20 +02:00
|
|
|
cpu_restore_state(cs, retaddr, true);
|
2014-06-28 22:06:19 +02:00
|
|
|
/* Floating-point exceptions (our only users) point to the next PC. */
|
|
|
|
env->pc += 4;
|
2012-12-04 21:16:07 +01:00
|
|
|
}
|
2013-08-27 17:52:12 +02:00
|
|
|
cpu_loop_exit(cs);
|
2012-03-24 17:51:08 +01:00
|
|
|
}
|
|
|
|
|
2012-04-09 16:20:20 +02:00
|
|
|
void QEMU_NORETURN arith_excp(CPUAlphaState *env, uintptr_t retaddr,
|
2012-03-24 17:51:08 +01:00
|
|
|
int exc, uint64_t mask)
|
|
|
|
{
|
|
|
|
env->trap_arg0 = exc;
|
|
|
|
env->trap_arg1 = mask;
|
|
|
|
dynamic_excp(env, retaddr, EXCP_ARITH, 0);
|
|
|
|
}
|