2018-05-22 18:50:55 +02:00
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/*
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* QEMU PCI bochs display adapter.
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*
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* This work is licensed under the terms of the GNU GPL, version 2 or later.
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* See the COPYING file in the top-level directory.
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*/
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2019-05-23 16:35:07 +02:00
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2018-05-22 18:50:55 +02:00
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#include "qemu/osdep.h"
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2019-05-23 16:35:07 +02:00
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#include "qemu/module.h"
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2018-06-25 14:42:06 +02:00
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#include "qemu/units.h"
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2022-12-22 11:03:28 +01:00
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#include "hw/pci/pci_device.h"
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2019-08-12 07:23:51 +02:00
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#include "hw/qdev-properties.h"
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2019-08-12 07:23:45 +02:00
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#include "migration/vmstate.h"
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2018-05-22 18:50:55 +02:00
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#include "hw/display/bochs-vbe.h"
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2018-10-05 18:01:47 +02:00
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#include "hw/display/edid.h"
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2018-05-22 18:50:55 +02:00
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#include "qapi/error.h"
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#include "ui/console.h"
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#include "ui/qemu-pixman.h"
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2020-09-03 22:43:22 +02:00
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#include "qom/object.h"
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2018-05-22 18:50:55 +02:00
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typedef struct BochsDisplayMode {
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pixman_format_code_t format;
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uint32_t bytepp;
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uint32_t width;
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uint32_t height;
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uint32_t stride;
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uint64_t offset;
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uint64_t size;
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} BochsDisplayMode;
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2020-09-03 22:43:22 +02:00
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struct BochsDisplayState {
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2018-05-22 18:50:55 +02:00
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/* parent */
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PCIDevice pci;
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/* device elements */
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QemuConsole *con;
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MemoryRegion vram;
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MemoryRegion mmio;
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MemoryRegion vbe;
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MemoryRegion qext;
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2018-10-05 18:01:47 +02:00
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MemoryRegion edid;
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2018-05-22 18:50:55 +02:00
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/* device config */
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uint64_t vgamem;
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2018-10-05 18:01:47 +02:00
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bool enable_edid;
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qemu_edid_info edid_info;
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uint8_t edid_blob[256];
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2018-05-22 18:50:55 +02:00
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/* device registers */
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uint16_t vbe_regs[VBE_DISPI_INDEX_NB];
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bool big_endian_fb;
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/* device state */
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BochsDisplayMode mode;
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2020-09-03 22:43:22 +02:00
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};
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2018-05-22 18:50:55 +02:00
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#define TYPE_BOCHS_DISPLAY "bochs-display"
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2020-09-16 20:25:19 +02:00
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OBJECT_DECLARE_SIMPLE_TYPE(BochsDisplayState, BOCHS_DISPLAY)
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2018-05-22 18:50:55 +02:00
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static const VMStateDescription vmstate_bochs_display = {
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.name = "bochs-display",
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.fields = (VMStateField[]) {
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VMSTATE_PCI_DEVICE(pci, BochsDisplayState),
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VMSTATE_UINT16_ARRAY(vbe_regs, BochsDisplayState, VBE_DISPI_INDEX_NB),
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VMSTATE_BOOL(big_endian_fb, BochsDisplayState),
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VMSTATE_END_OF_LIST()
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}
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};
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static uint64_t bochs_display_vbe_read(void *ptr, hwaddr addr,
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unsigned size)
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{
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BochsDisplayState *s = ptr;
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unsigned int index = addr >> 1;
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switch (index) {
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case VBE_DISPI_INDEX_ID:
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return VBE_DISPI_ID5;
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case VBE_DISPI_INDEX_VIDEO_MEMORY_64K:
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2018-06-25 14:42:06 +02:00
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return s->vgamem / (64 * KiB);
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2018-05-22 18:50:55 +02:00
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}
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if (index >= ARRAY_SIZE(s->vbe_regs)) {
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return -1;
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}
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return s->vbe_regs[index];
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}
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static void bochs_display_vbe_write(void *ptr, hwaddr addr,
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uint64_t val, unsigned size)
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{
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BochsDisplayState *s = ptr;
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unsigned int index = addr >> 1;
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if (index >= ARRAY_SIZE(s->vbe_regs)) {
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return;
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}
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s->vbe_regs[index] = val;
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}
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static const MemoryRegionOps bochs_display_vbe_ops = {
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.read = bochs_display_vbe_read,
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.write = bochs_display_vbe_write,
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.valid.min_access_size = 1,
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.valid.max_access_size = 4,
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.impl.min_access_size = 2,
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.impl.max_access_size = 2,
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.endianness = DEVICE_LITTLE_ENDIAN,
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};
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static uint64_t bochs_display_qext_read(void *ptr, hwaddr addr,
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unsigned size)
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{
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BochsDisplayState *s = ptr;
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switch (addr) {
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case PCI_VGA_QEXT_REG_SIZE:
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return PCI_VGA_QEXT_SIZE;
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case PCI_VGA_QEXT_REG_BYTEORDER:
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return s->big_endian_fb ?
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PCI_VGA_QEXT_BIG_ENDIAN : PCI_VGA_QEXT_LITTLE_ENDIAN;
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default:
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return 0;
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}
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}
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static void bochs_display_qext_write(void *ptr, hwaddr addr,
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uint64_t val, unsigned size)
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{
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BochsDisplayState *s = ptr;
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switch (addr) {
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case PCI_VGA_QEXT_REG_BYTEORDER:
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if (val == PCI_VGA_QEXT_BIG_ENDIAN) {
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s->big_endian_fb = true;
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}
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if (val == PCI_VGA_QEXT_LITTLE_ENDIAN) {
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s->big_endian_fb = false;
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}
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break;
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}
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}
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static const MemoryRegionOps bochs_display_qext_ops = {
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.read = bochs_display_qext_read,
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.write = bochs_display_qext_write,
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.valid.min_access_size = 4,
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.valid.max_access_size = 4,
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.endianness = DEVICE_LITTLE_ENDIAN,
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};
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static int bochs_display_get_mode(BochsDisplayState *s,
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BochsDisplayMode *mode)
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{
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uint16_t *vbe = s->vbe_regs;
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uint32_t virt_width;
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if (!(vbe[VBE_DISPI_INDEX_ENABLE] & VBE_DISPI_ENABLED)) {
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return -1;
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}
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memset(mode, 0, sizeof(*mode));
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switch (vbe[VBE_DISPI_INDEX_BPP]) {
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case 16:
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2023-08-23 08:53:27 +02:00
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/* best effort: support native endianness only */
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2018-05-22 18:50:55 +02:00
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mode->format = PIXMAN_r5g6b5;
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mode->bytepp = 2;
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2018-05-25 06:53:44 +02:00
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break;
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2018-05-22 18:50:55 +02:00
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case 32:
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mode->format = s->big_endian_fb
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? PIXMAN_BE_x8r8g8b8
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: PIXMAN_LE_x8r8g8b8;
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mode->bytepp = 4;
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break;
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default:
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return -1;
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}
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mode->width = vbe[VBE_DISPI_INDEX_XRES];
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mode->height = vbe[VBE_DISPI_INDEX_YRES];
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virt_width = vbe[VBE_DISPI_INDEX_VIRT_WIDTH];
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if (virt_width < mode->width) {
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virt_width = mode->width;
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}
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mode->stride = virt_width * mode->bytepp;
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mode->size = (uint64_t)mode->stride * mode->height;
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mode->offset = ((uint64_t)vbe[VBE_DISPI_INDEX_X_OFFSET] * mode->bytepp +
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(uint64_t)vbe[VBE_DISPI_INDEX_Y_OFFSET] * mode->stride);
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if (mode->width < 64 || mode->height < 64) {
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return -1;
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}
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if (mode->offset + mode->size > s->vgamem) {
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return -1;
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}
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return 0;
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}
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static void bochs_display_update(void *opaque)
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{
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BochsDisplayState *s = opaque;
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2018-05-22 18:50:56 +02:00
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DirtyBitmapSnapshot *snap = NULL;
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bool full_update = false;
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2018-05-22 18:50:55 +02:00
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BochsDisplayMode mode;
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DisplaySurface *ds;
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uint8_t *ptr;
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2018-05-22 18:50:56 +02:00
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bool dirty;
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int y, ys, ret;
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2018-05-22 18:50:55 +02:00
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ret = bochs_display_get_mode(s, &mode);
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if (ret < 0) {
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/* no (valid) video mode */
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return;
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}
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if (memcmp(&s->mode, &mode, sizeof(mode)) != 0) {
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/* video mode switch */
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s->mode = mode;
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ptr = memory_region_get_ram_ptr(&s->vram);
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ds = qemu_create_displaysurface_from(mode.width,
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mode.height,
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mode.format,
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mode.stride,
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ptr + mode.offset);
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dpy_gfx_replace_surface(s->con, ds);
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2018-05-22 18:50:56 +02:00
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full_update = true;
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2018-05-22 18:50:55 +02:00
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}
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2018-05-22 18:50:56 +02:00
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if (full_update) {
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dpy_gfx_update_full(s->con);
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} else {
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snap = memory_region_snapshot_and_clear_dirty(&s->vram,
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mode.offset, mode.size,
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DIRTY_MEMORY_VGA);
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ys = -1;
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for (y = 0; y < mode.height; y++) {
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dirty = memory_region_snapshot_get_dirty(&s->vram, snap,
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mode.offset + mode.stride * y,
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mode.stride);
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if (dirty && ys < 0) {
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ys = y;
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}
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if (!dirty && ys >= 0) {
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dpy_gfx_update(s->con, 0, ys,
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mode.width, y - ys);
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ys = -1;
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}
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}
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if (ys >= 0) {
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dpy_gfx_update(s->con, 0, ys,
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mode.width, y - ys);
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}
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2019-12-10 22:27:54 +01:00
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g_free(snap);
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2018-05-22 18:50:56 +02:00
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}
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2018-05-22 18:50:55 +02:00
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}
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static const GraphicHwOps bochs_display_gfx_ops = {
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.gfx_update = bochs_display_update,
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};
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static void bochs_display_realize(PCIDevice *dev, Error **errp)
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{
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BochsDisplayState *s = BOCHS_DISPLAY(dev);
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Object *obj = OBJECT(dev);
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2018-05-22 18:50:57 +02:00
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int ret;
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2018-05-22 18:50:55 +02:00
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2018-06-25 14:42:06 +02:00
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if (s->vgamem < 4 * MiB) {
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2018-05-22 18:50:55 +02:00
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error_setg(errp, "bochs-display: video memory too small");
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2020-04-22 15:07:12 +02:00
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return;
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2018-05-22 18:50:55 +02:00
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}
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2018-06-25 14:42:06 +02:00
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if (s->vgamem > 256 * MiB) {
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2018-05-22 18:50:55 +02:00
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error_setg(errp, "bochs-display: video memory too big");
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2020-04-22 15:07:12 +02:00
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return;
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2018-05-22 18:50:55 +02:00
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}
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s->vgamem = pow2ceil(s->vgamem);
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2020-04-22 15:07:12 +02:00
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s->con = graphic_console_init(DEVICE(dev), 0, &bochs_display_gfx_ops, s);
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2018-05-22 18:50:55 +02:00
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memory_region_init_ram(&s->vram, obj, "bochs-display-vram", s->vgamem,
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&error_fatal);
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memory_region_init_io(&s->vbe, obj, &bochs_display_vbe_ops, s,
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"bochs dispi interface", PCI_VGA_BOCHS_SIZE);
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memory_region_init_io(&s->qext, obj, &bochs_display_qext_ops, s,
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"qemu extended regs", PCI_VGA_QEXT_SIZE);
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2020-03-09 11:00:09 +01:00
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memory_region_init_io(&s->mmio, obj, &unassigned_io_ops, NULL,
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"bochs-display-mmio", PCI_VGA_MMIO_SIZE);
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2018-05-22 18:50:55 +02:00
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memory_region_add_subregion(&s->mmio, PCI_VGA_BOCHS_OFFSET, &s->vbe);
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memory_region_add_subregion(&s->mmio, PCI_VGA_QEXT_OFFSET, &s->qext);
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pci_set_byte(&s->pci.config[PCI_REVISION_ID], 2);
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pci_register_bar(&s->pci, 0, PCI_BASE_ADDRESS_MEM_PREFETCH, &s->vram);
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pci_register_bar(&s->pci, 2, PCI_BASE_ADDRESS_SPACE_MEMORY, &s->mmio);
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2018-05-22 18:50:56 +02:00
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2018-10-05 18:01:47 +02:00
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if (s->enable_edid) {
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qemu_edid_generate(s->edid_blob, sizeof(s->edid_blob), &s->edid_info);
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qemu_edid_region_io(&s->edid, obj, s->edid_blob, sizeof(s->edid_blob));
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memory_region_add_subregion(&s->mmio, 0, &s->edid);
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}
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2018-05-22 18:50:57 +02:00
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if (pci_bus_is_express(pci_get_bus(dev))) {
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ret = pcie_endpoint_cap_init(dev, 0x80);
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assert(ret > 0);
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2019-08-12 08:52:21 +02:00
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} else {
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dev->cap_present &= ~QEMU_PCI_CAP_EXPRESS;
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2018-05-22 18:50:57 +02:00
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}
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2018-05-22 18:50:56 +02:00
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memory_region_set_log(&s->vram, true, DIRTY_MEMORY_VGA);
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2018-05-22 18:50:55 +02:00
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}
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static bool bochs_display_get_big_endian_fb(Object *obj, Error **errp)
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{
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BochsDisplayState *s = BOCHS_DISPLAY(obj);
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return s->big_endian_fb;
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}
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static void bochs_display_set_big_endian_fb(Object *obj, bool value,
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Error **errp)
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{
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|
|
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BochsDisplayState *s = BOCHS_DISPLAY(obj);
|
|
|
|
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s->big_endian_fb = value;
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|
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}
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static void bochs_display_init(Object *obj)
|
|
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{
|
2019-08-12 08:52:21 +02:00
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PCIDevice *dev = PCI_DEVICE(obj);
|
|
|
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2018-05-22 18:50:55 +02:00
|
|
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/* Expose framebuffer byteorder via QOM */
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|
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object_property_add_bool(obj, "big-endian-framebuffer",
|
|
|
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bochs_display_get_big_endian_fb,
|
qom: Drop parameter @errp of object_property_add() & friends
The only way object_property_add() can fail is when a property with
the same name already exists. Since our property names are all
hardcoded, failure is a programming error, and the appropriate way to
handle it is passing &error_abort.
Same for its variants, except for object_property_add_child(), which
additionally fails when the child already has a parent. Parentage is
also under program control, so this is a programming error, too.
We have a bit over 500 callers. Almost half of them pass
&error_abort, slightly fewer ignore errors, one test case handles
errors, and the remaining few callers pass them to their own callers.
The previous few commits demonstrated once again that ignoring
programming errors is a bad idea.
Of the few ones that pass on errors, several violate the Error API.
The Error ** argument must be NULL, &error_abort, &error_fatal, or a
pointer to a variable containing NULL. Passing an argument of the
latter kind twice without clearing it in between is wrong: if the
first call sets an error, it no longer points to NULL for the second
call. ich9_pm_add_properties(), sparc32_ledma_realize(),
sparc32_dma_realize(), xilinx_axidma_realize(), xilinx_enet_realize()
are wrong that way.
When the one appropriate choice of argument is &error_abort, letting
users pick the argument is a bad idea.
Drop parameter @errp and assert the preconditions instead.
There's one exception to "duplicate property name is a programming
error": the way object_property_add() implements the magic (and
undocumented) "automatic arrayification". Don't drop @errp there.
Instead, rename object_property_add() to object_property_try_add(),
and add the obvious wrapper object_property_add().
Signed-off-by: Markus Armbruster <armbru@redhat.com>
Reviewed-by: Eric Blake <eblake@redhat.com>
Reviewed-by: Paolo Bonzini <pbonzini@redhat.com>
Message-Id: <20200505152926.18877-15-armbru@redhat.com>
[Two semantic rebase conflicts resolved]
2020-05-05 17:29:22 +02:00
|
|
|
bochs_display_set_big_endian_fb);
|
2019-08-12 08:52:21 +02:00
|
|
|
|
|
|
|
dev->cap_present |= QEMU_PCI_CAP_EXPRESS;
|
2018-05-22 18:50:55 +02:00
|
|
|
}
|
|
|
|
|
|
|
|
static void bochs_display_exit(PCIDevice *dev)
|
|
|
|
{
|
|
|
|
BochsDisplayState *s = BOCHS_DISPLAY(dev);
|
|
|
|
|
|
|
|
graphic_console_close(s->con);
|
|
|
|
}
|
|
|
|
|
|
|
|
static Property bochs_display_properties[] = {
|
2018-06-25 14:42:06 +02:00
|
|
|
DEFINE_PROP_SIZE("vgamem", BochsDisplayState, vgamem, 16 * MiB),
|
2019-06-07 10:34:44 +02:00
|
|
|
DEFINE_PROP_BOOL("edid", BochsDisplayState, enable_edid, true),
|
2018-10-05 18:01:47 +02:00
|
|
|
DEFINE_EDID_PROPERTIES(BochsDisplayState, edid_info),
|
2018-05-22 18:50:55 +02:00
|
|
|
DEFINE_PROP_END_OF_LIST(),
|
|
|
|
};
|
|
|
|
|
|
|
|
static void bochs_display_class_init(ObjectClass *klass, void *data)
|
|
|
|
{
|
|
|
|
DeviceClass *dc = DEVICE_CLASS(klass);
|
|
|
|
PCIDeviceClass *k = PCI_DEVICE_CLASS(klass);
|
|
|
|
|
|
|
|
k->class_id = PCI_CLASS_DISPLAY_OTHER;
|
|
|
|
k->vendor_id = PCI_VENDOR_ID_QEMU;
|
|
|
|
k->device_id = PCI_DEVICE_ID_QEMU_VGA;
|
|
|
|
|
|
|
|
k->realize = bochs_display_realize;
|
2018-05-30 15:02:16 +02:00
|
|
|
k->romfile = "vgabios-bochs-display.bin";
|
2018-05-22 18:50:55 +02:00
|
|
|
k->exit = bochs_display_exit;
|
|
|
|
dc->vmsd = &vmstate_bochs_display;
|
2020-01-10 16:30:32 +01:00
|
|
|
device_class_set_props(dc, bochs_display_properties);
|
2018-05-22 18:50:55 +02:00
|
|
|
set_bit(DEVICE_CATEGORY_DISPLAY, dc->categories);
|
|
|
|
}
|
|
|
|
|
|
|
|
static const TypeInfo bochs_display_type_info = {
|
|
|
|
.name = TYPE_BOCHS_DISPLAY,
|
|
|
|
.parent = TYPE_PCI_DEVICE,
|
|
|
|
.instance_size = sizeof(BochsDisplayState),
|
|
|
|
.instance_init = bochs_display_init,
|
|
|
|
.class_init = bochs_display_class_init,
|
|
|
|
.interfaces = (InterfaceInfo[]) {
|
2018-05-22 18:50:57 +02:00
|
|
|
{ INTERFACE_PCIE_DEVICE },
|
2018-05-22 18:50:55 +02:00
|
|
|
{ INTERFACE_CONVENTIONAL_PCI_DEVICE },
|
|
|
|
{ },
|
|
|
|
},
|
|
|
|
};
|
|
|
|
|
|
|
|
static void bochs_display_register_types(void)
|
|
|
|
{
|
|
|
|
type_register_static(&bochs_display_type_info);
|
|
|
|
}
|
|
|
|
|
|
|
|
type_init(bochs_display_register_types)
|