2019-07-01 18:26:18 +02:00
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/*
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* ASPEED XDMA Controller
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* Eddie James <eajames@linux.ibm.com>
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*
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* Copyright (C) 2019 IBM Corp.
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2021-02-01 21:01:47 +01:00
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* SPDX-License-Identifier: GPL-2.0-or-later
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2019-07-01 18:26:18 +02:00
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*/
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#ifndef ASPEED_XDMA_H
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#define ASPEED_XDMA_H
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#include "hw/sysbus.h"
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2020-09-03 22:43:22 +02:00
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#include "qom/object.h"
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2019-07-01 18:26:18 +02:00
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#define TYPE_ASPEED_XDMA "aspeed.xdma"
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2021-05-01 10:03:52 +02:00
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#define TYPE_ASPEED_2400_XDMA TYPE_ASPEED_XDMA "-ast2400"
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#define TYPE_ASPEED_2500_XDMA TYPE_ASPEED_XDMA "-ast2500"
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#define TYPE_ASPEED_2600_XDMA TYPE_ASPEED_XDMA "-ast2600"
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OBJECT_DECLARE_TYPE(AspeedXDMAState, AspeedXDMAClass, ASPEED_XDMA)
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2019-07-01 18:26:18 +02:00
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#define ASPEED_XDMA_NUM_REGS (ASPEED_XDMA_REG_SIZE / sizeof(uint32_t))
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#define ASPEED_XDMA_REG_SIZE 0x7C
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2020-09-03 22:43:22 +02:00
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struct AspeedXDMAState {
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2019-07-01 18:26:18 +02:00
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SysBusDevice parent;
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MemoryRegion iomem;
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qemu_irq irq;
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char bmc_cmdq_readp_set;
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uint32_t regs[ASPEED_XDMA_NUM_REGS];
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2020-09-03 22:43:22 +02:00
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};
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2019-07-01 18:26:18 +02:00
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2021-05-01 10:03:52 +02:00
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struct AspeedXDMAClass {
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SysBusDeviceClass parent_class;
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uint8_t cmdq_endp;
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uint8_t cmdq_wrp;
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uint8_t cmdq_rdp;
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uint8_t intr_ctrl;
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uint32_t intr_ctrl_mask;
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uint8_t intr_status;
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uint32_t intr_complete;
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};
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2019-07-01 18:26:18 +02:00
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#endif /* ASPEED_XDMA_H */
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