target/riscv: rvv: Fix early exit condition for whole register load/store
Vector whole register load instructions have EEW encoded in the opcode, so we shouldn't take SEW here. Vector whole register store instructions are always EEW=8. Signed-off-by: eop Chen <eop.chen@sifive.com> Reviewed-by: Frank Chang <frank.chang@sifive.com> Acked-by: Alistair Francis <alistair.francis@wdc.com> Message-Id: <165181414065.18540.14828125053334599921-0@git.sr.ht> Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
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@ -1118,10 +1118,10 @@ GEN_VEXT_TRANS(vle64ff_v, MO_64, r2nfvm, ldff_op, ld_us_check)
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typedef void gen_helper_ldst_whole(TCGv_ptr, TCGv, TCGv_env, TCGv_i32);
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static bool ldst_whole_trans(uint32_t vd, uint32_t rs1, uint32_t nf,
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gen_helper_ldst_whole *fn, DisasContext *s,
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bool is_store)
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uint32_t width, gen_helper_ldst_whole *fn,
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DisasContext *s, bool is_store)
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{
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uint32_t evl = (s->cfg_ptr->vlen / 8) * nf / (1 << s->sew);
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uint32_t evl = (s->cfg_ptr->vlen / 8) * nf / width;
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TCGLabel *over = gen_new_label();
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tcg_gen_brcondi_tl(TCG_COND_GEU, cpu_vstart, evl, over);
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@ -1153,38 +1153,42 @@ static bool ldst_whole_trans(uint32_t vd, uint32_t rs1, uint32_t nf,
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* load and store whole register instructions ignore vtype and vl setting.
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* Thus, we don't need to check vill bit. (Section 7.9)
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*/
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#define GEN_LDST_WHOLE_TRANS(NAME, ARG_NF, IS_STORE) \
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#define GEN_LDST_WHOLE_TRANS(NAME, ARG_NF, WIDTH, IS_STORE) \
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static bool trans_##NAME(DisasContext *s, arg_##NAME * a) \
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{ \
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if (require_rvv(s) && \
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QEMU_IS_ALIGNED(a->rd, ARG_NF)) { \
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return ldst_whole_trans(a->rd, a->rs1, ARG_NF, gen_helper_##NAME, \
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s, IS_STORE); \
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return ldst_whole_trans(a->rd, a->rs1, ARG_NF, WIDTH, \
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gen_helper_##NAME, s, IS_STORE); \
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} \
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return false; \
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}
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GEN_LDST_WHOLE_TRANS(vl1re8_v, 1, false)
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GEN_LDST_WHOLE_TRANS(vl1re16_v, 1, false)
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GEN_LDST_WHOLE_TRANS(vl1re32_v, 1, false)
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GEN_LDST_WHOLE_TRANS(vl1re64_v, 1, false)
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GEN_LDST_WHOLE_TRANS(vl2re8_v, 2, false)
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GEN_LDST_WHOLE_TRANS(vl2re16_v, 2, false)
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GEN_LDST_WHOLE_TRANS(vl2re32_v, 2, false)
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GEN_LDST_WHOLE_TRANS(vl2re64_v, 2, false)
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GEN_LDST_WHOLE_TRANS(vl4re8_v, 4, false)
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GEN_LDST_WHOLE_TRANS(vl4re16_v, 4, false)
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GEN_LDST_WHOLE_TRANS(vl4re32_v, 4, false)
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GEN_LDST_WHOLE_TRANS(vl4re64_v, 4, false)
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GEN_LDST_WHOLE_TRANS(vl8re8_v, 8, false)
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GEN_LDST_WHOLE_TRANS(vl8re16_v, 8, false)
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GEN_LDST_WHOLE_TRANS(vl8re32_v, 8, false)
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GEN_LDST_WHOLE_TRANS(vl8re64_v, 8, false)
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GEN_LDST_WHOLE_TRANS(vl1re8_v, 1, 1, false)
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GEN_LDST_WHOLE_TRANS(vl1re16_v, 1, 2, false)
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GEN_LDST_WHOLE_TRANS(vl1re32_v, 1, 4, false)
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GEN_LDST_WHOLE_TRANS(vl1re64_v, 1, 8, false)
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GEN_LDST_WHOLE_TRANS(vl2re8_v, 2, 1, false)
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GEN_LDST_WHOLE_TRANS(vl2re16_v, 2, 2, false)
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GEN_LDST_WHOLE_TRANS(vl2re32_v, 2, 4, false)
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GEN_LDST_WHOLE_TRANS(vl2re64_v, 2, 8, false)
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GEN_LDST_WHOLE_TRANS(vl4re8_v, 4, 1, false)
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GEN_LDST_WHOLE_TRANS(vl4re16_v, 4, 2, false)
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GEN_LDST_WHOLE_TRANS(vl4re32_v, 4, 4, false)
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GEN_LDST_WHOLE_TRANS(vl4re64_v, 4, 8, false)
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GEN_LDST_WHOLE_TRANS(vl8re8_v, 8, 1, false)
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GEN_LDST_WHOLE_TRANS(vl8re16_v, 8, 2, false)
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GEN_LDST_WHOLE_TRANS(vl8re32_v, 8, 4, false)
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GEN_LDST_WHOLE_TRANS(vl8re64_v, 8, 8, false)
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GEN_LDST_WHOLE_TRANS(vs1r_v, 1, true)
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GEN_LDST_WHOLE_TRANS(vs2r_v, 2, true)
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GEN_LDST_WHOLE_TRANS(vs4r_v, 4, true)
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GEN_LDST_WHOLE_TRANS(vs8r_v, 8, true)
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/*
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* The vector whole register store instructions are encoded similar to
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* unmasked unit-stride store of elements with EEW=8.
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*/
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GEN_LDST_WHOLE_TRANS(vs1r_v, 1, 1, true)
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GEN_LDST_WHOLE_TRANS(vs2r_v, 2, 1, true)
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GEN_LDST_WHOLE_TRANS(vs4r_v, 4, 1, true)
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GEN_LDST_WHOLE_TRANS(vs8r_v, 8, 1, true)
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/*
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*** Vector Integer Arithmetic Instructions
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