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target/riscv: Fix VS mode hypervisor CSR access

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VS mode access to hypervisor CSRs should generate virtual, not illegal,
instruction exceptions.

Don't return early and indicate an illegal instruction exception when
accessing a hypervisor CSR from VS mode. Instead, fall through to the
`hmode` predicate to return the correct virtual instruction exception.

Signed-off-by: Dylan Reid <dgreid@rivosinc.com>
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Message-Id: <20220506165456.297058-1-dgreid@rivosinc.com>
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
This commit is contained in:
Dylan Reid 2022-05-06 16:54:57 +00:00 committed by Alistair Francis
parent 3757b0d08b
commit d6cd3ae0eb
1 changed files with 5 additions and 5 deletions
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10
target/riscv/csr.c
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@ -3141,13 +3141,13 @@ static inline RISCVException riscv_csrrw_check(CPURISCVState *env,
#if !defined(CONFIG_USER_ONLY)
int effective_priv = env->priv;
if (riscv_has_ext(env, RVH) &&
env->priv == PRV_S &&
!riscv_cpu_virt_enabled(env)) {
if (riscv_has_ext(env, RVH) && env->priv == PRV_S) {
/*
* We are in S mode without virtualisation, therefore we are in HS Mode.
* We are in either HS or VS mode.
* Add 1 to the effective privledge level to allow us to access the
* Hypervisor CSRs.
* Hypervisor CSRs. The `hmode` predicate will determine if access
* should be allowed(HS) or if a virtual instruction exception should be
* raised(VS).
*/
effective_priv++;
}