disas/riscv: Add Zb[abcs] instructions
With the addition of Zb[abcs], we also need to add disassembler support for these new instructions. Signed-off-by: Philipp Tomsich <philipp.tomsich@vrull.eu> Acked-by: Alistair Francis <alistair.francis@wdc.com> Message-id: 20210911140016.834071-17-philipp.tomsich@vrull.eu Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
This commit is contained in:
Philipp Tomsich
Alistair Francis
parent
9916ea3c97
commit
02c1b569a1
157
disas/riscv.c
157
disas/riscv.c
@ -478,6 +478,49 @@ typedef enum {
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rv_op_fsflags = 316,
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rv_op_fsrmi = 317,
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rv_op_fsflagsi = 318,
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rv_op_bseti = 319,
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rv_op_bclri = 320,
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rv_op_binvi = 321,
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rv_op_bexti = 322,
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rv_op_rori = 323,
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rv_op_clz = 324,
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rv_op_ctz = 325,
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rv_op_cpop = 326,
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rv_op_sext_h = 327,
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rv_op_sext_b = 328,
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rv_op_xnor = 329,
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rv_op_orn = 330,
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rv_op_andn = 331,
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rv_op_rol = 332,
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rv_op_ror = 333,
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rv_op_sh1add = 334,
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rv_op_sh2add = 335,
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rv_op_sh3add = 336,
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rv_op_sh1add_uw = 337,
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rv_op_sh2add_uw = 338,
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rv_op_sh3add_uw = 339,
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rv_op_clmul = 340,
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rv_op_clmulr = 341,
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rv_op_clmulh = 342,
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rv_op_min = 343,
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rv_op_minu = 344,
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rv_op_max = 345,
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rv_op_maxu = 346,
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rv_op_clzw = 347,
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rv_op_ctzw = 348,
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rv_op_cpopw = 349,
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rv_op_slli_uw = 350,
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rv_op_add_uw = 351,
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rv_op_rolw = 352,
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rv_op_rorw = 353,
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rv_op_rev8 = 354,
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rv_op_zext_h = 355,
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rv_op_roriw = 356,
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rv_op_orc_b = 357,
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rv_op_bset = 358,
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rv_op_bclr = 359,
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rv_op_binv = 360,
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rv_op_bext = 361,
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} rv_op;
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/* structures */
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@ -1117,6 +1160,49 @@ const rv_opcode_data opcode_data[] = {
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{ "fsflags", rv_codec_i_csr, rv_fmt_rd_rs1, NULL, 0, 0, 0 },
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{ "fsrmi", rv_codec_i_csr, rv_fmt_rd_zimm, NULL, 0, 0, 0 },
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{ "fsflagsi", rv_codec_i_csr, rv_fmt_rd_zimm, NULL, 0, 0, 0 },
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{ "bseti", rv_codec_i_sh7, rv_fmt_rd_rs1_imm, NULL, 0, 0, 0 },
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{ "bclri", rv_codec_i_sh7, rv_fmt_rd_rs1_imm, NULL, 0, 0, 0 },
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{ "binvi", rv_codec_i_sh7, rv_fmt_rd_rs1_imm, NULL, 0, 0, 0 },
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{ "bexti", rv_codec_i_sh7, rv_fmt_rd_rs1_imm, NULL, 0, 0, 0 },
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{ "rori", rv_codec_i_sh7, rv_fmt_rd_rs1_imm, NULL, 0, 0, 0 },
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{ "clz", rv_codec_r, rv_fmt_rd_rs1, NULL, 0, 0, 0 },
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{ "ctz", rv_codec_r, rv_fmt_rd_rs1, NULL, 0, 0, 0 },
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{ "cpop", rv_codec_r, rv_fmt_rd_rs1, NULL, 0, 0, 0 },
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{ "sext.h", rv_codec_r, rv_fmt_rd_rs1, NULL, 0, 0, 0 },
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{ "sext.b", rv_codec_r, rv_fmt_rd_rs1, NULL, 0, 0, 0 },
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{ "xnor", rv_codec_r, rv_fmt_rd_rs1, NULL, 0, 0, 0 },
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{ "orn", rv_codec_r, rv_fmt_rd_rs1, NULL, 0, 0, 0 },
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{ "andn", rv_codec_r, rv_fmt_rd_rs1, NULL, 0, 0, 0 },
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{ "rol", rv_codec_r, rv_fmt_rd_rs1_rs2, NULL, 0, 0, 0 },
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{ "ror", rv_codec_r, rv_fmt_rd_rs1_rs2, NULL, 0, 0, 0 },
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{ "sh1add", rv_codec_r, rv_fmt_rd_rs1_rs2, NULL, 0, 0, 0 },
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{ "sh2add", rv_codec_r, rv_fmt_rd_rs1_rs2, NULL, 0, 0, 0 },
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{ "sh3add", rv_codec_r, rv_fmt_rd_rs1_rs2, NULL, 0, 0, 0 },
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{ "sh1add.uw", rv_codec_r, rv_fmt_rd_rs1_rs2, NULL, 0, 0, 0 },
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{ "sh2add.uw", rv_codec_r, rv_fmt_rd_rs1_rs2, NULL, 0, 0, 0 },
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{ "sh3add.uw", rv_codec_r, rv_fmt_rd_rs1_rs2, NULL, 0, 0, 0 },
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{ "clmul", rv_codec_r, rv_fmt_rd_rs1_rs2, NULL, 0, 0, 0 },
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{ "clmulr", rv_codec_r, rv_fmt_rd_rs1_rs2, NULL, 0, 0, 0 },
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{ "clmulh", rv_codec_r, rv_fmt_rd_rs1_rs2, NULL, 0, 0, 0 },
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{ "min", rv_codec_r, rv_fmt_rd_rs1_rs2, NULL, 0, 0, 0 },
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{ "minu", rv_codec_r, rv_fmt_rd_rs1_rs2, NULL, 0, 0, 0 },
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{ "max", rv_codec_r, rv_fmt_rd_rs1_rs2, NULL, 0, 0, 0 },
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{ "maxu", rv_codec_r, rv_fmt_rd_rs1_rs2, NULL, 0, 0, 0 },
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{ "clzw", rv_codec_r, rv_fmt_rd_rs1, NULL, 0, 0, 0 },
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{ "clzw", rv_codec_r, rv_fmt_rd_rs1, NULL, 0, 0, 0 },
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{ "cpopw", rv_codec_r, rv_fmt_rd_rs1, NULL, 0, 0, 0 },
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{ "slli.uw", rv_codec_r, rv_fmt_rd_rs1_rs2, NULL, 0, 0, 0 },
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{ "add.uw", rv_codec_r, rv_fmt_rd_rs1_rs2, NULL, 0, 0, 0 },
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{ "rolw", rv_codec_r, rv_fmt_rd_rs1_rs2, NULL, 0, 0, 0 },
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{ "rorw", rv_codec_r, rv_fmt_rd_rs1_rs2, NULL, 0, 0, 0 },
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{ "rev8", rv_codec_r, rv_fmt_rd_rs1, NULL, 0, 0, 0 },
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{ "zext.h", rv_codec_r, rv_fmt_rd_rs1, NULL, 0, 0, 0 },
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{ "roriw", rv_codec_i_sh5, rv_fmt_rd_rs1_imm, NULL, 0, 0, 0 },
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{ "orc.b", rv_codec_r, rv_fmt_rd_rs1, NULL, 0, 0, 0 },
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{ "bset", rv_codec_r, rv_fmt_rd_rs1_rs2, NULL, 0, 0, 0 },
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{ "bclr", rv_codec_r, rv_fmt_rd_rs1_rs2, NULL, 0, 0, 0 },
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{ "binv", rv_codec_r, rv_fmt_rd_rs1_rs2, NULL, 0, 0, 0 },
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{ "bext", rv_codec_r, rv_fmt_rd_rs1_rs2, NULL, 0, 0, 0 },
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};
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/* CSR names */
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@ -1507,7 +1593,20 @@ static void decode_inst_opcode(rv_decode *dec, rv_isa isa)
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case 0: op = rv_op_addi; break;
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case 1:
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switch (((inst >> 27) & 0b11111)) {
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case 0: op = rv_op_slli; break;
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case 0b00000: op = rv_op_slli; break;
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case 0b00101: op = rv_op_bseti; break;
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case 0b01001: op = rv_op_bclri; break;
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case 0b01101: op = rv_op_binvi; break;
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case 0b01100:
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switch (((inst >> 20) & 0b1111111)) {
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case 0b0000000: op = rv_op_clz; break;
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case 0b0000001: op = rv_op_ctz; break;
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case 0b0000010: op = rv_op_cpop; break;
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/* 0b0000011 */
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case 0b0000100: op = rv_op_sext_b; break;
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case 0b0000101: op = rv_op_sext_h; break;
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}
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break;
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}
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break;
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case 2: op = rv_op_slti; break;
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@ -1515,8 +1614,16 @@ static void decode_inst_opcode(rv_decode *dec, rv_isa isa)
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case 4: op = rv_op_xori; break;
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case 5:
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switch (((inst >> 27) & 0b11111)) {
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case 0: op = rv_op_srli; break;
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case 8: op = rv_op_srai; break;
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case 0b00000: op = rv_op_srli; break;
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case 0b00101: op = rv_op_orc_b; break;
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case 0b01000: op = rv_op_srai; break;
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case 0b01001: op = rv_op_bexti; break;
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case 0b01100: op = rv_op_rori; break;
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case 0b01101:
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switch ((inst >> 20) & 0b1111111) {
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case 0b0111000: op = rv_op_rev8; break;
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}
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break;
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}
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break;
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case 6: op = rv_op_ori; break;
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@ -1530,12 +1637,21 @@ static void decode_inst_opcode(rv_decode *dec, rv_isa isa)
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case 1:
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switch (((inst >> 25) & 0b1111111)) {
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case 0: op = rv_op_slliw; break;
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case 4: op = rv_op_slli_uw; break;
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case 48:
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switch ((inst >> 20) & 0b11111) {
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case 0b00000: op = rv_op_clzw; break;
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case 0b00001: op = rv_op_ctzw; break;
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case 0b00010: op = rv_op_cpopw; break;
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}
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break;
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}
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break;
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case 5:
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switch (((inst >> 25) & 0b1111111)) {
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case 0: op = rv_op_srliw; break;
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case 32: op = rv_op_sraiw; break;
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case 48: op = rv_op_roriw; break;
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}
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break;
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}
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@ -1623,8 +1739,32 @@ static void decode_inst_opcode(rv_decode *dec, rv_isa isa)
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case 13: op = rv_op_divu; break;
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case 14: op = rv_op_rem; break;
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case 15: op = rv_op_remu; break;
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case 36:
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switch ((inst >> 20) & 0b11111) {
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case 0: op = rv_op_zext_h; break;
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}
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break;
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case 41: op = rv_op_clmul; break;
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case 42: op = rv_op_clmulr; break;
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case 43: op = rv_op_clmulh; break;
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case 44: op = rv_op_min; break;
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case 45: op = rv_op_minu; break;
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case 46: op = rv_op_max; break;
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case 47: op = rv_op_maxu; break;
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case 130: op = rv_op_sh1add; break;
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case 132: op = rv_op_sh2add; break;
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case 134: op = rv_op_sh3add; break;
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case 161: op = rv_op_bset; break;
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case 256: op = rv_op_sub; break;
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case 260: op = rv_op_xnor; break;
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case 261: op = rv_op_sra; break;
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case 262: op = rv_op_orn; break;
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case 263: op = rv_op_andn; break;
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case 289: op = rv_op_bclr; break;
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case 293: op = rv_op_bext; break;
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case 385: op = rv_op_rol; break;
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case 386: op = rv_op_ror; break;
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case 417: op = rv_op_binv; break;
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}
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break;
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case 13: op = rv_op_lui; break;
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@ -1638,8 +1778,19 @@ static void decode_inst_opcode(rv_decode *dec, rv_isa isa)
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case 13: op = rv_op_divuw; break;
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case 14: op = rv_op_remw; break;
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case 15: op = rv_op_remuw; break;
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case 32: op = rv_op_add_uw; break;
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case 36:
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switch ((inst >> 20) & 0b11111) {
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case 0: op = rv_op_zext_h; break;
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}
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break;
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case 130: op = rv_op_sh1add_uw; break;
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case 132: op = rv_op_sh2add_uw; break;
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case 134: op = rv_op_sh3add_uw; break;
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case 256: op = rv_op_subw; break;
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case 261: op = rv_op_sraw; break;
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case 385: op = rv_op_rolw; break;
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case 389: op = rv_op_rorw; break;
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}
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break;
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case 16:
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