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target-mips: remove JR, BLTZAL, BGEZAL and add NAL, BAL instructions

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Signed-off-by: Yongbok Kim <yongbok.kim@imgtec.com>
Signed-off-by: Leon Alrae <leon.alrae@imgtec.com>
Reviewed-by: Aurelien Jarno <aurelien@aurel32.net>
This commit is contained in:
Yongbok Kim 2014-06-27 08:49:08 +01:00 committed by Leon Alrae
parent ddc584bdb5
commit 0aefa33318
2 changed files with 18 additions and 2 deletions
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2
disas/mips.c
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@ -1313,6 +1313,8 @@ const struct mips_opcode mips_builtin_opcodes[] =
{"bgtzalc", "s,t,p", 0x1c000000, 0xffe00000, CBD|RD_s|RD_t, 0, I32R6}, {"bgtzalc", "s,t,p", 0x1c000000, 0xffe00000, CBD|RD_s|RD_t, 0, I32R6},
{"bltzalc", "s,t,p", 0x1c000000, 0xfc000000, CBD|RD_s|RD_t, 0, I32R6}, {"bltzalc", "s,t,p", 0x1c000000, 0xfc000000, CBD|RD_s|RD_t, 0, I32R6},
{"bltuc", "s,t,p", 0x1c000000, 0xfc000000, CBD|RD_s|RD_t, 0, I32R6}, {"bltuc", "s,t,p", 0x1c000000, 0xfc000000, CBD|RD_s|RD_t, 0, I32R6},
{"nal", "p", 0x04100000, 0xffff0000, WR_31, 0, I32R6},
{"bal", "p", 0x04110000, 0xffff0000, UBD|WR_31, 0, I32R6},
{"bc1eqz", "T,p", 0x45200000, 0xffe00000, CBD|RD_T|FP_S|FP_D, 0, I32R6}, {"bc1eqz", "T,p", 0x45200000, 0xffe00000, CBD|RD_T|FP_S|FP_D, 0, I32R6},
{"bc1nez", "T,p", 0x45a00000, 0xffe00000, CBD|RD_T|FP_S|FP_D, 0, I32R6}, {"bc1nez", "T,p", 0x45a00000, 0xffe00000, CBD|RD_T|FP_S|FP_D, 0, I32R6},
{"bc2eqz", "E,p", 0x49200000, 0xffe00000, CBD|RD_C2, 0, I32R6}, {"bc2eqz", "E,p", 0x49200000, 0xffe00000, CBD|RD_C2, 0, I32R6},

18
target-mips/translate.c
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@ -15851,6 +15851,9 @@ static void decode_opc_special_legacy(CPUMIPSState *env, DisasContext *ctx)
gen_muldiv(ctx, op1, 0, rs, rt); gen_muldiv(ctx, op1, 0, rs, rt);
break; break;
#endif #endif
case OPC_JR:
gen_compute_branch(ctx, op1, 4, rs, rd, sa);
break;
case OPC_SPIM: case OPC_SPIM:
#ifdef MIPS_STRICT_STANDARD #ifdef MIPS_STRICT_STANDARD
MIPS_INVAL("SPIM"); MIPS_INVAL("SPIM");
@ -15933,7 +15936,7 @@ static void decode_opc_special(CPUMIPSState *env, DisasContext *ctx)
case OPC_XOR: case OPC_XOR:
gen_logic(ctx, op1, rd, rs, rt); gen_logic(ctx, op1, rd, rs, rt);
break; break;
case OPC_JR ... OPC_JALR: case OPC_JALR:
gen_compute_branch(ctx, op1, 4, rs, rd, sa); gen_compute_branch(ctx, op1, 4, rs, rd, sa);
break; break;
case OPC_TGE ... OPC_TEQ: /* Traps */ case OPC_TGE ... OPC_TEQ: /* Traps */
@ -16903,9 +16906,20 @@ static void decode_opc (CPUMIPSState *env, DisasContext *ctx)
check_insn_opc_removed(ctx, ISA_MIPS32R6); check_insn_opc_removed(ctx, ISA_MIPS32R6);
case OPC_BLTZ: case OPC_BLTZ:
case OPC_BGEZ: case OPC_BGEZ:
gen_compute_branch(ctx, op1, 4, rs, -1, imm << 2);
break;
case OPC_BLTZAL: case OPC_BLTZAL:
case OPC_BGEZAL: case OPC_BGEZAL:
gen_compute_branch(ctx, op1, 4, rs, -1, imm << 2); if (ctx->insn_flags & ISA_MIPS32R6) {
if (rs == 0) {
/* OPC_NAL, OPC_BAL */
gen_compute_branch(ctx, op1, 4, 0, -1, imm << 2);
} else {
generate_exception(ctx, EXCP_RI);
}
} else {
gen_compute_branch(ctx, op1, 4, rs, -1, imm << 2);
}
break; break;
case OPC_TGEI ... OPC_TEQI: /* REGIMM traps */ case OPC_TGEI ... OPC_TEQI: /* REGIMM traps */
case OPC_TNEI: case OPC_TNEI: