target-mips: remove JR, BLTZAL, BGEZAL and add NAL, BAL instructions
Signed-off-by: Yongbok Kim <yongbok.kim@imgtec.com> Signed-off-by: Leon Alrae <leon.alrae@imgtec.com> Reviewed-by: Aurelien Jarno <aurelien@aurel32.net>
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@ -1313,6 +1313,8 @@ const struct mips_opcode mips_builtin_opcodes[] =
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{"bgtzalc", "s,t,p", 0x1c000000, 0xffe00000, CBD|RD_s|RD_t, 0, I32R6},
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{"bltzalc", "s,t,p", 0x1c000000, 0xfc000000, CBD|RD_s|RD_t, 0, I32R6},
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{"bltuc", "s,t,p", 0x1c000000, 0xfc000000, CBD|RD_s|RD_t, 0, I32R6},
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{"nal", "p", 0x04100000, 0xffff0000, WR_31, 0, I32R6},
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{"bal", "p", 0x04110000, 0xffff0000, UBD|WR_31, 0, I32R6},
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{"bc1eqz", "T,p", 0x45200000, 0xffe00000, CBD|RD_T|FP_S|FP_D, 0, I32R6},
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{"bc1nez", "T,p", 0x45a00000, 0xffe00000, CBD|RD_T|FP_S|FP_D, 0, I32R6},
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{"bc2eqz", "E,p", 0x49200000, 0xffe00000, CBD|RD_C2, 0, I32R6},
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@ -15851,6 +15851,9 @@ static void decode_opc_special_legacy(CPUMIPSState *env, DisasContext *ctx)
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gen_muldiv(ctx, op1, 0, rs, rt);
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break;
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#endif
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case OPC_JR:
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gen_compute_branch(ctx, op1, 4, rs, rd, sa);
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break;
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case OPC_SPIM:
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#ifdef MIPS_STRICT_STANDARD
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MIPS_INVAL("SPIM");
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@ -15933,7 +15936,7 @@ static void decode_opc_special(CPUMIPSState *env, DisasContext *ctx)
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case OPC_XOR:
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gen_logic(ctx, op1, rd, rs, rt);
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break;
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case OPC_JR ... OPC_JALR:
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case OPC_JALR:
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gen_compute_branch(ctx, op1, 4, rs, rd, sa);
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break;
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case OPC_TGE ... OPC_TEQ: /* Traps */
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@ -16903,9 +16906,20 @@ static void decode_opc (CPUMIPSState *env, DisasContext *ctx)
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check_insn_opc_removed(ctx, ISA_MIPS32R6);
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case OPC_BLTZ:
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case OPC_BGEZ:
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gen_compute_branch(ctx, op1, 4, rs, -1, imm << 2);
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break;
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case OPC_BLTZAL:
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case OPC_BGEZAL:
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if (ctx->insn_flags & ISA_MIPS32R6) {
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if (rs == 0) {
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/* OPC_NAL, OPC_BAL */
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gen_compute_branch(ctx, op1, 4, 0, -1, imm << 2);
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} else {
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generate_exception(ctx, EXCP_RI);
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}
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} else {
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gen_compute_branch(ctx, op1, 4, rs, -1, imm << 2);
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}
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break;
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case OPC_TGEI ... OPC_TEQI: /* REGIMM traps */
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case OPC_TNEI:
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