target-mips: make ITC Configuration Tags accessible to the CPU
Add CP0.ErrCtl register with WST, SPR and ITC bits. In 34K and interAptiv processors these bits are used to enable CACHE instruction access to different arrays. When WST=0, SPR=0 and ITC=1 the CACHE instruction will access ITC tag values. Generally we do not model caches and we have been treating the CACHE instruction as NOP. But since CACHE can operate on ITC Tags new MIPS_HFLAG_ITC_CACHE hflag is introduced to generate the helper only when CACHE is in the ITC Access mode. Signed-off-by: Leon Alrae <leon.alrae@imgtec.com>
This commit is contained in:
Leon Alrae
parent
40d48212f9
commit
0d74a222c2
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@ -519,6 +519,10 @@ struct CPUMIPSState {
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#define CP0DB_DSS 0
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target_ulong CP0_DEPC;
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int32_t CP0_Performance0;
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int32_t CP0_ErrCtl;
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#define CP0EC_WST 29
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#define CP0EC_SPR 28
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#define CP0EC_ITC 26
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uint64_t CP0_TagLo;
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int32_t CP0_DataLo;
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int32_t CP0_TagHi;
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@ -534,7 +538,7 @@ struct CPUMIPSState {
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#define EXCP_INST_NOTAVAIL 0x2 /* No valid instruction word for BadInstr */
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uint32_t hflags; /* CPU State */
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/* TMASK defines different execution modes */
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#define MIPS_HFLAG_TMASK 0x75807FF
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#define MIPS_HFLAG_TMASK 0xF5807FF
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#define MIPS_HFLAG_MODE 0x00007 /* execution modes */
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/* The KSU flags must be the lowest bits in hflags. The flag order
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must be the same as defined for CP0 Status. This allows to use
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@ -583,6 +587,7 @@ struct CPUMIPSState {
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#define MIPS_HFLAG_MSA 0x1000000
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#define MIPS_HFLAG_FRE 0x2000000 /* FRE enabled */
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#define MIPS_HFLAG_ELPA 0x4000000
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#define MIPS_HFLAG_ITC_CACHE 0x8000000 /* CACHE instr. operates on ITC tag */
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target_ulong btarget; /* Jump / branch target */
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target_ulong bcond; /* Branch condition (if needed) */
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@ -151,6 +151,7 @@ DEF_HELPER_2(mtc0_framemask, void, env, tl)
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DEF_HELPER_2(mtc0_debug, void, env, tl)
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DEF_HELPER_2(mttc0_debug, void, env, tl)
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DEF_HELPER_2(mtc0_performance0, void, env, tl)
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DEF_HELPER_2(mtc0_errctl, void, env, tl)
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DEF_HELPER_2(mtc0_taglo, void, env, tl)
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DEF_HELPER_2(mtc0_datalo, void, env, tl)
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DEF_HELPER_2(mtc0_taghi, void, env, tl)
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@ -949,3 +950,5 @@ MSALDST_PROTO(h)
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MSALDST_PROTO(w)
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MSALDST_PROTO(d)
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#undef MSALDST_PROTO
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DEF_HELPER_3(cache, void, env, tl, i32)
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@ -1632,9 +1632,31 @@ void helper_mtc0_performance0(CPUMIPSState *env, target_ulong arg1)
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env->CP0_Performance0 = arg1 & 0x000007ff;
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}
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void helper_mtc0_errctl(CPUMIPSState *env, target_ulong arg1)
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{
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int32_t wst = arg1 & (1 << CP0EC_WST);
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int32_t spr = arg1 & (1 << CP0EC_SPR);
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int32_t itc = env->itc_tag ? (arg1 & (1 << CP0EC_ITC)) : 0;
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env->CP0_ErrCtl = wst | spr | itc;
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if (itc && !wst && !spr) {
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env->hflags |= MIPS_HFLAG_ITC_CACHE;
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} else {
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env->hflags &= ~MIPS_HFLAG_ITC_CACHE;
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}
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}
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void helper_mtc0_taglo(CPUMIPSState *env, target_ulong arg1)
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{
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env->CP0_TagLo = arg1 & 0xFFFFFCF6;
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if (env->hflags & MIPS_HFLAG_ITC_CACHE) {
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/* If CACHE instruction is configured for ITC tags then make all
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CP0.TagLo bits writable. The actual write to ITC Configuration
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Tag will take care of the read-only bits. */
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env->CP0_TagLo = arg1;
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} else {
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env->CP0_TagLo = arg1 & 0xFFFFFCF6;
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}
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}
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void helper_mtc0_datalo(CPUMIPSState *env, target_ulong arg1)
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@ -3781,3 +3803,19 @@ MSA_ST_DF(DF_HALF, h, cpu_stw_data)
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MSA_ST_DF(DF_WORD, w, cpu_stl_data)
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MSA_ST_DF(DF_DOUBLE, d, cpu_stq_data)
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#endif
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void helper_cache(CPUMIPSState *env, target_ulong addr, uint32_t op)
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{
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#ifndef CONFIG_USER_ONLY
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target_ulong index = addr & 0x1fffffff;
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if (op == 9) {
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/* Index Store Tag */
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memory_region_dispatch_write(env->itc_tag, index, env->CP0_TagLo,
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8, MEMTXATTRS_UNSPECIFIED);
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} else if (op == 5) {
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/* Index Load Tag */
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memory_region_dispatch_read(env->itc_tag, index, &env->CP0_TagLo,
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8, MEMTXATTRS_UNSPECIFIED);
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}
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#endif
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}
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@ -5486,8 +5486,14 @@ static void gen_mfc0(DisasContext *ctx, TCGv arg, int reg, int sel)
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}
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break;
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case 26:
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tcg_gen_movi_tl(arg, 0); /* unimplemented */
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rn = "ECC";
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switch (sel) {
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case 0:
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gen_mfc0_load32(arg, offsetof(CPUMIPSState, CP0_ErrCtl));
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rn = "ErrCtl";
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break;
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default:
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goto cp0_unimplemented;
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}
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break;
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case 27:
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switch (sel) {
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@ -6136,8 +6142,15 @@ static void gen_mtc0(DisasContext *ctx, TCGv arg, int reg, int sel)
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}
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break;
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case 26:
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/* ignored */
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rn = "ECC";
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switch (sel) {
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case 0:
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gen_helper_mtc0_errctl(cpu_env, arg);
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ctx->bstate = BS_STOP;
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rn = "ErrCtl";
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break;
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default:
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goto cp0_unimplemented;
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}
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break;
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case 27:
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switch (sel) {
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@ -6762,8 +6775,14 @@ static void gen_dmfc0(DisasContext *ctx, TCGv arg, int reg, int sel)
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}
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break;
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case 26:
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tcg_gen_movi_tl(arg, 0); /* unimplemented */
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rn = "ECC";
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switch (sel) {
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case 0:
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gen_mfc0_load32(arg, offsetof(CPUMIPSState, CP0_ErrCtl));
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rn = "ErrCtl";
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break;
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default:
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goto cp0_unimplemented;
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}
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break;
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case 27:
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switch (sel) {
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@ -7404,8 +7423,15 @@ static void gen_dmtc0(DisasContext *ctx, TCGv arg, int reg, int sel)
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}
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break;
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case 26:
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/* ignored */
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rn = "ECC";
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switch (sel) {
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case 0:
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gen_helper_mtc0_errctl(cpu_env, arg);
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ctx->bstate = BS_STOP;
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rn = "ErrCtl";
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break;
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default:
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goto cp0_unimplemented;
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}
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break;
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case 27:
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switch (sel) {
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@ -11190,6 +11216,15 @@ static void gen_addiupc (DisasContext *ctx, int rx, int imm,
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tcg_temp_free(t0);
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}
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static void gen_cache_operation(DisasContext *ctx, uint32_t op, int base,
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int16_t offset)
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{
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TCGv_i32 t0 = tcg_const_i32(op);
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TCGv t1 = tcg_temp_new();
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gen_base_offset_addr(ctx, t1, base, offset);
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gen_helper_cache(cpu_env, t1, t0);
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}
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#if defined(TARGET_MIPS64)
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static void decode_i64_mips16 (DisasContext *ctx,
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int ry, int funct, int16_t offset,
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@ -13741,7 +13776,9 @@ static void decode_micromips32_opc(CPUMIPSState *env, DisasContext *ctx)
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switch (minor) {
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case CACHE:
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check_cp0_enabled(ctx);
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/* Treat as no-op. */
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if (ctx->hflags & MIPS_HFLAG_ITC_CACHE) {
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gen_cache_operation(ctx, rt, rs, imm);
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}
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break;
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case LWC2:
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case SWC2:
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@ -17195,7 +17232,9 @@ static void decode_opc_special3_r6(CPUMIPSState *env, DisasContext *ctx)
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break;
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case R6_OPC_CACHE:
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check_cp0_enabled(ctx);
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/* Treat as NOP. */
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if (ctx->hflags & MIPS_HFLAG_ITC_CACHE) {
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gen_cache_operation(ctx, rt, rs, imm);
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}
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break;
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case R6_OPC_SC:
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gen_st_cond(ctx, op1, rt, rs, imm);
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@ -19304,6 +19343,9 @@ static void decode_opc(CPUMIPSState *env, DisasContext *ctx)
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check_insn_opc_removed(ctx, ISA_MIPS32R6);
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check_cp0_enabled(ctx);
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check_insn(ctx, ISA_MIPS3 | ISA_MIPS32);
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if (ctx->hflags & MIPS_HFLAG_ITC_CACHE) {
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gen_cache_operation(ctx, rt, rs, imm);
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}
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/* Treat as NOP. */
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break;
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case OPC_PREF:
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