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hw/intc/grlib_irqmp: implements multicore irq

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Now there is an ncpus property, use it in order to deliver the IRQ to
multiple CPU.

Co-developed-by: Frederic Konrad <konrad.frederic@yahoo.fr>
Signed-off-by: Clément Chigot <chigot@adacore.com>
Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org>
Message-ID: <20240131085047.18458-5-chigot@adacore.com>
Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org>
This commit is contained in:
Clément Chigot 2024-01-31 09:50:42 +01:00 committed by Philippe Mathieu-Daudé
parent 7ed9a5f626
commit 0fa5cd4a60
3 changed files with 23 additions and 23 deletions
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41
hw/intc/grlib_irqmp.c
View File

@ -70,7 +70,7 @@ struct IRQMP {
unsigned int ncpus;
IRQMPState *state;
qemu_irq start_signal[IRQMP_MAX_CPU];
qemu_irq irq;
qemu_irq irq[IRQMP_MAX_CPU];
};
struct IRQMPState {
@ -89,37 +89,35 @@ struct IRQMPState {
static void grlib_irqmp_check_irqs(IRQMPState *state)
{
uint32_t pend = 0;
uint32_t level0 = 0;
uint32_t level1 = 0;
int i;
assert(state != NULL);
assert(state->parent != NULL);
/* IRQ for CPU 0 (no SMP support) */
pend = (state->pending | state->force[0])
& state->mask[0];
for (i = 0; i < state->parent->ncpus; i++) {
uint32_t pend = (state->pending | state->force[i]) & state->mask[i];
uint32_t level0 = pend & ~state->level;
uint32_t level1 = pend & state->level;
level0 = pend & ~state->level;
level1 = pend & state->level;
trace_grlib_irqmp_check_irqs(state->pending, state->force[i],
state->mask[i], level1, level0);
trace_grlib_irqmp_check_irqs(state->pending, state->force[0],
state->mask[0], level1, level0);
/* Trigger level1 interrupt first and level0 if there is no level1 */
qemu_set_irq(state->parent->irq, level1 ?: level0);
/* Trigger level1 interrupt first and level0 if there is no level1 */
qemu_set_irq(state->parent->irq[i], level1 ?: level0);
}
}
static void grlib_irqmp_ack_mask(IRQMPState *state, uint32_t mask)
static void grlib_irqmp_ack_mask(IRQMPState *state, unsigned int cpu,
uint32_t mask)
{
/* Clear registers */
state->pending &= ~mask;
state->force[0] &= ~mask; /* Only CPU 0 (No SMP support) */
state->force[cpu] &= ~mask;
grlib_irqmp_check_irqs(state);
}
void grlib_irqmp_ack(DeviceState *dev, int intno)
void grlib_irqmp_ack(DeviceState *dev, unsigned int cpu, int intno)
{
IRQMP *irqmp = GRLIB_IRQMP(dev);
IRQMPState *state;
@ -133,7 +131,7 @@ void grlib_irqmp_ack(DeviceState *dev, int intno)
trace_grlib_irqmp_ack(intno);
grlib_irqmp_ack_mask(state, mask);
grlib_irqmp_ack_mask(state, cpu, mask);
}
static void grlib_irqmp_set_irq(void *opaque, int irq, int level)
@ -159,7 +157,6 @@ static void grlib_irqmp_set_irq(void *opaque, int irq, int level)
s->pending |= 1 << irq;
}
grlib_irqmp_check_irqs(s);
}
}
@ -263,7 +260,9 @@ static void grlib_irqmp_write(void *opaque, hwaddr addr,
case CLEAR_OFFSET:
value &= ~1; /* clean up the value */
grlib_irqmp_ack_mask(state, value);
for (i = 0; i < irqmp->ncpus; i++) {
grlib_irqmp_ack_mask(state, i, value);
}
return;
case MP_STATUS_OFFSET:
@ -367,7 +366,7 @@ static void grlib_irqmp_realize(DeviceState *dev, Error **errp)
*/
qdev_init_gpio_out_named(dev, irqmp->start_signal, "grlib-start-cpu",
IRQMP_MAX_CPU);
qdev_init_gpio_out_named(dev, &irqmp->irq, "grlib-irq", 1);
qdev_init_gpio_out_named(dev, irqmp->irq, "grlib-irq", irqmp->ncpus);
memory_region_init_io(&irqmp->iomem, OBJECT(dev), &grlib_irqmp_ops, irqmp,
"irqmp", IRQMP_REG_SIZE);

3
hw/sparc/leon3.c
View File

@ -169,7 +169,8 @@ static void leon3_cache_control_int(CPUSPARCState *env)
static void leon3_irq_ack(CPUSPARCState *env, int intno)
{
grlib_irqmp_ack(env->irq_manager, intno);
/* No SMP support yet, only CPU #0 available so far. */
grlib_irqmp_ack(env->irq_manager, 0, intno);
}
/*

2
include/hw/intc/grlib_irqmp.h
View File

@ -36,6 +36,6 @@
/* IRQMP */
#define TYPE_GRLIB_IRQMP "grlib-irqmp"
void grlib_irqmp_ack(DeviceState *dev, int intno);
void grlib_irqmp_ack(DeviceState *dev, unsigned int cpu, int intno);
#endif /* GRLIB_IRQMP_H */