hw/arm/smmuv3: Skeleton
This patch implements a skeleton for the smmuv3 device. Datatypes and register definitions are introduced. The MMIO region, the interrupts and the queue are initialized. Only the MMIO read operation is implemented here. Signed-off-by: Prem Mallappa <prem.mallappa@broadcom.com> Signed-off-by: Eric Auger <eric.auger@redhat.com> Reviewed-by: Peter Maydell <peter.maydell@linaro.org> Message-id: 1524665762-31355-5-git-send-email-eric.auger@redhat.com Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
This commit is contained in:
Prem Mallappa
Peter Maydell
parent
93641948d4
commit
10a83cb988
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@ -35,4 +35,4 @@ obj-$(CONFIG_MPS2) += mps2-tz.o
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obj-$(CONFIG_MSF2) += msf2-soc.o msf2-som.o
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obj-$(CONFIG_IOTKIT) += iotkit.o
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obj-$(CONFIG_FSL_IMX7) += fsl-imx7.o mcimx7d-sabre.o
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obj-$(CONFIG_ARM_SMMUV3) += smmu-common.o
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obj-$(CONFIG_ARM_SMMUV3) += smmu-common.o smmuv3.o
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@ -0,0 +1,142 @@
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/*
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* ARM SMMUv3 support - Internal API
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*
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* Copyright (C) 2014-2016 Broadcom Corporation
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* Copyright (c) 2017 Red Hat, Inc.
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* Written by Prem Mallappa, Eric Auger
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License version 2 as
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* published by the Free Software Foundation.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*
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* You should have received a copy of the GNU General Public License along
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* with this program; if not, see <http://www.gnu.org/licenses/>.
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*/
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#ifndef HW_ARM_SMMU_V3_INTERNAL_H
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#define HW_ARM_SMMU_V3_INTERNAL_H
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#include "hw/arm/smmu-common.h"
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/* MMIO Registers */
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REG32(IDR0, 0x0)
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FIELD(IDR0, S1P, 1 , 1)
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FIELD(IDR0, TTF, 2 , 2)
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FIELD(IDR0, COHACC, 4 , 1)
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FIELD(IDR0, ASID16, 12, 1)
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FIELD(IDR0, TTENDIAN, 21, 2)
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FIELD(IDR0, STALL_MODEL, 24, 2)
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FIELD(IDR0, TERM_MODEL, 26, 1)
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FIELD(IDR0, STLEVEL, 27, 2)
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REG32(IDR1, 0x4)
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FIELD(IDR1, SIDSIZE, 0 , 6)
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FIELD(IDR1, EVENTQS, 16, 5)
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FIELD(IDR1, CMDQS, 21, 5)
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#define SMMU_IDR1_SIDSIZE 16
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#define SMMU_CMDQS 19
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#define SMMU_EVENTQS 19
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REG32(IDR2, 0x8)
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REG32(IDR3, 0xc)
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REG32(IDR4, 0x10)
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REG32(IDR5, 0x14)
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FIELD(IDR5, OAS, 0, 3);
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FIELD(IDR5, GRAN4K, 4, 1);
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FIELD(IDR5, GRAN16K, 5, 1);
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FIELD(IDR5, GRAN64K, 6, 1);
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#define SMMU_IDR5_OAS 4
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REG32(IIDR, 0x1c)
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REG32(CR0, 0x20)
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FIELD(CR0, SMMU_ENABLE, 0, 1)
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FIELD(CR0, EVENTQEN, 2, 1)
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FIELD(CR0, CMDQEN, 3, 1)
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REG32(CR0ACK, 0x24)
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REG32(CR1, 0x28)
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REG32(CR2, 0x2c)
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REG32(STATUSR, 0x40)
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REG32(IRQ_CTRL, 0x50)
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FIELD(IRQ_CTRL, GERROR_IRQEN, 0, 1)
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FIELD(IRQ_CTRL, PRI_IRQEN, 1, 1)
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FIELD(IRQ_CTRL, EVENTQ_IRQEN, 2, 1)
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REG32(IRQ_CTRL_ACK, 0x54)
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REG32(GERROR, 0x60)
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FIELD(GERROR, CMDQ_ERR, 0, 1)
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FIELD(GERROR, EVENTQ_ABT_ERR, 2, 1)
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FIELD(GERROR, PRIQ_ABT_ERR, 3, 1)
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FIELD(GERROR, MSI_CMDQ_ABT_ERR, 4, 1)
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FIELD(GERROR, MSI_EVENTQ_ABT_ERR, 5, 1)
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FIELD(GERROR, MSI_PRIQ_ABT_ERR, 6, 1)
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FIELD(GERROR, MSI_GERROR_ABT_ERR, 7, 1)
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FIELD(GERROR, MSI_SFM_ERR, 8, 1)
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REG32(GERRORN, 0x64)
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#define A_GERROR_IRQ_CFG0 0x68 /* 64b */
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REG32(GERROR_IRQ_CFG1, 0x70)
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REG32(GERROR_IRQ_CFG2, 0x74)
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#define A_STRTAB_BASE 0x80 /* 64b */
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#define SMMU_BASE_ADDR_MASK 0xffffffffffe0
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REG32(STRTAB_BASE_CFG, 0x88)
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FIELD(STRTAB_BASE_CFG, FMT, 16, 2)
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FIELD(STRTAB_BASE_CFG, SPLIT, 6 , 5)
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FIELD(STRTAB_BASE_CFG, LOG2SIZE, 0 , 6)
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#define A_CMDQ_BASE 0x90 /* 64b */
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REG32(CMDQ_PROD, 0x98)
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REG32(CMDQ_CONS, 0x9c)
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FIELD(CMDQ_CONS, ERR, 24, 7)
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#define A_EVENTQ_BASE 0xa0 /* 64b */
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REG32(EVENTQ_PROD, 0xa8)
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REG32(EVENTQ_CONS, 0xac)
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#define A_EVENTQ_IRQ_CFG0 0xb0 /* 64b */
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REG32(EVENTQ_IRQ_CFG1, 0xb8)
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REG32(EVENTQ_IRQ_CFG2, 0xbc)
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#define A_IDREGS 0xfd0
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static inline int smmu_enabled(SMMUv3State *s)
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{
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return FIELD_EX32(s->cr[0], CR0, SMMU_ENABLE);
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}
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/* Command Queue Entry */
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typedef struct Cmd {
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uint32_t word[4];
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} Cmd;
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/* Event Queue Entry */
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typedef struct Evt {
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uint32_t word[8];
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} Evt;
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static inline uint32_t smmuv3_idreg(int regoffset)
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{
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/*
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* Return the value of the Primecell/Corelink ID registers at the
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* specified offset from the first ID register.
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* These value indicate an ARM implementation of MMU600 p1
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*/
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static const uint8_t smmuv3_ids[] = {
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0x04, 0, 0, 0, 0x84, 0xB4, 0xF0, 0x10, 0x0D, 0xF0, 0x05, 0xB1
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};
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return smmuv3_ids[regoffset / 4];
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}
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#endif
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@ -0,0 +1,366 @@
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/*
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* Copyright (C) 2014-2016 Broadcom Corporation
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* Copyright (c) 2017 Red Hat, Inc.
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* Written by Prem Mallappa, Eric Auger
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License version 2 as
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* published by the Free Software Foundation.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*
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* You should have received a copy of the GNU General Public License along
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* with this program; if not, see <http://www.gnu.org/licenses/>.
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*/
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#include "qemu/osdep.h"
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#include "hw/boards.h"
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#include "sysemu/sysemu.h"
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#include "hw/sysbus.h"
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#include "hw/qdev-core.h"
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#include "hw/pci/pci.h"
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#include "exec/address-spaces.h"
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#include "trace.h"
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#include "qemu/log.h"
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#include "qemu/error-report.h"
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#include "qapi/error.h"
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#include "hw/arm/smmuv3.h"
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#include "smmuv3-internal.h"
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static void smmuv3_init_regs(SMMUv3State *s)
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{
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/**
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* IDR0: stage1 only, AArch64 only, coherent access, 16b ASID,
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* multi-level stream table
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*/
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s->idr[0] = FIELD_DP32(s->idr[0], IDR0, S1P, 1); /* stage 1 supported */
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s->idr[0] = FIELD_DP32(s->idr[0], IDR0, TTF, 2); /* AArch64 PTW only */
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s->idr[0] = FIELD_DP32(s->idr[0], IDR0, COHACC, 1); /* IO coherent */
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s->idr[0] = FIELD_DP32(s->idr[0], IDR0, ASID16, 1); /* 16-bit ASID */
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s->idr[0] = FIELD_DP32(s->idr[0], IDR0, TTENDIAN, 2); /* little endian */
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s->idr[0] = FIELD_DP32(s->idr[0], IDR0, STALL_MODEL, 1); /* No stall */
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/* terminated transaction will always be aborted/error returned */
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s->idr[0] = FIELD_DP32(s->idr[0], IDR0, TERM_MODEL, 1);
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/* 2-level stream table supported */
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s->idr[0] = FIELD_DP32(s->idr[0], IDR0, STLEVEL, 1);
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s->idr[1] = FIELD_DP32(s->idr[1], IDR1, SIDSIZE, SMMU_IDR1_SIDSIZE);
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s->idr[1] = FIELD_DP32(s->idr[1], IDR1, EVENTQS, SMMU_EVENTQS);
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s->idr[1] = FIELD_DP32(s->idr[1], IDR1, CMDQS, SMMU_CMDQS);
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/* 4K and 64K granule support */
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s->idr[5] = FIELD_DP32(s->idr[5], IDR5, GRAN4K, 1);
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s->idr[5] = FIELD_DP32(s->idr[5], IDR5, GRAN64K, 1);
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s->idr[5] = FIELD_DP32(s->idr[5], IDR5, OAS, SMMU_IDR5_OAS); /* 44 bits */
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s->cmdq.base = deposit64(s->cmdq.base, 0, 5, SMMU_CMDQS);
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s->cmdq.prod = 0;
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s->cmdq.cons = 0;
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s->cmdq.entry_size = sizeof(struct Cmd);
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s->eventq.base = deposit64(s->eventq.base, 0, 5, SMMU_EVENTQS);
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s->eventq.prod = 0;
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s->eventq.cons = 0;
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s->eventq.entry_size = sizeof(struct Evt);
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s->features = 0;
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s->sid_split = 0;
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}
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static MemTxResult smmu_write_mmio(void *opaque, hwaddr offset, uint64_t data,
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unsigned size, MemTxAttrs attrs)
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{
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/* not yet implemented */
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return MEMTX_ERROR;
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}
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static MemTxResult smmu_readll(SMMUv3State *s, hwaddr offset,
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uint64_t *data, MemTxAttrs attrs)
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{
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switch (offset) {
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case A_GERROR_IRQ_CFG0:
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*data = s->gerror_irq_cfg0;
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return MEMTX_OK;
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case A_STRTAB_BASE:
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*data = s->strtab_base;
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return MEMTX_OK;
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case A_CMDQ_BASE:
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*data = s->cmdq.base;
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return MEMTX_OK;
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case A_EVENTQ_BASE:
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*data = s->eventq.base;
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return MEMTX_OK;
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default:
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*data = 0;
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qemu_log_mask(LOG_UNIMP,
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"%s Unexpected 64-bit access to 0x%"PRIx64" (RAZ)\n",
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__func__, offset);
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return MEMTX_OK;
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}
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}
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static MemTxResult smmu_readl(SMMUv3State *s, hwaddr offset,
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uint64_t *data, MemTxAttrs attrs)
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{
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switch (offset) {
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case A_IDREGS ... A_IDREGS + 0x1f:
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*data = smmuv3_idreg(offset - A_IDREGS);
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return MEMTX_OK;
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case A_IDR0 ... A_IDR5:
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*data = s->idr[(offset - A_IDR0) / 4];
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return MEMTX_OK;
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case A_IIDR:
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*data = s->iidr;
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return MEMTX_OK;
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case A_CR0:
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*data = s->cr[0];
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return MEMTX_OK;
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case A_CR0ACK:
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*data = s->cr0ack;
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return MEMTX_OK;
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case A_CR1:
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*data = s->cr[1];
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return MEMTX_OK;
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case A_CR2:
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*data = s->cr[2];
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return MEMTX_OK;
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case A_STATUSR:
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*data = s->statusr;
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return MEMTX_OK;
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case A_IRQ_CTRL:
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case A_IRQ_CTRL_ACK:
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*data = s->irq_ctrl;
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return MEMTX_OK;
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case A_GERROR:
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*data = s->gerror;
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return MEMTX_OK;
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case A_GERRORN:
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*data = s->gerrorn;
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return MEMTX_OK;
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case A_GERROR_IRQ_CFG0: /* 64b */
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*data = extract64(s->gerror_irq_cfg0, 0, 32);
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return MEMTX_OK;
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case A_GERROR_IRQ_CFG0 + 4:
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*data = extract64(s->gerror_irq_cfg0, 32, 32);
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return MEMTX_OK;
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case A_GERROR_IRQ_CFG1:
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*data = s->gerror_irq_cfg1;
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return MEMTX_OK;
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case A_GERROR_IRQ_CFG2:
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*data = s->gerror_irq_cfg2;
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return MEMTX_OK;
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case A_STRTAB_BASE: /* 64b */
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*data = extract64(s->strtab_base, 0, 32);
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return MEMTX_OK;
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case A_STRTAB_BASE + 4: /* 64b */
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*data = extract64(s->strtab_base, 32, 32);
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return MEMTX_OK;
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case A_STRTAB_BASE_CFG:
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*data = s->strtab_base_cfg;
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return MEMTX_OK;
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case A_CMDQ_BASE: /* 64b */
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*data = extract64(s->cmdq.base, 0, 32);
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return MEMTX_OK;
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case A_CMDQ_BASE + 4:
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*data = extract64(s->cmdq.base, 32, 32);
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return MEMTX_OK;
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case A_CMDQ_PROD:
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*data = s->cmdq.prod;
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return MEMTX_OK;
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case A_CMDQ_CONS:
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*data = s->cmdq.cons;
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return MEMTX_OK;
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case A_EVENTQ_BASE: /* 64b */
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*data = extract64(s->eventq.base, 0, 32);
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return MEMTX_OK;
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case A_EVENTQ_BASE + 4: /* 64b */
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*data = extract64(s->eventq.base, 32, 32);
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return MEMTX_OK;
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case A_EVENTQ_PROD:
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*data = s->eventq.prod;
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return MEMTX_OK;
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case A_EVENTQ_CONS:
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*data = s->eventq.cons;
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return MEMTX_OK;
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default:
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*data = 0;
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qemu_log_mask(LOG_UNIMP,
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"%s unhandled 32-bit access at 0x%"PRIx64" (RAZ)\n",
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__func__, offset);
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return MEMTX_OK;
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}
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}
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static MemTxResult smmu_read_mmio(void *opaque, hwaddr offset, uint64_t *data,
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unsigned size, MemTxAttrs attrs)
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{
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SMMUState *sys = opaque;
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SMMUv3State *s = ARM_SMMUV3(sys);
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MemTxResult r;
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/* CONSTRAINED UNPREDICTABLE choice to have page0/1 be exact aliases */
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offset &= ~0x10000;
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switch (size) {
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case 8:
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r = smmu_readll(s, offset, data, attrs);
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break;
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case 4:
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r = smmu_readl(s, offset, data, attrs);
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break;
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default:
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r = MEMTX_ERROR;
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break;
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}
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trace_smmuv3_read_mmio(offset, *data, size, r);
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return r;
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}
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static const MemoryRegionOps smmu_mem_ops = {
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.read_with_attrs = smmu_read_mmio,
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.write_with_attrs = smmu_write_mmio,
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.endianness = DEVICE_LITTLE_ENDIAN,
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.valid = {
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.min_access_size = 4,
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.max_access_size = 8,
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},
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.impl = {
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.min_access_size = 4,
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.max_access_size = 8,
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},
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};
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static void smmu_init_irq(SMMUv3State *s, SysBusDevice *dev)
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{
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int i;
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for (i = 0; i < ARRAY_SIZE(s->irq); i++) {
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sysbus_init_irq(dev, &s->irq[i]);
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}
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}
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static void smmu_reset(DeviceState *dev)
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{
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SMMUv3State *s = ARM_SMMUV3(dev);
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SMMUv3Class *c = ARM_SMMUV3_GET_CLASS(s);
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c->parent_reset(dev);
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smmuv3_init_regs(s);
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}
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static void smmu_realize(DeviceState *d, Error **errp)
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{
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SMMUState *sys = ARM_SMMU(d);
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SMMUv3State *s = ARM_SMMUV3(sys);
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SMMUv3Class *c = ARM_SMMUV3_GET_CLASS(s);
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SysBusDevice *dev = SYS_BUS_DEVICE(d);
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Error *local_err = NULL;
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c->parent_realize(d, &local_err);
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if (local_err) {
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error_propagate(errp, local_err);
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return;
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}
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|
||||
memory_region_init_io(&sys->iomem, OBJECT(s),
|
||||
&smmu_mem_ops, sys, TYPE_ARM_SMMUV3, 0x20000);
|
||||
|
||||
sys->mrtypename = TYPE_SMMUV3_IOMMU_MEMORY_REGION;
|
||||
|
||||
sysbus_init_mmio(dev, &sys->iomem);
|
||||
|
||||
smmu_init_irq(s, dev);
|
||||
}
|
||||
|
||||
static const VMStateDescription vmstate_smmuv3_queue = {
|
||||
.name = "smmuv3_queue",
|
||||
.version_id = 1,
|
||||
.minimum_version_id = 1,
|
||||
.fields = (VMStateField[]) {
|
||||
VMSTATE_UINT64(base, SMMUQueue),
|
||||
VMSTATE_UINT32(prod, SMMUQueue),
|
||||
VMSTATE_UINT32(cons, SMMUQueue),
|
||||
VMSTATE_UINT8(log2size, SMMUQueue),
|
||||
},
|
||||
};
|
||||
|
||||
static const VMStateDescription vmstate_smmuv3 = {
|
||||
.name = "smmuv3",
|
||||
.version_id = 1,
|
||||
.minimum_version_id = 1,
|
||||
.fields = (VMStateField[]) {
|
||||
VMSTATE_UINT32(features, SMMUv3State),
|
||||
VMSTATE_UINT8(sid_size, SMMUv3State),
|
||||
VMSTATE_UINT8(sid_split, SMMUv3State),
|
||||
|
||||
VMSTATE_UINT32_ARRAY(cr, SMMUv3State, 3),
|
||||
VMSTATE_UINT32(cr0ack, SMMUv3State),
|
||||
VMSTATE_UINT32(statusr, SMMUv3State),
|
||||
VMSTATE_UINT32(irq_ctrl, SMMUv3State),
|
||||
VMSTATE_UINT32(gerror, SMMUv3State),
|
||||
VMSTATE_UINT32(gerrorn, SMMUv3State),
|
||||
VMSTATE_UINT64(gerror_irq_cfg0, SMMUv3State),
|
||||
VMSTATE_UINT32(gerror_irq_cfg1, SMMUv3State),
|
||||
VMSTATE_UINT32(gerror_irq_cfg2, SMMUv3State),
|
||||
VMSTATE_UINT64(strtab_base, SMMUv3State),
|
||||
VMSTATE_UINT32(strtab_base_cfg, SMMUv3State),
|
||||
VMSTATE_UINT64(eventq_irq_cfg0, SMMUv3State),
|
||||
VMSTATE_UINT32(eventq_irq_cfg1, SMMUv3State),
|
||||
VMSTATE_UINT32(eventq_irq_cfg2, SMMUv3State),
|
||||
|
||||
VMSTATE_STRUCT(cmdq, SMMUv3State, 0, vmstate_smmuv3_queue, SMMUQueue),
|
||||
VMSTATE_STRUCT(eventq, SMMUv3State, 0, vmstate_smmuv3_queue, SMMUQueue),
|
||||
|
||||
VMSTATE_END_OF_LIST(),
|
||||
},
|
||||
};
|
||||
|
||||
static void smmuv3_instance_init(Object *obj)
|
||||
{
|
||||
/* Nothing much to do here as of now */
|
||||
}
|
||||
|
||||
static void smmuv3_class_init(ObjectClass *klass, void *data)
|
||||
{
|
||||
DeviceClass *dc = DEVICE_CLASS(klass);
|
||||
SMMUv3Class *c = ARM_SMMUV3_CLASS(klass);
|
||||
|
||||
dc->vmsd = &vmstate_smmuv3;
|
||||
device_class_set_parent_reset(dc, smmu_reset, &c->parent_reset);
|
||||
c->parent_realize = dc->realize;
|
||||
dc->realize = smmu_realize;
|
||||
}
|
||||
|
||||
static void smmuv3_iommu_memory_region_class_init(ObjectClass *klass,
|
||||
void *data)
|
||||
{
|
||||
}
|
||||
|
||||
static const TypeInfo smmuv3_type_info = {
|
||||
.name = TYPE_ARM_SMMUV3,
|
||||
.parent = TYPE_ARM_SMMU,
|
||||
.instance_size = sizeof(SMMUv3State),
|
||||
.instance_init = smmuv3_instance_init,
|
||||
.class_size = sizeof(SMMUv3Class),
|
||||
.class_init = smmuv3_class_init,
|
||||
};
|
||||
|
||||
static const TypeInfo smmuv3_iommu_memory_region_info = {
|
||||
.parent = TYPE_IOMMU_MEMORY_REGION,
|
||||
.name = TYPE_SMMUV3_IOMMU_MEMORY_REGION,
|
||||
.class_init = smmuv3_iommu_memory_region_class_init,
|
||||
};
|
||||
|
||||
static void smmuv3_register_types(void)
|
||||
{
|
||||
type_register(&smmuv3_type_info);
|
||||
type_register(&smmuv3_iommu_memory_region_info);
|
||||
}
|
||||
|
||||
type_init(smmuv3_register_types)
|
||||
|
||||
|
|
@ -12,3 +12,6 @@ smmu_ptw_invalid_pte(int stage, int level, uint64_t baseaddr, uint64_t pteaddr,
|
|||
smmu_ptw_page_pte(int stage, int level, uint64_t iova, uint64_t baseaddr, uint64_t pteaddr, uint64_t pte, uint64_t address) "stage=%d level=%d iova=0x%"PRIx64" base@=0x%"PRIx64" pte@=0x%"PRIx64" pte=0x%"PRIx64" page address = 0x%"PRIx64
|
||||
smmu_ptw_block_pte(int stage, int level, uint64_t baseaddr, uint64_t pteaddr, uint64_t pte, uint64_t iova, uint64_t gpa, int bsize_mb) "stage=%d level=%d base@=0x%"PRIx64" pte@=0x%"PRIx64" pte=0x%"PRIx64" iova=0x%"PRIx64" block address = 0x%"PRIx64" block size = %d MiB"
|
||||
smmu_get_pte(uint64_t baseaddr, int index, uint64_t pteaddr, uint64_t pte) "baseaddr=0x%"PRIx64" index=0x%x, pteaddr=0x%"PRIx64", pte=0x%"PRIx64
|
||||
|
||||
#hw/arm/smmuv3.c
|
||||
smmuv3_read_mmio(uint64_t addr, uint64_t val, unsigned size, uint32_t r) "addr: 0x%"PRIx64" val:0x%"PRIx64" size: 0x%x(%d)"
|
||||
|
|
|
|||
|
|
@ -0,0 +1,87 @@
|
|||
/*
|
||||
* Copyright (C) 2014-2016 Broadcom Corporation
|
||||
* Copyright (c) 2017 Red Hat, Inc.
|
||||
* Written by Prem Mallappa, Eric Auger
|
||||
*
|
||||
* This program is free software; you can redistribute it and/or modify
|
||||
* it under the terms of the GNU General Public License version 2 as
|
||||
* published by the Free Software Foundation.
|
||||
*
|
||||
* This program is distributed in the hope that it will be useful,
|
||||
* but WITHOUT ANY WARRANTY; without even the implied warranty of
|
||||
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
|
||||
* GNU General Public License for more details.
|
||||
*
|
||||
* You should have received a copy of the GNU General Public License along
|
||||
* with this program; if not, see <http://www.gnu.org/licenses/>.
|
||||
*/
|
||||
|
||||
#ifndef HW_ARM_SMMUV3_H
|
||||
#define HW_ARM_SMMUV3_H
|
||||
|
||||
#include "hw/arm/smmu-common.h"
|
||||
#include "hw/registerfields.h"
|
||||
|
||||
#define TYPE_SMMUV3_IOMMU_MEMORY_REGION "smmuv3-iommu-memory-region"
|
||||
|
||||
typedef struct SMMUQueue {
|
||||
uint64_t base; /* base register */
|
||||
uint32_t prod;
|
||||
uint32_t cons;
|
||||
uint8_t entry_size;
|
||||
uint8_t log2size;
|
||||
} SMMUQueue;
|
||||
|
||||
typedef struct SMMUv3State {
|
||||
SMMUState smmu_state;
|
||||
|
||||
uint32_t features;
|
||||
uint8_t sid_size;
|
||||
uint8_t sid_split;
|
||||
|
||||
uint32_t idr[6];
|
||||
uint32_t iidr;
|
||||
uint32_t cr[3];
|
||||
uint32_t cr0ack;
|
||||
uint32_t statusr;
|
||||
uint32_t irq_ctrl;
|
||||
uint32_t gerror;
|
||||
uint32_t gerrorn;
|
||||
uint64_t gerror_irq_cfg0;
|
||||
uint32_t gerror_irq_cfg1;
|
||||
uint32_t gerror_irq_cfg2;
|
||||
uint64_t strtab_base;
|
||||
uint32_t strtab_base_cfg;
|
||||
uint64_t eventq_irq_cfg0;
|
||||
uint32_t eventq_irq_cfg1;
|
||||
uint32_t eventq_irq_cfg2;
|
||||
|
||||
SMMUQueue eventq, cmdq;
|
||||
|
||||
qemu_irq irq[4];
|
||||
} SMMUv3State;
|
||||
|
||||
typedef enum {
|
||||
SMMU_IRQ_EVTQ,
|
||||
SMMU_IRQ_PRIQ,
|
||||
SMMU_IRQ_CMD_SYNC,
|
||||
SMMU_IRQ_GERROR,
|
||||
} SMMUIrq;
|
||||
|
||||
typedef struct {
|
||||
/*< private >*/
|
||||
SMMUBaseClass smmu_base_class;
|
||||
/*< public >*/
|
||||
|
||||
DeviceRealize parent_realize;
|
||||
DeviceReset parent_reset;
|
||||
} SMMUv3Class;
|
||||
|
||||
#define TYPE_ARM_SMMUV3 "arm-smmuv3"
|
||||
#define ARM_SMMUV3(obj) OBJECT_CHECK(SMMUv3State, (obj), TYPE_ARM_SMMUV3)
|
||||
#define ARM_SMMUV3_CLASS(klass) \
|
||||
OBJECT_CLASS_CHECK(SMMUv3Class, (klass), TYPE_ARM_SMMUV3)
|
||||
#define ARM_SMMUV3_GET_CLASS(obj) \
|
||||
OBJECT_GET_CLASS(SMMUv3Class, (obj), TYPE_ARM_SMMUV3)
|
||||
|
||||
#endif
|
||||
Loading…
Reference in New Issue