target/riscv: Specify the XLEN for CPUs
Signed-off-by: Alistair Francis <alistair.francis@wdc.com> Reviewed-by: Bin Meng <bin.meng@windriver.com> Tested-by: Bin Meng <bin.meng@windriver.com> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Reviewed-by: Palmer Dabbelt <palmerdabbelt@google.com> Acked-by: Palmer Dabbelt <palmerdabbelt@google.com> Message-id: c1da66affbb83ec4a2fbeb0194293bd24d65f5dc.1608142916.git.alistair.francis@wdc.com
This commit is contained in:
parent
51ae0cabc6
commit
114baaca51
|
@ -158,22 +158,36 @@ static void riscv_base_cpu_init(Object *obj)
|
||||||
set_misa(env, 0);
|
set_misa(env, 0);
|
||||||
}
|
}
|
||||||
|
|
||||||
static void rvxx_sifive_u_cpu_init(Object *obj)
|
#ifdef TARGET_RISCV64
|
||||||
|
static void rv64_sifive_u_cpu_init(Object *obj)
|
||||||
{
|
{
|
||||||
CPURISCVState *env = &RISCV_CPU(obj)->env;
|
CPURISCVState *env = &RISCV_CPU(obj)->env;
|
||||||
set_misa(env, RVXLEN | RVI | RVM | RVA | RVF | RVD | RVC | RVS | RVU);
|
set_misa(env, RV64 | RVI | RVM | RVA | RVF | RVD | RVC | RVS | RVU);
|
||||||
set_priv_version(env, PRIV_VERSION_1_10_0);
|
set_priv_version(env, PRIV_VERSION_1_10_0);
|
||||||
}
|
}
|
||||||
|
|
||||||
static void rvxx_sifive_e_cpu_init(Object *obj)
|
static void rv64_sifive_e_cpu_init(Object *obj)
|
||||||
{
|
{
|
||||||
CPURISCVState *env = &RISCV_CPU(obj)->env;
|
CPURISCVState *env = &RISCV_CPU(obj)->env;
|
||||||
set_misa(env, RVXLEN | RVI | RVM | RVA | RVC | RVU);
|
set_misa(env, RV64 | RVI | RVM | RVA | RVC | RVU);
|
||||||
set_priv_version(env, PRIV_VERSION_1_10_0);
|
set_priv_version(env, PRIV_VERSION_1_10_0);
|
||||||
qdev_prop_set_bit(DEVICE(obj), "mmu", false);
|
qdev_prop_set_bit(DEVICE(obj), "mmu", false);
|
||||||
}
|
}
|
||||||
|
#else
|
||||||
|
static void rv32_sifive_u_cpu_init(Object *obj)
|
||||||
|
{
|
||||||
|
CPURISCVState *env = &RISCV_CPU(obj)->env;
|
||||||
|
set_misa(env, RV32 | RVI | RVM | RVA | RVF | RVD | RVC | RVS | RVU);
|
||||||
|
set_priv_version(env, PRIV_VERSION_1_10_0);
|
||||||
|
}
|
||||||
|
|
||||||
#if defined(TARGET_RISCV32)
|
static void rv32_sifive_e_cpu_init(Object *obj)
|
||||||
|
{
|
||||||
|
CPURISCVState *env = &RISCV_CPU(obj)->env;
|
||||||
|
set_misa(env, RV32 | RVI | RVM | RVA | RVC | RVU);
|
||||||
|
set_priv_version(env, PRIV_VERSION_1_10_0);
|
||||||
|
qdev_prop_set_bit(DEVICE(obj), "mmu", false);
|
||||||
|
}
|
||||||
|
|
||||||
static void rv32_ibex_cpu_init(Object *obj)
|
static void rv32_ibex_cpu_init(Object *obj)
|
||||||
{
|
{
|
||||||
|
@ -191,7 +205,6 @@ static void rv32_imafcu_nommu_cpu_init(Object *obj)
|
||||||
set_resetvec(env, DEFAULT_RSTVEC);
|
set_resetvec(env, DEFAULT_RSTVEC);
|
||||||
qdev_prop_set_bit(DEVICE(obj), "mmu", false);
|
qdev_prop_set_bit(DEVICE(obj), "mmu", false);
|
||||||
}
|
}
|
||||||
|
|
||||||
#endif
|
#endif
|
||||||
|
|
||||||
static ObjectClass *riscv_cpu_class_by_name(const char *cpu_model)
|
static ObjectClass *riscv_cpu_class_by_name(const char *cpu_model)
|
||||||
|
@ -643,13 +656,13 @@ static const TypeInfo riscv_cpu_type_infos[] = {
|
||||||
#if defined(TARGET_RISCV32)
|
#if defined(TARGET_RISCV32)
|
||||||
DEFINE_CPU(TYPE_RISCV_CPU_BASE32, riscv_base_cpu_init),
|
DEFINE_CPU(TYPE_RISCV_CPU_BASE32, riscv_base_cpu_init),
|
||||||
DEFINE_CPU(TYPE_RISCV_CPU_IBEX, rv32_ibex_cpu_init),
|
DEFINE_CPU(TYPE_RISCV_CPU_IBEX, rv32_ibex_cpu_init),
|
||||||
DEFINE_CPU(TYPE_RISCV_CPU_SIFIVE_E31, rvxx_sifive_e_cpu_init),
|
DEFINE_CPU(TYPE_RISCV_CPU_SIFIVE_E31, rv32_sifive_e_cpu_init),
|
||||||
DEFINE_CPU(TYPE_RISCV_CPU_SIFIVE_E34, rv32_imafcu_nommu_cpu_init),
|
DEFINE_CPU(TYPE_RISCV_CPU_SIFIVE_E34, rv32_imafcu_nommu_cpu_init),
|
||||||
DEFINE_CPU(TYPE_RISCV_CPU_SIFIVE_U34, rvxx_sifive_u_cpu_init),
|
DEFINE_CPU(TYPE_RISCV_CPU_SIFIVE_U34, rv32_sifive_u_cpu_init),
|
||||||
#elif defined(TARGET_RISCV64)
|
#elif defined(TARGET_RISCV64)
|
||||||
DEFINE_CPU(TYPE_RISCV_CPU_BASE64, riscv_base_cpu_init),
|
DEFINE_CPU(TYPE_RISCV_CPU_BASE64, riscv_base_cpu_init),
|
||||||
DEFINE_CPU(TYPE_RISCV_CPU_SIFIVE_E51, rvxx_sifive_e_cpu_init),
|
DEFINE_CPU(TYPE_RISCV_CPU_SIFIVE_E51, rv64_sifive_e_cpu_init),
|
||||||
DEFINE_CPU(TYPE_RISCV_CPU_SIFIVE_U54, rvxx_sifive_u_cpu_init),
|
DEFINE_CPU(TYPE_RISCV_CPU_SIFIVE_U54, rv64_sifive_u_cpu_init),
|
||||||
#endif
|
#endif
|
||||||
};
|
};
|
||||||
|
|
||||||
|
|
Loading…
Reference in New Issue