target/i386: Combine 5 sets of variables in mmu_translate
We don't need one variable set per translation level, which requires copying into pte/pte_addr for huge pages. Standardize on pte/pte_addr for all levels. Signed-off-by: Richard Henderson <richard.henderson@linaro.org> Message-Id: <20221002172956.265735-8-richard.henderson@linaro.org> Signed-off-by: Paolo Bonzini <pbonzini@redhat.com>
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@ -82,7 +82,7 @@ static bool mmu_translate(CPUX86State *env, const TranslateParams *in,
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const bool is_user = (in->mmu_idx == MMU_USER_IDX);
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const MMUAccessType access_type = in->access_type;
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uint64_t ptep, pte;
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hwaddr pde_addr, pte_addr;
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hwaddr pte_addr;
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uint64_t rsvd_mask = PG_ADDRESS_MASK & ~MAKE_64BIT_MASK(0, cpu->phys_bits);
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uint32_t pkr;
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int page_size;
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@ -92,116 +92,122 @@ static bool mmu_translate(CPUX86State *env, const TranslateParams *in,
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}
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if (pg_mode & PG_MODE_PAE) {
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uint64_t pde, pdpe;
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target_ulong pdpe_addr;
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#ifdef TARGET_X86_64
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if (pg_mode & PG_MODE_LMA) {
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bool la57 = pg_mode & PG_MODE_LA57;
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uint64_t pml5e_addr, pml5e;
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uint64_t pml4e_addr, pml4e;
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if (la57) {
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pml5e_addr = ((in->cr3 & ~0xfff) +
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(((addr >> 48) & 0x1ff) << 3)) & a20_mask;
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PTE_HPHYS(pml5e_addr);
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pml5e = x86_ldq_phys(cs, pml5e_addr);
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if (!(pml5e & PG_PRESENT_MASK)) {
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if (pg_mode & PG_MODE_LA57) {
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/*
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* Page table level 5
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*/
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pte_addr = ((in->cr3 & ~0xfff) +
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(((addr >> 48) & 0x1ff) << 3)) & a20_mask;
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PTE_HPHYS(pte_addr);
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pte = x86_ldq_phys(cs, pte_addr);
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if (!(pte & PG_PRESENT_MASK)) {
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goto do_fault;
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}
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if (pml5e & (rsvd_mask | PG_PSE_MASK)) {
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if (pte & (rsvd_mask | PG_PSE_MASK)) {
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goto do_fault_rsvd;
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}
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if (!(pml5e & PG_ACCESSED_MASK)) {
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pml5e |= PG_ACCESSED_MASK;
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x86_stl_phys_notdirty(cs, pml5e_addr, pml5e);
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if (!(pte & PG_ACCESSED_MASK)) {
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pte |= PG_ACCESSED_MASK;
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x86_stl_phys_notdirty(cs, pte_addr, pte);
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}
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ptep = pml5e ^ PG_NX_MASK;
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ptep = pte ^ PG_NX_MASK;
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} else {
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pml5e = in->cr3;
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pte = in->cr3;
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ptep = PG_NX_MASK | PG_USER_MASK | PG_RW_MASK;
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}
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pml4e_addr = ((pml5e & PG_ADDRESS_MASK) +
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(((addr >> 39) & 0x1ff) << 3)) & a20_mask;
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PTE_HPHYS(pml4e_addr);
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pml4e = x86_ldq_phys(cs, pml4e_addr);
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if (!(pml4e & PG_PRESENT_MASK)) {
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/*
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* Page table level 4
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*/
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pte_addr = ((pte & PG_ADDRESS_MASK) +
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(((addr >> 39) & 0x1ff) << 3)) & a20_mask;
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PTE_HPHYS(pte_addr);
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pte = x86_ldq_phys(cs, pte_addr);
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if (!(pte & PG_PRESENT_MASK)) {
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goto do_fault;
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}
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if (pml4e & (rsvd_mask | PG_PSE_MASK)) {
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if (pte & (rsvd_mask | PG_PSE_MASK)) {
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goto do_fault_rsvd;
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}
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if (!(pml4e & PG_ACCESSED_MASK)) {
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pml4e |= PG_ACCESSED_MASK;
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x86_stl_phys_notdirty(cs, pml4e_addr, pml4e);
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if (!(pte & PG_ACCESSED_MASK)) {
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pte |= PG_ACCESSED_MASK;
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x86_stl_phys_notdirty(cs, pte_addr, pte);
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}
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ptep &= pml4e ^ PG_NX_MASK;
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pdpe_addr = ((pml4e & PG_ADDRESS_MASK) + (((addr >> 30) & 0x1ff) << 3)) &
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a20_mask;
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PTE_HPHYS(pdpe_addr);
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pdpe = x86_ldq_phys(cs, pdpe_addr);
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if (!(pdpe & PG_PRESENT_MASK)) {
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ptep &= pte ^ PG_NX_MASK;
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/*
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* Page table level 3
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*/
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pte_addr = ((pte & PG_ADDRESS_MASK) +
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(((addr >> 30) & 0x1ff) << 3)) & a20_mask;
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PTE_HPHYS(pte_addr);
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pte = x86_ldq_phys(cs, pte_addr);
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if (!(pte & PG_PRESENT_MASK)) {
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goto do_fault;
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}
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if (pdpe & rsvd_mask) {
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if (pte & rsvd_mask) {
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goto do_fault_rsvd;
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}
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ptep &= pdpe ^ PG_NX_MASK;
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if (!(pdpe & PG_ACCESSED_MASK)) {
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pdpe |= PG_ACCESSED_MASK;
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x86_stl_phys_notdirty(cs, pdpe_addr, pdpe);
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ptep &= pte ^ PG_NX_MASK;
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if (!(pte & PG_ACCESSED_MASK)) {
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pte |= PG_ACCESSED_MASK;
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x86_stl_phys_notdirty(cs, pte_addr, pte);
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}
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if (pdpe & PG_PSE_MASK) {
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if (pte & PG_PSE_MASK) {
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/* 1 GB page */
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page_size = 1024 * 1024 * 1024;
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pte_addr = pdpe_addr;
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pte = pdpe;
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goto do_check_protect;
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}
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} else
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#endif
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{
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/* XXX: load them when cr3 is loaded ? */
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pdpe_addr = ((in->cr3 & ~0x1f) + ((addr >> 27) & 0x18)) &
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a20_mask;
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PTE_HPHYS(pdpe_addr);
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pdpe = x86_ldq_phys(cs, pdpe_addr);
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if (!(pdpe & PG_PRESENT_MASK)) {
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/*
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* Page table level 3
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*/
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pte_addr = ((in->cr3 & ~0x1f) + ((addr >> 27) & 0x18)) & a20_mask;
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PTE_HPHYS(pte_addr);
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pte = x86_ldq_phys(cs, pte_addr);
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if (!(pte & PG_PRESENT_MASK)) {
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goto do_fault;
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}
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rsvd_mask |= PG_HI_USER_MASK;
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if (pdpe & (rsvd_mask | PG_NX_MASK)) {
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if (pte & (rsvd_mask | PG_NX_MASK)) {
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goto do_fault_rsvd;
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}
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ptep = PG_NX_MASK | PG_USER_MASK | PG_RW_MASK;
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}
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pde_addr = ((pdpe & PG_ADDRESS_MASK) + (((addr >> 21) & 0x1ff) << 3)) &
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a20_mask;
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PTE_HPHYS(pde_addr);
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pde = x86_ldq_phys(cs, pde_addr);
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if (!(pde & PG_PRESENT_MASK)) {
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/*
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* Page table level 2
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*/
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pte_addr = ((pte & PG_ADDRESS_MASK) +
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(((addr >> 21) & 0x1ff) << 3)) & a20_mask;
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PTE_HPHYS(pte_addr);
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pte = x86_ldq_phys(cs, pte_addr);
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if (!(pte & PG_PRESENT_MASK)) {
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goto do_fault;
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}
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if (pde & rsvd_mask) {
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if (pte & rsvd_mask) {
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goto do_fault_rsvd;
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}
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ptep &= pde ^ PG_NX_MASK;
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if (pde & PG_PSE_MASK) {
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ptep &= pte ^ PG_NX_MASK;
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if (pte & PG_PSE_MASK) {
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/* 2 MB page */
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page_size = 2048 * 1024;
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pte_addr = pde_addr;
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pte = pde;
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goto do_check_protect;
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}
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/* 4 KB page */
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if (!(pde & PG_ACCESSED_MASK)) {
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pde |= PG_ACCESSED_MASK;
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x86_stl_phys_notdirty(cs, pde_addr, pde);
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if (!(pte & PG_ACCESSED_MASK)) {
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pte |= PG_ACCESSED_MASK;
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x86_stl_phys_notdirty(cs, pte_addr, pte);
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}
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pte_addr = ((pde & PG_ADDRESS_MASK) + (((addr >> 12) & 0x1ff) << 3)) &
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a20_mask;
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/*
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* Page table level 1
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*/
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pte_addr = ((pte & PG_ADDRESS_MASK) +
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(((addr >> 12) & 0x1ff) << 3)) & a20_mask;
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PTE_HPHYS(pte_addr);
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pte = x86_ldq_phys(cs, pte_addr);
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if (!(pte & PG_PRESENT_MASK)) {
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@ -214,39 +220,37 @@ static bool mmu_translate(CPUX86State *env, const TranslateParams *in,
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ptep &= pte ^ PG_NX_MASK;
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page_size = 4096;
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} else {
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uint32_t pde;
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/* page directory entry */
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pde_addr = ((in->cr3 & ~0xfff) + ((addr >> 20) & 0xffc)) &
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a20_mask;
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PTE_HPHYS(pde_addr);
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pde = x86_ldl_phys(cs, pde_addr);
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if (!(pde & PG_PRESENT_MASK)) {
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/*
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* Page table level 2
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*/
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pte_addr = ((in->cr3 & ~0xfff) + ((addr >> 20) & 0xffc)) & a20_mask;
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PTE_HPHYS(pte_addr);
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pte = x86_ldl_phys(cs, pte_addr);
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if (!(pte & PG_PRESENT_MASK)) {
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goto do_fault;
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}
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ptep = pde | PG_NX_MASK;
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ptep = pte | PG_NX_MASK;
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/* if PSE bit is set, then we use a 4MB page */
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if ((pde & PG_PSE_MASK) && (pg_mode & PG_MODE_PSE)) {
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if ((pte & PG_PSE_MASK) && (pg_mode & PG_MODE_PSE)) {
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page_size = 4096 * 1024;
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pte_addr = pde_addr;
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/* Bits 20-13 provide bits 39-32 of the address, bit 21 is reserved.
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/*
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* Bits 20-13 provide bits 39-32 of the address, bit 21 is reserved.
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* Leave bits 20-13 in place for setting accessed/dirty bits below.
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*/
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pte = pde | ((pde & 0x1fe000LL) << (32 - 13));
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pte = (uint32_t)pte | ((pte & 0x1fe000LL) << (32 - 13));
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rsvd_mask = 0x200000;
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goto do_check_protect_pse36;
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}
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if (!(pde & PG_ACCESSED_MASK)) {
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pde |= PG_ACCESSED_MASK;
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x86_stl_phys_notdirty(cs, pde_addr, pde);
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if (!(pte & PG_ACCESSED_MASK)) {
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pte |= PG_ACCESSED_MASK;
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x86_stl_phys_notdirty(cs, pte_addr, pte);
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}
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/* page directory entry */
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pte_addr = ((pde & ~0xfff) + ((addr >> 10) & 0xffc)) &
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a20_mask;
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/*
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* Page table level 1
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*/
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pte_addr = ((pte & ~0xfffu) + ((addr >> 10) & 0xffc)) & a20_mask;
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PTE_HPHYS(pte_addr);
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pte = x86_ldl_phys(cs, pte_addr);
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if (!(pte & PG_PRESENT_MASK)) {
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