meson: rename included C source files to .c.inc

With Makefiles that have automatically generated dependencies, you
generated includes are set as dependencies of the Makefile, so that they
are built before everything else and they are available when first
building the .c files.

Alternatively you can use a fine-grained dependency, e.g.

        target/arm/translate.o: target/arm/decode-neon-shared.inc.c

With Meson you have only one choice and it is a third option, namely
"build at the beginning of the corresponding target"; the way you
express it is to list the includes in the sources of that target.

The problem is that Meson decides if something is a source vs. a
generated include by looking at the extension: '.c', '.cc', '.m', '.C'
are sources, while everything else is considered an include---including
'.inc.c'.

Use '.c.inc' to avoid this, as it is consistent with our other convention
of using '.rst.inc' for included reStructuredText files.  The editorconfig
file is adjusted.

Signed-off-by: Paolo Bonzini <pbonzini@redhat.com>
This commit is contained in:
Paolo Bonzini 2020-02-04 12:41:01 +01:00
parent 243af0225a
commit 139c1837db
99 changed files with 175 additions and 174 deletions

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@ -22,9 +22,10 @@ indent_style = tab
indent_size = 8 indent_size = 8
file_type_emacs = makefile file_type_emacs = makefile
[*.{c,h}] [*.{c,h,c.inc,h.inc}]
indent_style = space indent_style = space
indent_size = 4 indent_size = 4
file_type_emacs = c
[*.sh] [*.sh]
indent_style = space indent_style = space

4
.gitignore vendored
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@ -18,7 +18,7 @@
/ui/shader/texture-blit-frag.h /ui/shader/texture-blit-frag.h
/ui/shader/texture-blit-vert.h /ui/shader/texture-blit-vert.h
/ui/shader/texture-blit-flip-vert.h /ui/shader/texture-blit-flip-vert.h
/ui/input-keymap-*.c /ui/input-keymap-*.c.inc
*-timestamp *-timestamp
/*-softmmu /*-softmmu
/*-darwin-user /*-darwin-user
@ -161,4 +161,4 @@ trace-dtrace-root.h
trace-dtrace-root.dtrace trace-dtrace-root.dtrace
trace-ust-all.h trace-ust-all.h
trace-ust-all.c trace-ust-all.c
/target/arm/decode-sve.inc.c /target/arm/decode-sve.c.inc

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@ -289,28 +289,28 @@ KEYCODEMAP_GEN = $(SRC_PATH)/ui/keycodemapdb/tools/keymap-gen
KEYCODEMAP_CSV = $(SRC_PATH)/ui/keycodemapdb/data/keymaps.csv KEYCODEMAP_CSV = $(SRC_PATH)/ui/keycodemapdb/data/keymaps.csv
KEYCODEMAP_FILES = \ KEYCODEMAP_FILES = \
ui/input-keymap-atset1-to-qcode.c \ ui/input-keymap-atset1-to-qcode.c.inc \
ui/input-keymap-linux-to-qcode.c \ ui/input-keymap-linux-to-qcode.c.inc \
ui/input-keymap-qcode-to-atset1.c \ ui/input-keymap-qcode-to-atset1.c.inc \
ui/input-keymap-qcode-to-atset2.c \ ui/input-keymap-qcode-to-atset2.c.inc \
ui/input-keymap-qcode-to-atset3.c \ ui/input-keymap-qcode-to-atset3.c.inc \
ui/input-keymap-qcode-to-linux.c \ ui/input-keymap-qcode-to-linux.c.inc \
ui/input-keymap-qcode-to-qnum.c \ ui/input-keymap-qcode-to-qnum.c.inc \
ui/input-keymap-qcode-to-sun.c \ ui/input-keymap-qcode-to-sun.c.inc \
ui/input-keymap-qnum-to-qcode.c \ ui/input-keymap-qnum-to-qcode.c.inc \
ui/input-keymap-usb-to-qcode.c \ ui/input-keymap-usb-to-qcode.c.inc \
ui/input-keymap-win32-to-qcode.c \ ui/input-keymap-win32-to-qcode.c.inc \
ui/input-keymap-x11-to-qcode.c \ ui/input-keymap-x11-to-qcode.c.inc \
ui/input-keymap-xorgevdev-to-qcode.c \ ui/input-keymap-xorgevdev-to-qcode.c.inc \
ui/input-keymap-xorgkbd-to-qcode.c \ ui/input-keymap-xorgkbd-to-qcode.c.inc \
ui/input-keymap-xorgxquartz-to-qcode.c \ ui/input-keymap-xorgxquartz-to-qcode.c.inc \
ui/input-keymap-xorgxwin-to-qcode.c \ ui/input-keymap-xorgxwin-to-qcode.c.inc \
ui/input-keymap-osx-to-qcode.c \ ui/input-keymap-osx-to-qcode.c.inc \
$(NULL) $(NULL)
generated-files-$(CONFIG_SOFTMMU) += $(KEYCODEMAP_FILES) generated-files-$(CONFIG_SOFTMMU) += $(KEYCODEMAP_FILES)
ui/input-keymap-%.c: $(KEYCODEMAP_GEN) $(KEYCODEMAP_CSV) $(SRC_PATH)/ui/Makefile.objs ui/input-keymap-%.c.inc: $(KEYCODEMAP_GEN) $(KEYCODEMAP_CSV) $(SRC_PATH)/ui/Makefile.objs
$(call quiet-command,\ $(call quiet-command,\
stem=$* && src=$${stem%-to-*} dst=$${stem#*-to-} && \ stem=$* && src=$${stem%-to-*} dst=$${stem#*-to-} && \
test -e $(KEYCODEMAP_GEN) && \ test -e $(KEYCODEMAP_GEN) && \

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@ -2354,7 +2354,7 @@ void cpu_stq_le_data(CPUArchState *env, target_ulong ptr, uint64_t val)
#define ATOMIC_MMU_CLEANUP #define ATOMIC_MMU_CLEANUP
#define ATOMIC_MMU_IDX get_mmuidx(oi) #define ATOMIC_MMU_IDX get_mmuidx(oi)
#include "atomic_common.inc.c" #include "atomic_common.c.inc"
#define DATA_SIZE 1 #define DATA_SIZE 1
#include "atomic_template.h" #include "atomic_template.h"

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@ -1189,7 +1189,7 @@ static void *atomic_mmu_lookup(CPUArchState *env, target_ulong addr,
#define ATOMIC_NAME(X) HELPER(glue(glue(atomic_ ## X, SUFFIX), END)) #define ATOMIC_NAME(X) HELPER(glue(glue(atomic_ ## X, SUFFIX), END))
#define EXTRA_ARGS #define EXTRA_ARGS
#include "atomic_common.inc.c" #include "atomic_common.c.inc"
#define DATA_SIZE 1 #define DATA_SIZE 1
#include "atomic_template.h" #include "atomic_template.h"

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@ -42,7 +42,7 @@ order build,interface,tests,code,documentation,devel-doc,blobs
# (most common languages first # (most common languages first
# #
filetype code \.c$ # C filetype code \.c$ # C
filetype code \.inc.c$ # C filetype code \.c.inc$ # C
filetype code \.C$ # C++ filetype code \.C$ # C++
filetype code \.cpp$ # C++ filetype code \.cpp$ # C++
filetype code \.c\+\+$ # C++ filetype code \.c\+\+$ # C++

4
exec.c
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@ -3659,7 +3659,7 @@ void cpu_physical_memory_unmap(void *buffer, hwaddr len,
#define TRANSLATE(...) address_space_translate(as, __VA_ARGS__) #define TRANSLATE(...) address_space_translate(as, __VA_ARGS__)
#define RCU_READ_LOCK(...) rcu_read_lock() #define RCU_READ_LOCK(...) rcu_read_lock()
#define RCU_READ_UNLOCK(...) rcu_read_unlock() #define RCU_READ_UNLOCK(...) rcu_read_unlock()
#include "memory_ldst.inc.c" #include "memory_ldst.c.inc"
int64_t address_space_cache_init(MemoryRegionCache *cache, int64_t address_space_cache_init(MemoryRegionCache *cache,
AddressSpace *as, AddressSpace *as,
@ -3795,7 +3795,7 @@ address_space_write_cached_slow(MemoryRegionCache *cache, hwaddr addr,
#define TRANSLATE(...) address_space_translate_cached(cache, __VA_ARGS__) #define TRANSLATE(...) address_space_translate_cached(cache, __VA_ARGS__)
#define RCU_READ_LOCK() ((void)0) #define RCU_READ_LOCK() ((void)0)
#define RCU_READ_UNLOCK() ((void)0) #define RCU_READ_UNLOCK() ((void)0)
#include "memory_ldst.inc.c" #include "memory_ldst.c.inc"
/* virtual memory access for debug (includes writing to ROM) */ /* virtual memory access for debug (includes writing to ROM) */
int cpu_memory_rw_debug(CPUState *cpu, target_ulong addr, int cpu_memory_rw_debug(CPUState *cpu, target_ulong addr,

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@ -621,7 +621,7 @@ static inline float64 float64_pack_raw(FloatParts p)
| are propagated from function inputs to output. These details are target- | are propagated from function inputs to output. These details are target-
| specific. | specific.
*----------------------------------------------------------------------------*/ *----------------------------------------------------------------------------*/
#include "softfloat-specialize.inc.c" #include "softfloat-specialize.c.inc"
/* Canonicalize EXP and FRAC, setting CLS. */ /* Canonicalize EXP and FRAC, setting CLS. */
static FloatParts sf_canonicalize(FloatParts part, const FloatFmt *parm, static FloatParts sf_canonicalize(FloatParts part, const FloatFmt *parm,

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@ -636,7 +636,7 @@ struct TCGContext {
/* Track which vCPU triggers events */ /* Track which vCPU triggers events */
CPUState *cpu; /* *_trans */ CPUState *cpu; /* *_trans */
/* These structures are private to tcg-target.inc.c. */ /* These structures are private to tcg-target.c.inc. */
#ifdef TCG_TARGET_NEED_LDST_LABELS #ifdef TCG_TARGET_NEED_LDST_LABELS
QSIMPLEQ_HEAD(, TCGLabelQemuLdst) ldst_labels; QSIMPLEQ_HEAD(, TCGLabelQemuLdst) ldst_labels;
#endif #endif

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@ -113,7 +113,7 @@ EOT
for f in "$@"; do for f in "$@"; do
case "$f" in case "$f" in
*.inc.c) *.c.inc)
# These aren't standalone C source files # These aren't standalone C source files
echo "SKIPPING $f (not a standalone source file)" echo "SKIPPING $f (not a standalone source file)"
continue continue

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@ -13,66 +13,66 @@ obj-$(call lnot,$(CONFIG_KVM)) += kvm-stub.o
DECODETREE = $(SRC_PATH)/scripts/decodetree.py DECODETREE = $(SRC_PATH)/scripts/decodetree.py
target/arm/decode-sve.inc.c: $(SRC_PATH)/target/arm/sve.decode $(DECODETREE) target/arm/decode-sve.c.inc: $(SRC_PATH)/target/arm/sve.decode $(DECODETREE)
$(call quiet-command,\ $(call quiet-command,\
$(PYTHON) $(DECODETREE) --decode disas_sve -o $@ $<,\ $(PYTHON) $(DECODETREE) --decode disas_sve -o $@ $<,\
"GEN", $(TARGET_DIR)$@) "GEN", $(TARGET_DIR)$@)
target/arm/decode-neon-shared.inc.c: $(SRC_PATH)/target/arm/neon-shared.decode $(DECODETREE) target/arm/decode-neon-shared.c.inc: $(SRC_PATH)/target/arm/neon-shared.decode $(DECODETREE)
$(call quiet-command,\ $(call quiet-command,\
$(PYTHON) $(DECODETREE) --static-decode disas_neon_shared -o $@ $<,\ $(PYTHON) $(DECODETREE) --static-decode disas_neon_shared -o $@ $<,\
"GEN", $(TARGET_DIR)$@) "GEN", $(TARGET_DIR)$@)
target/arm/decode-neon-dp.inc.c: $(SRC_PATH)/target/arm/neon-dp.decode $(DECODETREE) target/arm/decode-neon-dp.c.inc: $(SRC_PATH)/target/arm/neon-dp.decode $(DECODETREE)
$(call quiet-command,\ $(call quiet-command,\
$(PYTHON) $(DECODETREE) --static-decode disas_neon_dp -o $@ $<,\ $(PYTHON) $(DECODETREE) --static-decode disas_neon_dp -o $@ $<,\
"GEN", $(TARGET_DIR)$@) "GEN", $(TARGET_DIR)$@)
target/arm/decode-neon-ls.inc.c: $(SRC_PATH)/target/arm/neon-ls.decode $(DECODETREE) target/arm/decode-neon-ls.c.inc: $(SRC_PATH)/target/arm/neon-ls.decode $(DECODETREE)
$(call quiet-command,\ $(call quiet-command,\
$(PYTHON) $(DECODETREE) --static-decode disas_neon_ls -o $@ $<,\ $(PYTHON) $(DECODETREE) --static-decode disas_neon_ls -o $@ $<,\
"GEN", $(TARGET_DIR)$@) "GEN", $(TARGET_DIR)$@)
target/arm/decode-vfp.inc.c: $(SRC_PATH)/target/arm/vfp.decode $(DECODETREE) target/arm/decode-vfp.c.inc: $(SRC_PATH)/target/arm/vfp.decode $(DECODETREE)
$(call quiet-command,\ $(call quiet-command,\
$(PYTHON) $(DECODETREE) --static-decode disas_vfp -o $@ $<,\ $(PYTHON) $(DECODETREE) --static-decode disas_vfp -o $@ $<,\
"GEN", $(TARGET_DIR)$@) "GEN", $(TARGET_DIR)$@)
target/arm/decode-vfp-uncond.inc.c: $(SRC_PATH)/target/arm/vfp-uncond.decode $(DECODETREE) target/arm/decode-vfp-uncond.c.inc: $(SRC_PATH)/target/arm/vfp-uncond.decode $(DECODETREE)
$(call quiet-command,\ $(call quiet-command,\
$(PYTHON) $(DECODETREE) --static-decode disas_vfp_uncond -o $@ $<,\ $(PYTHON) $(DECODETREE) --static-decode disas_vfp_uncond -o $@ $<,\
"GEN", $(TARGET_DIR)$@) "GEN", $(TARGET_DIR)$@)
target/arm/decode-a32.inc.c: $(SRC_PATH)/target/arm/a32.decode $(DECODETREE) target/arm/decode-a32.c.inc: $(SRC_PATH)/target/arm/a32.decode $(DECODETREE)
$(call quiet-command,\ $(call quiet-command,\
$(PYTHON) $(DECODETREE) --static-decode disas_a32 -o $@ $<,\ $(PYTHON) $(DECODETREE) --static-decode disas_a32 -o $@ $<,\
"GEN", $(TARGET_DIR)$@) "GEN", $(TARGET_DIR)$@)
target/arm/decode-a32-uncond.inc.c: $(SRC_PATH)/target/arm/a32-uncond.decode $(DECODETREE) target/arm/decode-a32-uncond.c.inc: $(SRC_PATH)/target/arm/a32-uncond.decode $(DECODETREE)
$(call quiet-command,\ $(call quiet-command,\
$(PYTHON) $(DECODETREE) --static-decode disas_a32_uncond -o $@ $<,\ $(PYTHON) $(DECODETREE) --static-decode disas_a32_uncond -o $@ $<,\
"GEN", $(TARGET_DIR)$@) "GEN", $(TARGET_DIR)$@)
target/arm/decode-t32.inc.c: $(SRC_PATH)/target/arm/t32.decode $(DECODETREE) target/arm/decode-t32.c.inc: $(SRC_PATH)/target/arm/t32.decode $(DECODETREE)
$(call quiet-command,\ $(call quiet-command,\
$(PYTHON) $(DECODETREE) --static-decode disas_t32 -o $@ $<,\ $(PYTHON) $(DECODETREE) --static-decode disas_t32 -o $@ $<,\
"GEN", $(TARGET_DIR)$@) "GEN", $(TARGET_DIR)$@)
target/arm/decode-t16.inc.c: $(SRC_PATH)/target/arm/t16.decode $(DECODETREE) target/arm/decode-t16.c.inc: $(SRC_PATH)/target/arm/t16.decode $(DECODETREE)
$(call quiet-command,\ $(call quiet-command,\
$(PYTHON) $(DECODETREE) -w 16 --static-decode disas_t16 -o $@ $<,\ $(PYTHON) $(DECODETREE) -w 16 --static-decode disas_t16 -o $@ $<,\
"GEN", $(TARGET_DIR)$@) "GEN", $(TARGET_DIR)$@)
target/arm/translate-sve.o: target/arm/decode-sve.inc.c target/arm/translate-sve.o: target/arm/decode-sve.c.inc
target/arm/translate.o: target/arm/decode-neon-shared.inc.c target/arm/translate.o: target/arm/decode-neon-shared.c.inc
target/arm/translate.o: target/arm/decode-neon-dp.inc.c target/arm/translate.o: target/arm/decode-neon-dp.c.inc
target/arm/translate.o: target/arm/decode-neon-ls.inc.c target/arm/translate.o: target/arm/decode-neon-ls.c.inc
target/arm/translate.o: target/arm/decode-vfp.inc.c target/arm/translate.o: target/arm/decode-vfp.c.inc
target/arm/translate.o: target/arm/decode-vfp-uncond.inc.c target/arm/translate.o: target/arm/decode-vfp-uncond.c.inc
target/arm/translate.o: target/arm/decode-a32.inc.c target/arm/translate.o: target/arm/decode-a32.c.inc
target/arm/translate.o: target/arm/decode-a32-uncond.inc.c target/arm/translate.o: target/arm/decode-a32-uncond.c.inc
target/arm/translate.o: target/arm/decode-t32.inc.c target/arm/translate.o: target/arm/decode-t32.c.inc
target/arm/translate.o: target/arm/decode-t16.inc.c target/arm/translate.o: target/arm/decode-t16.c.inc
obj-y += tlb_helper.o debug_helper.o obj-y += tlb_helper.o debug_helper.o
obj-y += translate.o op_helper.o obj-y += translate.o op_helper.o

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@ -50,9 +50,9 @@ static inline int rsub_8(DisasContext *s, int x)
} }
/* Include the generated Neon decoder */ /* Include the generated Neon decoder */
#include "decode-neon-dp.inc.c" #include "decode-neon-dp.c.inc"
#include "decode-neon-ls.inc.c" #include "decode-neon-ls.c.inc"
#include "decode-neon-shared.inc.c" #include "decode-neon-shared.c.inc"
/* Return the offset of a 2**SIZE piece of a NEON register, at index ELE, /* Return the offset of a 2**SIZE piece of a NEON register, at index ELE,
* where 0 is the least significant end of the register. * where 0 is the least significant end of the register.

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@ -100,7 +100,7 @@ static inline int msz_dtype(DisasContext *s, int msz)
* Include the generated decoder. * Include the generated decoder.
*/ */
#include "decode-sve.inc.c" #include "decode-sve.c.inc"
/* /*
* Implement all of the translator functions referenced by the decoder. * Implement all of the translator functions referenced by the decoder.

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@ -27,8 +27,8 @@
*/ */
/* Include the generated VFP decoder */ /* Include the generated VFP decoder */
#include "decode-vfp.inc.c" #include "decode-vfp.c.inc"
#include "decode-vfp-uncond.inc.c" #include "decode-vfp-uncond.c.inc"
/* /*
* The imm8 encodes the sign bit, enough bits to represent an exponent in * The imm8 encodes the sign bit, enough bits to represent an exponent in

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@ -1176,8 +1176,8 @@ static TCGv_ptr vfp_reg_ptr(bool dp, int reg)
#define ARM_CP_RW_BIT (1 << 20) #define ARM_CP_RW_BIT (1 << 20)
/* Include the VFP and Neon decoders */ /* Include the VFP and Neon decoders */
#include "translate-vfp.inc.c" #include "translate-vfp.c.inc"
#include "translate-neon.inc.c" #include "translate-neon.c.inc"
static inline void iwmmxt_load_reg(TCGv_i64 var, int reg) static inline void iwmmxt_load_reg(TCGv_i64 var, int reg)
{ {
@ -5217,10 +5217,10 @@ static int t16_pop_list(DisasContext *s, int x)
* Include the generated decoders. * Include the generated decoders.
*/ */
#include "decode-a32.inc.c" #include "decode-a32.c.inc"
#include "decode-a32-uncond.inc.c" #include "decode-a32-uncond.c.inc"
#include "decode-t32.inc.c" #include "decode-t32.c.inc"
#include "decode-t16.inc.c" #include "decode-t16.c.inc"
/* Helpers to swap operands for reverse-subtract. */ /* Helpers to swap operands for reverse-subtract. */
static void gen_rsb(TCGv_i32 dst, TCGv_i32 a, TCGv_i32 b) static void gen_rsb(TCGv_i32 dst, TCGv_i32 a, TCGv_i32 b)

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@ -21,12 +21,12 @@
DECODETREE = $(SRC_PATH)/scripts/decodetree.py DECODETREE = $(SRC_PATH)/scripts/decodetree.py
decode-y = $(SRC_PATH)/target/avr/insn.decode decode-y = $(SRC_PATH)/target/avr/insn.decode
target/avr/decode_insn.inc.c: $(decode-y) $(DECODETREE) target/avr/decode_insn.c.inc: $(decode-y) $(DECODETREE)
$(call quiet-command, \ $(call quiet-command, \
$(PYTHON) $(DECODETREE) -o $@ --decode decode_insn --insnwidth 16 $<, \ $(PYTHON) $(DECODETREE) -o $@ --decode decode_insn --insnwidth 16 $<, \
"GEN", $(TARGET_DIR)$@) "GEN", $(TARGET_DIR)$@)
target/avr/translate.o: target/avr/decode_insn.inc.c target/avr/translate.o: target/avr/decode_insn.c.inc
obj-y += translate.o cpu.o helper.o obj-y += translate.o cpu.o helper.o
obj-y += gdbstub.o obj-y += gdbstub.o

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@ -60,7 +60,7 @@ static int append_16(DisasContext *ctx, int x)
/* Include the auto-generated decoder. */ /* Include the auto-generated decoder. */
static bool decode_insn(DisasContext *ctx, uint16_t insn); static bool decode_insn(DisasContext *ctx, uint16_t insn);
#include "decode_insn.inc.c" #include "decode_insn.c.inc"
#define output(mnemonic, format, ...) \ #define output(mnemonic, format, ...) \
(pctx->info->fprintf_func(pctx->info->stream, "%-9s " format, \ (pctx->info->fprintf_func(pctx->info->stream, "%-9s " format, \

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@ -198,7 +198,7 @@ static bool avr_have_feature(DisasContext *ctx, int feature)
} }
static bool decode_insn(DisasContext *ctx, uint16_t insn); static bool decode_insn(DisasContext *ctx, uint16_t insn);
#include "decode_insn.inc.c" #include "decode_insn.c.inc"
/* /*
* Arithmetic Instructions * Arithmetic Instructions

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@ -3037,7 +3037,7 @@ static unsigned int crisv32_decoder(CPUCRISState *env, DisasContext *dc)
return insn_len; return insn_len;
} }
#include "translate_v10.inc.c" #include "translate_v10.c.inc"
/* /*
* Delay slots on QEMU/CRIS. * Delay slots on QEMU/CRIS.

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@ -4,8 +4,8 @@ obj-$(CONFIG_SOFTMMU) += machine.o
DECODETREE = $(SRC_PATH)/scripts/decodetree.py DECODETREE = $(SRC_PATH)/scripts/decodetree.py
target/hppa/decode.inc.c: $(SRC_PATH)/target/hppa/insns.decode $(DECODETREE) target/hppa/decode.c.inc: $(SRC_PATH)/target/hppa/insns.decode $(DECODETREE)
$(call quiet-command,\ $(call quiet-command,\
$(PYTHON) $(DECODETREE) -o $@ $<, "GEN", $(TARGET_DIR)$@) $(PYTHON) $(DECODETREE) -o $@ $<, "GEN", $(TARGET_DIR)$@)
target/hppa/translate.o: target/hppa/decode.inc.c target/hppa/translate.o: target/hppa/decode.c.inc

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@ -334,7 +334,7 @@ static int expand_shl11(DisasContext *ctx, int val)
/* Include the auto-generated decoder. */ /* Include the auto-generated decoder. */
#include "decode.inc.c" #include "decode.c.inc"
/* We are not using a goto_tb (for whatever reason), but have updated /* We are not using a goto_tb (for whatever reason), but have updated
the iaq (for whatever reason), so don't do it again on exit. */ the iaq (for whatever reason), so don't do it again on exit. */

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@ -31322,7 +31322,7 @@ void mips_tcg_init(void)
#endif #endif
} }
#include "translate_init.inc.c" #include "translate_init.c.inc"
void cpu_mips_realize_env(CPUMIPSState *env) void cpu_mips_realize_env(CPUMIPSState *env)
{ {

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@ -6,10 +6,10 @@ obj-y += gdbstub.o
DECODETREE = $(SRC_PATH)/scripts/decodetree.py DECODETREE = $(SRC_PATH)/scripts/decodetree.py
target/openrisc/decode.inc.c: \ target/openrisc/decode.c.inc: \
$(SRC_PATH)/target/openrisc/insns.decode $(DECODETREE) $(SRC_PATH)/target/openrisc/insns.decode $(DECODETREE)
$(call quiet-command,\ $(call quiet-command,\
$(PYTHON) $(DECODETREE) -o $@ $<, "GEN", $(TARGET_DIR)$@) $(PYTHON) $(DECODETREE) -o $@ $<, "GEN", $(TARGET_DIR)$@)
target/openrisc/translate.o: target/openrisc/decode.inc.c target/openrisc/translate.o: target/openrisc/decode.c.inc
target/openrisc/disas.o: target/openrisc/decode.inc.c target/openrisc/disas.o: target/openrisc/decode.c.inc

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@ -25,7 +25,7 @@
typedef disassemble_info DisasContext; typedef disassemble_info DisasContext;
/* Include the auto-generated decoder. */ /* Include the auto-generated decoder. */
#include "decode.inc.c" #include "decode.c.inc"
#define output(mnemonic, format, ...) \ #define output(mnemonic, format, ...) \
(info->fprintf_func(info->stream, "%-9s " format, \ (info->fprintf_func(info->stream, "%-9s " format, \

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@ -65,7 +65,7 @@ static inline bool is_user(DisasContext *dc)
} }
/* Include the auto-generated decoder. */ /* Include the auto-generated decoder. */
#include "decode.inc.c" #include "decode.c.inc"
static TCGv cpu_sr; static TCGv cpu_sr;
static TCGv cpu_regs[32]; static TCGv cpu_regs[32];

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@ -398,7 +398,7 @@ target_ulong helper_divso(CPUPPCState *env, target_ulong arg1,
target_ulong helper_602_mfrom(target_ulong arg) target_ulong helper_602_mfrom(target_ulong arg)
{ {
if (likely(arg < 602)) { if (likely(arg < 602)) {
#include "mfrom_table.inc.c" #include "mfrom_table.c.inc"
return mfrom_ROM_table[arg]; return mfrom_ROM_table[arg];
} else { } else {
return 0; return 0;

View File

@ -6900,15 +6900,15 @@ static inline void set_avr64(int regno, TCGv_i64 src, bool high)
tcg_gen_st_i64(src, cpu_env, avr64_offset(regno, high)); tcg_gen_st_i64(src, cpu_env, avr64_offset(regno, high));
} }
#include "translate/fp-impl.inc.c" #include "translate/fp-impl.c.inc"
#include "translate/vmx-impl.inc.c" #include "translate/vmx-impl.c.inc"
#include "translate/vsx-impl.inc.c" #include "translate/vsx-impl.c.inc"
#include "translate/dfp-impl.inc.c" #include "translate/dfp-impl.c.inc"
#include "translate/spe-impl.inc.c" #include "translate/spe-impl.c.inc"
/* Handles lfdp, lxsd, lxssp */ /* Handles lfdp, lxsd, lxssp */
static void gen_dform39(DisasContext *ctx) static void gen_dform39(DisasContext *ctx)
@ -7587,19 +7587,19 @@ GEN_HANDLER2_E(treclaim, "treclaim", 0x1F, 0x0E, 0x1D, 0x03E0F800, \
GEN_HANDLER2_E(trechkpt, "trechkpt", 0x1F, 0x0E, 0x1F, 0x03FFF800, \ GEN_HANDLER2_E(trechkpt, "trechkpt", 0x1F, 0x0E, 0x1F, 0x03FFF800, \
PPC_NONE, PPC2_TM), PPC_NONE, PPC2_TM),
#include "translate/fp-ops.inc.c" #include "translate/fp-ops.c.inc"
#include "translate/vmx-ops.inc.c" #include "translate/vmx-ops.c.inc"
#include "translate/vsx-ops.inc.c" #include "translate/vsx-ops.c.inc"
#include "translate/dfp-ops.inc.c" #include "translate/dfp-ops.c.inc"
#include "translate/spe-ops.inc.c" #include "translate/spe-ops.c.inc"
}; };
#include "helper_regs.h" #include "helper_regs.h"
#include "translate_init.inc.c" #include "translate_init.c.inc"
/*****************************************************************************/ /*****************************************************************************/
/* Misc PowerPC helpers */ /* Misc PowerPC helpers */

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@ -14,15 +14,15 @@ decode16-y = $(SRC_PATH)/target/riscv/insn16.decode
decode16-$(TARGET_RISCV32) += $(SRC_PATH)/target/riscv/insn16-32.decode decode16-$(TARGET_RISCV32) += $(SRC_PATH)/target/riscv/insn16-32.decode
decode16-$(TARGET_RISCV64) += $(SRC_PATH)/target/riscv/insn16-64.decode decode16-$(TARGET_RISCV64) += $(SRC_PATH)/target/riscv/insn16-64.decode
target/riscv/decode_insn32.inc.c: $(decode32-y) $(DECODETREE) target/riscv/decode_insn32.c.inc: $(decode32-y) $(DECODETREE)
$(call quiet-command, \ $(call quiet-command, \
$(PYTHON) $(DECODETREE) -o $@ --static-decode decode_insn32 \ $(PYTHON) $(DECODETREE) -o $@ --static-decode decode_insn32 \
$(decode32-y), "GEN", $(TARGET_DIR)$@) $(decode32-y), "GEN", $(TARGET_DIR)$@)
target/riscv/decode_insn16.inc.c: $(decode16-y) $(DECODETREE) target/riscv/decode_insn16.c.inc: $(decode16-y) $(DECODETREE)
$(call quiet-command, \ $(call quiet-command, \
$(PYTHON) $(DECODETREE) -o $@ --static-decode decode_insn16 \ $(PYTHON) $(DECODETREE) -o $@ --static-decode decode_insn16 \
--insnwidth 16 $(decode16-y), "GEN", $(TARGET_DIR)$@) --insnwidth 16 $(decode16-y), "GEN", $(TARGET_DIR)$@)
target/riscv/translate.o: target/riscv/decode_insn32.inc.c \ target/riscv/translate.o: target/riscv/decode_insn32.c.inc \
target/riscv/decode_insn16.inc.c target/riscv/decode_insn16.c.inc

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@ -583,7 +583,7 @@ static int ex_rvc_shifti(DisasContext *ctx, int imm)
} }
/* Include the auto-generated decoder for 32 bit insn */ /* Include the auto-generated decoder for 32 bit insn */
#include "decode_insn32.inc.c" #include "decode_insn32.c.inc"
static bool gen_arith_imm_fn(DisasContext *ctx, arg_i *a, static bool gen_arith_imm_fn(DisasContext *ctx, arg_i *a,
void (*func)(TCGv, TCGv, target_long)) void (*func)(TCGv, TCGv, target_long))
@ -718,17 +718,17 @@ static bool gen_shift(DisasContext *ctx, arg_r *a,
} }
/* Include insn module translation function */ /* Include insn module translation function */
#include "insn_trans/trans_rvi.inc.c" #include "insn_trans/trans_rvi.c.inc"
#include "insn_trans/trans_rvm.inc.c" #include "insn_trans/trans_rvm.c.inc"
#include "insn_trans/trans_rva.inc.c" #include "insn_trans/trans_rva.c.inc"
#include "insn_trans/trans_rvf.inc.c" #include "insn_trans/trans_rvf.c.inc"
#include "insn_trans/trans_rvd.inc.c" #include "insn_trans/trans_rvd.c.inc"
#include "insn_trans/trans_rvh.inc.c" #include "insn_trans/trans_rvh.c.inc"
#include "insn_trans/trans_rvv.inc.c" #include "insn_trans/trans_rvv.c.inc"
#include "insn_trans/trans_privileged.inc.c" #include "insn_trans/trans_privileged.c.inc"
/* Include the auto-generated decoder for 16 bit insn */ /* Include the auto-generated decoder for 16 bit insn */
#include "decode_insn16.inc.c" #include "decode_insn16.c.inc"
static void decode_opc(CPURISCVState *env, DisasContext *ctx, uint16_t opcode) static void decode_opc(CPURISCVState *env, DisasContext *ctx, uint16_t opcode)
{ {

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@ -2,10 +2,10 @@ obj-y += translate.o op_helper.o helper.o cpu.o gdbstub.o disas.o
DECODETREE = $(SRC_PATH)/scripts/decodetree.py DECODETREE = $(SRC_PATH)/scripts/decodetree.py
target/rx/decode.inc.c: \ target/rx/decode.c.inc: \
$(SRC_PATH)/target/rx/insns.decode $(DECODETREE) $(SRC_PATH)/target/rx/insns.decode $(DECODETREE)
$(call quiet-command,\ $(call quiet-command,\
$(PYTHON) $(DECODETREE) --varinsnwidth 32 -o $@ $<, "GEN", $(TARGET_DIR)$@) $(PYTHON) $(DECODETREE) --varinsnwidth 32 -o $@ $<, "GEN", $(TARGET_DIR)$@)
target/rx/translate.o: target/rx/decode.inc.c target/rx/translate.o: target/rx/decode.c.inc
target/rx/disas.o: target/rx/decode.inc.c target/rx/disas.o: target/rx/decode.c.inc

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@ -100,7 +100,7 @@ static int bdsp_s(DisasContext *ctx, int d)
} }
/* Include the auto-generated decoder. */ /* Include the auto-generated decoder. */
#include "decode.inc.c" #include "decode.c.inc"
static void dump_bytes(DisasContext *ctx) static void dump_bytes(DisasContext *ctx)
{ {

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@ -124,7 +124,7 @@ static int bdsp_s(DisasContext *ctx, int d)
} }
/* Include the auto-generated decoder. */ /* Include the auto-generated decoder. */
#include "decode.inc.c" #include "decode.c.inc"
void rx_cpu_dump_state(CPUState *cs, FILE *f, int flags) void rx_cpu_dump_state(CPUState *cs, FILE *f, int flags)
{ {

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@ -5120,7 +5120,7 @@ static DisasJumpType op_mpcifc(DisasContext *s, DisasOps *o)
} }
#endif #endif
#include "translate_vx.inc.c" #include "translate_vx.c.inc"
/* ====================================================================== */ /* ====================================================================== */
/* The "Cc OUTput" generators. Given the generated output (and in some cases /* The "Cc OUTput" generators. Given the generated output (and in some cases

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@ -35,13 +35,13 @@
#include "overlay_tool.h" #include "overlay_tool.h"
#define xtensa_modules xtensa_modules_dc232b #define xtensa_modules xtensa_modules_dc232b
#include "core-dc232b/xtensa-modules.inc.c" #include "core-dc232b/xtensa-modules.c.inc"
static XtensaConfig dc232b __attribute__((unused)) = { static XtensaConfig dc232b __attribute__((unused)) = {
.name = "dc232b", .name = "dc232b",
.gdb_regmap = { .gdb_regmap = {
.reg = { .reg = {
#include "core-dc232b/gdb-config.inc.c" #include "core-dc232b/gdb-config.c.inc"
} }
}, },
.isa_internal = &xtensa_modules, .isa_internal = &xtensa_modules,

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@ -34,13 +34,13 @@
#include "overlay_tool.h" #include "overlay_tool.h"
#define xtensa_modules xtensa_modules_dc233c #define xtensa_modules xtensa_modules_dc233c
#include "core-dc233c/xtensa-modules.inc.c" #include "core-dc233c/xtensa-modules.c.inc"
static XtensaConfig dc233c __attribute__((unused)) = { static XtensaConfig dc233c __attribute__((unused)) = {
.name = "dc233c", .name = "dc233c",
.gdb_regmap = { .gdb_regmap = {
.reg = { .reg = {
#include "core-dc233c/gdb-config.inc.c" #include "core-dc233c/gdb-config.c.inc"
} }
}, },
.isa_internal = &xtensa_modules, .isa_internal = &xtensa_modules,

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@ -34,13 +34,13 @@
#include "overlay_tool.h" #include "overlay_tool.h"
#define xtensa_modules xtensa_modules_de212 #define xtensa_modules xtensa_modules_de212
#include "core-de212/xtensa-modules.inc.c" #include "core-de212/xtensa-modules.c.inc"
static XtensaConfig de212 __attribute__((unused)) = { static XtensaConfig de212 __attribute__((unused)) = {
.name = "de212", .name = "de212",
.gdb_regmap = { .gdb_regmap = {
.reg = { .reg = {
#include "core-de212/gdb-config.inc.c" #include "core-de212/gdb-config.c.inc"
} }
}, },
.isa_internal = &xtensa_modules, .isa_internal = &xtensa_modules,

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@ -34,7 +34,7 @@
#include "overlay_tool.h" #include "overlay_tool.h"
#define xtensa_modules xtensa_modules_fsf #define xtensa_modules xtensa_modules_fsf
#include "core-fsf/xtensa-modules.inc.c" #include "core-fsf/xtensa-modules.c.inc"
static XtensaConfig fsf __attribute__((unused)) = { static XtensaConfig fsf __attribute__((unused)) = {
.name = "fsf", .name = "fsf",

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@ -34,13 +34,13 @@
#include "overlay_tool.h" #include "overlay_tool.h"
#define xtensa_modules xtensa_modules_sample_controller #define xtensa_modules xtensa_modules_sample_controller
#include "core-sample_controller/xtensa-modules.inc.c" #include "core-sample_controller/xtensa-modules.c.inc"
static XtensaConfig sample_controller __attribute__((unused)) = { static XtensaConfig sample_controller __attribute__((unused)) = {
.name = "sample_controller", .name = "sample_controller",
.gdb_regmap = { .gdb_regmap = {
.reg = { .reg = {
#include "core-sample_controller/gdb-config.inc.c" #include "core-sample_controller/gdb-config.c.inc"
} }
}, },
.isa_internal = &xtensa_modules, .isa_internal = &xtensa_modules,

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@ -34,13 +34,13 @@
#include "overlay_tool.h" #include "overlay_tool.h"
#define xtensa_modules xtensa_modules_test_kc705_be #define xtensa_modules xtensa_modules_test_kc705_be
#include "core-test_kc705_be/xtensa-modules.inc.c" #include "core-test_kc705_be/xtensa-modules.c.inc"
static XtensaConfig test_kc705_be __attribute__((unused)) = { static XtensaConfig test_kc705_be __attribute__((unused)) = {
.name = "test_kc705_be", .name = "test_kc705_be",
.gdb_regmap = { .gdb_regmap = {
.reg = { .reg = {
#include "core-test_kc705_be/gdb-config.inc.c" #include "core-test_kc705_be/gdb-config.c.inc"
} }
}, },
.isa_internal = &xtensa_modules, .isa_internal = &xtensa_modules,

View File

@ -35,13 +35,13 @@
#include "overlay_tool.h" #include "overlay_tool.h"
#define xtensa_modules xtensa_modules_test_mmuhifi_c3 #define xtensa_modules xtensa_modules_test_mmuhifi_c3
#include "core-test_mmuhifi_c3/xtensa-modules.inc.c" #include "core-test_mmuhifi_c3/xtensa-modules.c.inc"
static XtensaConfig test_mmuhifi_c3 __attribute__((unused)) = { static XtensaConfig test_mmuhifi_c3 __attribute__((unused)) = {
.name = "test_mmuhifi_c3", .name = "test_mmuhifi_c3",
.gdb_regmap = { .gdb_regmap = {
.reg = { .reg = {
#include "core-test_mmuhifi_c3/gdb-config.inc.c" #include "core-test_mmuhifi_c3/gdb-config.c.inc"
} }
}, },
.isa_internal = &xtensa_modules, .isa_internal = &xtensa_modules,

View File

@ -23,7 +23,7 @@ tar -xf "$OVERLAY" -C "$TARGET" --strip-components=2 \
xtensa/config/core-isa.h \ xtensa/config/core-isa.h \
xtensa/config/core-matmap.h xtensa/config/core-matmap.h
tar -xf "$OVERLAY" -O gdb/xtensa-config.c | \ tar -xf "$OVERLAY" -O gdb/xtensa-config.c | \
sed -n '1,/*\//p;/XTREG/,/XTREG_END/p' > "$TARGET"/gdb-config.inc.c sed -n '1,/*\//p;/XTREG/,/XTREG_END/p' > "$TARGET"/gdb-config.c.inc
# #
# Fix up known issues in the xtensa-modules.c # Fix up known issues in the xtensa-modules.c
# #
@ -35,7 +35,7 @@ tar -xf "$OVERLAY" -O binutils/xtensa-modules.c | \
-e '/^#include "ansidecl.h"/d' \ -e '/^#include "ansidecl.h"/d' \
-e '/^Slot_[a-zA-Z0-9_]\+_decode (const xtensa_insnbuf insn)/,/^}/s/^ return 0;$/ return XTENSA_UNDEFINED;/' \ -e '/^Slot_[a-zA-Z0-9_]\+_decode (const xtensa_insnbuf insn)/,/^}/s/^ return 0;$/ return XTENSA_UNDEFINED;/' \
-e 's/#include <xtensa-isa.h>/#include "xtensa-isa.h"/' \ -e 's/#include <xtensa-isa.h>/#include "xtensa-isa.h"/' \
> "$TARGET"/xtensa-modules.inc.c > "$TARGET"/xtensa-modules.c.inc
cat <<EOF > "${TARGET}.c" cat <<EOF > "${TARGET}.c"
#include "qemu/osdep.h" #include "qemu/osdep.h"
@ -49,13 +49,13 @@ cat <<EOF > "${TARGET}.c"
#include "overlay_tool.h" #include "overlay_tool.h"
#define xtensa_modules xtensa_modules_$NAME #define xtensa_modules xtensa_modules_$NAME
#include "core-$NAME/xtensa-modules.inc.c" #include "core-$NAME/xtensa-modules.c.inc"
static XtensaConfig $NAME __attribute__((unused)) = { static XtensaConfig $NAME __attribute__((unused)) = {
.name = "$NAME", .name = "$NAME",
.gdb_regmap = { .gdb_regmap = {
.reg = { .reg = {
#include "core-$NAME/gdb-config.inc.c" #include "core-$NAME/gdb-config.c.inc"
} }
}, },
.isa_internal = &xtensa_modules, .isa_internal = &xtensa_modules,

View File

@ -652,7 +652,7 @@ function tcg_gen_xxx(args).
4) Backend 4) Backend
tcg-target.h contains the target specific definitions. tcg-target.inc.c tcg-target.h contains the target specific definitions. tcg-target.c.inc
contains the target specific code; it is #included by tcg/tcg.c, rather contains the target specific code; it is #included by tcg/tcg.c, rather
than being a standalone C file. than being a standalone C file.

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@ -10,7 +10,7 @@
* See the COPYING file in the top-level directory for details. * See the COPYING file in the top-level directory for details.
*/ */
#include "../tcg-pool.inc.c" #include "../tcg-pool.c.inc"
#include "qemu/bitops.h" #include "qemu/bitops.h"
/* We're going to re-use TCGType in setting of the SF bit, which controls /* We're going to re-use TCGType in setting of the SF bit, which controls
@ -1542,7 +1542,7 @@ static void tcg_out_cltz(TCGContext *s, TCGType ext, TCGReg d,
} }
#ifdef CONFIG_SOFTMMU #ifdef CONFIG_SOFTMMU
#include "../tcg-ldst.inc.c" #include "../tcg-ldst.c.inc"
/* helper signature: helper_ret_ld_mmu(CPUState *env, target_ulong addr, /* helper signature: helper_ret_ld_mmu(CPUState *env, target_ulong addr,
* TCGMemOpIdx oi, uintptr_t ra) * TCGMemOpIdx oi, uintptr_t ra)

View File

@ -23,7 +23,7 @@
*/ */
#include "elf.h" #include "elf.h"
#include "../tcg-pool.inc.c" #include "../tcg-pool.c.inc"
int arm_arch = __ARM_ARCH; int arm_arch = __ARM_ARCH;
@ -1131,7 +1131,7 @@ static TCGCond tcg_out_cmp2(TCGContext *s, const TCGArg *args,
} }
#ifdef CONFIG_SOFTMMU #ifdef CONFIG_SOFTMMU
#include "../tcg-ldst.inc.c" #include "../tcg-ldst.c.inc"
/* helper signature: helper_ret_ld_mmu(CPUState *env, target_ulong addr, /* helper signature: helper_ret_ld_mmu(CPUState *env, target_ulong addr,
* int mmu_idx, uintptr_t ra) * int mmu_idx, uintptr_t ra)

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@ -22,7 +22,7 @@
* THE SOFTWARE. * THE SOFTWARE.
*/ */
#include "../tcg-pool.inc.c" #include "../tcg-pool.c.inc"
#ifdef CONFIG_DEBUG_TCG #ifdef CONFIG_DEBUG_TCG
static const char * const tcg_target_reg_names[TCG_TARGET_NB_REGS] = { static const char * const tcg_target_reg_names[TCG_TARGET_NB_REGS] = {
@ -1647,7 +1647,7 @@ static void tcg_out_nopn(TCGContext *s, int n)
} }
#if defined(CONFIG_SOFTMMU) #if defined(CONFIG_SOFTMMU)
#include "../tcg-ldst.inc.c" #include "../tcg-ldst.c.inc"
/* helper signature: helper_ret_ld_mmu(CPUState *env, target_ulong addr, /* helper signature: helper_ret_ld_mmu(CPUState *env, target_ulong addr,
* int mmu_idx, uintptr_t ra) * int mmu_idx, uintptr_t ra)

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@ -1107,7 +1107,7 @@ static void tcg_out_call(TCGContext *s, tcg_insn_unit *arg)
} }
#if defined(CONFIG_SOFTMMU) #if defined(CONFIG_SOFTMMU)
#include "../tcg-ldst.inc.c" #include "../tcg-ldst.c.inc"
static void * const qemu_ld_helpers[16] = { static void * const qemu_ld_helpers[16] = {
[MO_UB] = helper_ret_ldub_mmu, [MO_UB] = helper_ret_ldub_mmu,

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@ -23,7 +23,7 @@
*/ */
#include "elf.h" #include "elf.h"
#include "../tcg-pool.inc.c" #include "../tcg-pool.c.inc"
#if defined _CALL_DARWIN || defined __APPLE__ #if defined _CALL_DARWIN || defined __APPLE__
#define TCG_TARGET_CALL_DARWIN #define TCG_TARGET_CALL_DARWIN
@ -1845,7 +1845,7 @@ static const uint32_t qemu_exts_opc[4] = {
}; };
#if defined (CONFIG_SOFTMMU) #if defined (CONFIG_SOFTMMU)
#include "../tcg-ldst.inc.c" #include "../tcg-ldst.c.inc"
/* helper signature: helper_ld_mmu(CPUState *env, target_ulong addr, /* helper signature: helper_ld_mmu(CPUState *env, target_ulong addr,
* int mmu_idx, uintptr_t ra) * int mmu_idx, uintptr_t ra)

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@ -27,7 +27,7 @@
* THE SOFTWARE. * THE SOFTWARE.
*/ */
#include "../tcg-pool.inc.c" #include "../tcg-pool.c.inc"
#ifdef CONFIG_DEBUG_TCG #ifdef CONFIG_DEBUG_TCG
static const char * const tcg_target_reg_names[TCG_TARGET_NB_REGS] = { static const char * const tcg_target_reg_names[TCG_TARGET_NB_REGS] = {
@ -919,7 +919,7 @@ static void tcg_out_mb(TCGContext *s, TCGArg a0)
*/ */
#if defined(CONFIG_SOFTMMU) #if defined(CONFIG_SOFTMMU)
#include "../tcg-ldst.inc.c" #include "../tcg-ldst.c.inc"
/* helper signature: helper_ret_ld_mmu(CPUState *env, target_ulong addr, /* helper signature: helper_ret_ld_mmu(CPUState *env, target_ulong addr,
* TCGMemOpIdx oi, uintptr_t ra) * TCGMemOpIdx oi, uintptr_t ra)

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@ -29,7 +29,7 @@
#error "unsupported code generation mode" #error "unsupported code generation mode"
#endif #endif
#include "../tcg-pool.inc.c" #include "../tcg-pool.c.inc"
#include "elf.h" #include "elf.h"
/* ??? The translation blocks produced by TCG are generally small enough to /* ??? The translation blocks produced by TCG are generally small enough to
@ -1536,7 +1536,7 @@ static void tcg_out_qemu_st_direct(TCGContext *s, MemOp opc, TCGReg data,
} }
#if defined(CONFIG_SOFTMMU) #if defined(CONFIG_SOFTMMU)
#include "../tcg-ldst.inc.c" #include "../tcg-ldst.c.inc"
/* We're expecting to use a 20-bit negative offset on the tlb memory ops. */ /* We're expecting to use a 20-bit negative offset on the tlb memory ops. */
QEMU_BUILD_BUG_ON(TLB_MASK_TABLE_OFS(0) > 0); QEMU_BUILD_BUG_ON(TLB_MASK_TABLE_OFS(0) > 0);

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@ -22,7 +22,7 @@
* THE SOFTWARE. * THE SOFTWARE.
*/ */
#include "../tcg-pool.inc.c" #include "../tcg-pool.c.inc"
#ifdef CONFIG_DEBUG_TCG #ifdef CONFIG_DEBUG_TCG
static const char * const tcg_target_reg_names[TCG_TARGET_NB_REGS] = { static const char * const tcg_target_reg_names[TCG_TARGET_NB_REGS] = {

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@ -118,7 +118,7 @@ static inline void new_pool_l8(TCGContext *s, int rtype, tcg_insn_unit *label,
new_pool_insert(s, n); new_pool_insert(s, n);
} }
/* To be provided by cpu/tcg-target.inc.c. */ /* To be provided by cpu/tcg-target.c.inc. */
static void tcg_out_nop_fill(tcg_insn_unit *p, int count); static void tcg_out_nop_fill(tcg_insn_unit *p, int count);
static int tcg_out_pool_finalize(TCGContext *s) static int tcg_out_pool_finalize(TCGContext *s)

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@ -65,7 +65,7 @@
#include "exec/log.h" #include "exec/log.h"
#include "sysemu/sysemu.h" #include "sysemu/sysemu.h"
/* Forward declarations for functions declared in tcg-target.inc.c and /* Forward declarations for functions declared in tcg-target.c.inc and
used here. */ used here. */
static void tcg_target_init(TCGContext *s); static void tcg_target_init(TCGContext *s);
static const TCGTargetOpDef *tcg_target_op_def(TCGOpcode); static const TCGTargetOpDef *tcg_target_op_def(TCGOpcode);
@ -101,7 +101,7 @@ static void tcg_register_jit_int(void *buf, size_t size,
size_t debug_frame_size) size_t debug_frame_size)
__attribute__((unused)); __attribute__((unused));
/* Forward declarations for functions declared and used in tcg-target.inc.c. */ /* Forward declarations for functions declared and used in tcg-target.c.inc. */
static const char *target_parse_constraint(TCGArgConstraint *ct, static const char *target_parse_constraint(TCGArgConstraint *ct,
const char *ct_str, TCGType type); const char *ct_str, TCGType type);
static void tcg_out_ld(TCGContext *s, TCGType type, TCGReg ret, TCGReg arg1, static void tcg_out_ld(TCGContext *s, TCGType type, TCGReg ret, TCGReg arg1,
@ -341,7 +341,7 @@ static void set_jmp_reset_offset(TCGContext *s, int which)
assert(s->tb_jmp_reset_offset[which] == off); assert(s->tb_jmp_reset_offset[which] == off);
} }
#include "tcg-target.inc.c" #include "tcg-target.c.inc"
/* compare a pointer @ptr and a tb_tc @s */ /* compare a pointer @ptr and a tb_tc @s */
static int ptr_cmp_tb_tc(const void *ptr, const struct tb_tc *s) static int ptr_cmp_tb_tc(const void *ptr, const struct tb_tc *s)

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@ -21,7 +21,7 @@ This is what TCI (Tiny Code Interpreter) does.
2) Implementation 2) Implementation
Like each TCG host frontend, TCI implements the code generator in Like each TCG host frontend, TCI implements the code generator in
tcg-target.inc.c, tcg-target.h. Both files are in directory tcg/tci. tcg-target.c.inc, tcg-target.h. Both files are in directory tcg/tci.
The additional file tcg/tci.c adds the interpreter. The additional file tcg/tci.c adds the interpreter.
@ -123,7 +123,7 @@ u1 = linux-user-test works
would also improve speed for hosts which support byte alignment). would also improve speed for hosts which support byte alignment).
* A better disassembler for the pseudo code would be nice (a very primitive * A better disassembler for the pseudo code would be nice (a very primitive
disassembler is included in tcg-target.inc.c). disassembler is included in tcg-target.c.inc).
* It might be useful to have a runtime option which selects the native TCG * It might be useful to have a runtime option which selects the native TCG
or TCI, so QEMU would have to include two TCGs. Today, selecting TCI or TCI, so QEMU would have to include two TCGs. Today, selecting TCI

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@ -116,7 +116,7 @@ static void usage_complete(int argc, char *argv[])
} }
/* keep wrappers separate but do not bother defining headers for all of them */ /* keep wrappers separate but do not bother defining headers for all of them */
#include "wrap.inc.c" #include "wrap.c.inc"
static void not_implemented(void) static void not_implemented(void)
{ {

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@ -4,23 +4,23 @@
#include "standard-headers/linux/input.h" #include "standard-headers/linux/input.h"
#include "ui/input-keymap-atset1-to-qcode.c" #include "ui/input-keymap-atset1-to-qcode.c.inc"
#include "ui/input-keymap-linux-to-qcode.c" #include "ui/input-keymap-linux-to-qcode.c.inc"
#include "ui/input-keymap-qcode-to-atset1.c" #include "ui/input-keymap-qcode-to-atset1.c.inc"
#include "ui/input-keymap-qcode-to-atset2.c" #include "ui/input-keymap-qcode-to-atset2.c.inc"
#include "ui/input-keymap-qcode-to-atset3.c" #include "ui/input-keymap-qcode-to-atset3.c.inc"
#include "ui/input-keymap-qcode-to-linux.c" #include "ui/input-keymap-qcode-to-linux.c.inc"
#include "ui/input-keymap-qcode-to-qnum.c" #include "ui/input-keymap-qcode-to-qnum.c.inc"
#include "ui/input-keymap-qcode-to-sun.c" #include "ui/input-keymap-qcode-to-sun.c.inc"
#include "ui/input-keymap-qnum-to-qcode.c" #include "ui/input-keymap-qnum-to-qcode.c.inc"
#include "ui/input-keymap-usb-to-qcode.c" #include "ui/input-keymap-usb-to-qcode.c.inc"
#include "ui/input-keymap-win32-to-qcode.c" #include "ui/input-keymap-win32-to-qcode.c.inc"
#include "ui/input-keymap-x11-to-qcode.c" #include "ui/input-keymap-x11-to-qcode.c.inc"
#include "ui/input-keymap-xorgevdev-to-qcode.c" #include "ui/input-keymap-xorgevdev-to-qcode.c.inc"
#include "ui/input-keymap-xorgkbd-to-qcode.c" #include "ui/input-keymap-xorgkbd-to-qcode.c.inc"
#include "ui/input-keymap-xorgxquartz-to-qcode.c" #include "ui/input-keymap-xorgxquartz-to-qcode.c.inc"
#include "ui/input-keymap-xorgxwin-to-qcode.c" #include "ui/input-keymap-xorgxwin-to-qcode.c.inc"
#include "ui/input-keymap-osx-to-qcode.c" #include "ui/input-keymap-osx-to-qcode.c.inc"
int qemu_input_linux_to_qcode(unsigned int lnx) int qemu_input_linux_to_qcode(unsigned int lnx)
{ {

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@ -199,56 +199,56 @@ static void zrle_write_u8(VncState *vs, uint8_t value)
#define ZRLE_BPP 8 #define ZRLE_BPP 8
#define ZYWRLE_ENDIAN ENDIAN_NO #define ZYWRLE_ENDIAN ENDIAN_NO
#include "vnc-enc-zrle.inc.c" #include "vnc-enc-zrle.c.inc"
#undef ZRLE_BPP #undef ZRLE_BPP
#define ZRLE_BPP 15 #define ZRLE_BPP 15
#undef ZYWRLE_ENDIAN #undef ZYWRLE_ENDIAN
#define ZYWRLE_ENDIAN ENDIAN_LITTLE #define ZYWRLE_ENDIAN ENDIAN_LITTLE
#include "vnc-enc-zrle.inc.c" #include "vnc-enc-zrle.c.inc"
#undef ZYWRLE_ENDIAN #undef ZYWRLE_ENDIAN
#define ZYWRLE_ENDIAN ENDIAN_BIG #define ZYWRLE_ENDIAN ENDIAN_BIG
#include "vnc-enc-zrle.inc.c" #include "vnc-enc-zrle.c.inc"
#undef ZRLE_BPP #undef ZRLE_BPP
#define ZRLE_BPP 16 #define ZRLE_BPP 16
#undef ZYWRLE_ENDIAN #undef ZYWRLE_ENDIAN
#define ZYWRLE_ENDIAN ENDIAN_LITTLE #define ZYWRLE_ENDIAN ENDIAN_LITTLE
#include "vnc-enc-zrle.inc.c" #include "vnc-enc-zrle.c.inc"
#undef ZYWRLE_ENDIAN #undef ZYWRLE_ENDIAN
#define ZYWRLE_ENDIAN ENDIAN_BIG #define ZYWRLE_ENDIAN ENDIAN_BIG
#include "vnc-enc-zrle.inc.c" #include "vnc-enc-zrle.c.inc"
#undef ZRLE_BPP #undef ZRLE_BPP
#define ZRLE_BPP 32 #define ZRLE_BPP 32
#undef ZYWRLE_ENDIAN #undef ZYWRLE_ENDIAN
#define ZYWRLE_ENDIAN ENDIAN_LITTLE #define ZYWRLE_ENDIAN ENDIAN_LITTLE
#include "vnc-enc-zrle.inc.c" #include "vnc-enc-zrle.c.inc"
#undef ZYWRLE_ENDIAN #undef ZYWRLE_ENDIAN
#define ZYWRLE_ENDIAN ENDIAN_BIG #define ZYWRLE_ENDIAN ENDIAN_BIG
#include "vnc-enc-zrle.inc.c" #include "vnc-enc-zrle.c.inc"
#define ZRLE_COMPACT_PIXEL 24a #define ZRLE_COMPACT_PIXEL 24a
#undef ZYWRLE_ENDIAN #undef ZYWRLE_ENDIAN
#define ZYWRLE_ENDIAN ENDIAN_LITTLE #define ZYWRLE_ENDIAN ENDIAN_LITTLE
#include "vnc-enc-zrle.inc.c" #include "vnc-enc-zrle.c.inc"
#undef ZYWRLE_ENDIAN #undef ZYWRLE_ENDIAN
#define ZYWRLE_ENDIAN ENDIAN_BIG #define ZYWRLE_ENDIAN ENDIAN_BIG
#include "vnc-enc-zrle.inc.c" #include "vnc-enc-zrle.c.inc"
#undef ZRLE_COMPACT_PIXEL #undef ZRLE_COMPACT_PIXEL
#define ZRLE_COMPACT_PIXEL 24b #define ZRLE_COMPACT_PIXEL 24b
#undef ZYWRLE_ENDIAN #undef ZYWRLE_ENDIAN
#define ZYWRLE_ENDIAN ENDIAN_LITTLE #define ZYWRLE_ENDIAN ENDIAN_LITTLE
#include "vnc-enc-zrle.inc.c" #include "vnc-enc-zrle.c.inc"
#undef ZYWRLE_ENDIAN #undef ZYWRLE_ENDIAN
#define ZYWRLE_ENDIAN ENDIAN_BIG #define ZYWRLE_ENDIAN ENDIAN_BIG
#include "vnc-enc-zrle.inc.c" #include "vnc-enc-zrle.c.inc"
#undef ZRLE_COMPACT_PIXEL #undef ZRLE_COMPACT_PIXEL
#undef ZRLE_BPP #undef ZRLE_BPP