target-arm: add arm_is_secure() function
arm_is_secure() function allows to determine CPU security state if the CPU implements Security Extensions/EL3. arm_is_secure_below_el3() returns true if CPU is in secure state below EL3. Signed-off-by: Sergey Fedorov <s.fedorov@samsung.com> Signed-off-by: Fabian Aggeler <aggelerf@ethz.ch> Signed-off-by: Greg Bellows <greg.bellows@linaro.org> Reviewed-by: Peter Maydell <peter.maydell@linaro.org> Message-id: 1413910544-20150-3-git-send-email-greg.bellows@linaro.org Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
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@ -753,6 +753,53 @@ static inline int arm_feature(CPUARMState *env, int feature)
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return (env->features & (1ULL << feature)) != 0;
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}
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#if !defined(CONFIG_USER_ONLY)
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/* Return true if exception levels below EL3 are in secure state,
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* or would be following an exception return to that level.
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* Unlike arm_is_secure() (which is always a question about the
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* _current_ state of the CPU) this doesn't care about the current
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* EL or mode.
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*/
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static inline bool arm_is_secure_below_el3(CPUARMState *env)
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{
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if (arm_feature(env, ARM_FEATURE_EL3)) {
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return !(env->cp15.scr_el3 & SCR_NS);
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} else {
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/* If EL2 is not supported then the secure state is implementation
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* defined, in which case QEMU defaults to non-secure.
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*/
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return false;
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}
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}
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/* Return true if the processor is in secure state */
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static inline bool arm_is_secure(CPUARMState *env)
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{
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if (arm_feature(env, ARM_FEATURE_EL3)) {
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if (is_a64(env) && extract32(env->pstate, 2, 2) == 3) {
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/* CPU currently in AArch64 state and EL3 */
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return true;
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} else if (!is_a64(env) &&
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(env->uncached_cpsr & CPSR_M) == ARM_CPU_MODE_MON) {
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/* CPU currently in AArch32 state and monitor mode */
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return true;
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}
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}
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return arm_is_secure_below_el3(env);
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}
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#else
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static inline bool arm_is_secure_below_el3(CPUARMState *env)
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{
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return false;
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}
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static inline bool arm_is_secure(CPUARMState *env)
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{
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return false;
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}
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#endif
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/* Return true if the specified exception level is running in AArch64 state. */
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static inline bool arm_el_is_aa64(CPUARMState *env, int el)
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{
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