target/ppc: Implement ppc_cpu_record_sigsegv
Record DAR, DSISR, and exception_index. That last means that we must exit to cpu_loop ourselves, instead of letting exception_index being overwritten. This is exactly what the user-mode ppc_cpu_tlb_fill does, so simply rename it as ppc_cpu_record_sigsegv. Reviewed-by: Warner Losh <imp@bsdimp.com> Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org> Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
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@ -1302,9 +1302,6 @@ extern const VMStateDescription vmstate_ppc_cpu;
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/*****************************************************************************/
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/*****************************************************************************/
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void ppc_translate_init(void);
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void ppc_translate_init(void);
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bool ppc_cpu_tlb_fill(CPUState *cs, vaddr address, int size,
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MMUAccessType access_type, int mmu_idx,
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bool probe, uintptr_t retaddr);
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#if !defined(CONFIG_USER_ONLY)
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#if !defined(CONFIG_USER_ONLY)
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void ppc_store_sdr1(CPUPPCState *env, target_ulong value);
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void ppc_store_sdr1(CPUPPCState *env, target_ulong value);
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@ -9014,9 +9014,11 @@ static const struct SysemuCPUOps ppc_sysemu_ops = {
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static const struct TCGCPUOps ppc_tcg_ops = {
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static const struct TCGCPUOps ppc_tcg_ops = {
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.initialize = ppc_translate_init,
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.initialize = ppc_translate_init,
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.tlb_fill = ppc_cpu_tlb_fill,
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#ifndef CONFIG_USER_ONLY
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#ifdef CONFIG_USER_ONLY
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.record_sigsegv = ppc_cpu_record_sigsegv,
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#else
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.tlb_fill = ppc_cpu_tlb_fill,
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.cpu_exec_interrupt = ppc_cpu_exec_interrupt,
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.cpu_exec_interrupt = ppc_cpu_exec_interrupt,
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.do_interrupt = ppc_cpu_do_interrupt,
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.do_interrupt = ppc_cpu_do_interrupt,
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.cpu_exec_enter = ppc_cpu_exec_enter,
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.cpu_exec_enter = ppc_cpu_exec_enter,
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@ -283,5 +283,14 @@ static inline void pte_invalidate(target_ulong *pte0)
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#define PTE_PTEM_MASK 0x7FFFFFBF
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#define PTE_PTEM_MASK 0x7FFFFFBF
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#define PTE_CHECK_MASK (TARGET_PAGE_MASK | 0x7B)
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#define PTE_CHECK_MASK (TARGET_PAGE_MASK | 0x7B)
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#ifdef CONFIG_USER_ONLY
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void ppc_cpu_record_sigsegv(CPUState *cs, vaddr addr,
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MMUAccessType access_type,
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bool maperr, uintptr_t ra);
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#else
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bool ppc_cpu_tlb_fill(CPUState *cs, vaddr address, int size,
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MMUAccessType access_type, int mmu_idx,
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bool probe, uintptr_t retaddr);
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#endif
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#endif /* PPC_INTERNAL_H */
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#endif /* PPC_INTERNAL_H */
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@ -21,16 +21,23 @@
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#include "qemu/osdep.h"
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#include "qemu/osdep.h"
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#include "cpu.h"
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#include "cpu.h"
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#include "exec/exec-all.h"
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#include "exec/exec-all.h"
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#include "internal.h"
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void ppc_cpu_record_sigsegv(CPUState *cs, vaddr address,
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bool ppc_cpu_tlb_fill(CPUState *cs, vaddr address, int size,
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MMUAccessType access_type,
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MMUAccessType access_type, int mmu_idx,
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bool maperr, uintptr_t retaddr)
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bool probe, uintptr_t retaddr)
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{
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{
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PowerPCCPU *cpu = POWERPC_CPU(cs);
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PowerPCCPU *cpu = POWERPC_CPU(cs);
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CPUPPCState *env = &cpu->env;
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CPUPPCState *env = &cpu->env;
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int exception, error_code;
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int exception, error_code;
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/*
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* Both DSISR and the "trap number" (exception vector offset,
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* looked up from exception_index) are present in the linux-user
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* signal frame.
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* FIXME: we don't actually populate the trap number properly.
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* It would be easiest to fill in an env->trap value now.
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*/
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if (access_type == MMU_INST_FETCH) {
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if (access_type == MMU_INST_FETCH) {
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exception = POWERPC_EXCP_ISI;
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exception = POWERPC_EXCP_ISI;
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error_code = 0x40000000;
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error_code = 0x40000000;
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