RISC-V Build Infrastructure

This adds RISC-V into the build system enabling the following targets:

- riscv32-softmmu
- riscv64-softmmu
- riscv32-linux-user
- riscv64-linux-user

This adds defaults configs for RISC-V, enables the build for the RISC-V
CPU core, hardware, and Linux User Emulation. The 'qemu-binfmt-conf.sh'
script is updated to add the RISC-V ELF magic.

Expected checkpatch errors for consistency reasons:

ERROR: line over 90 characters
FILE: scripts/qemu-binfmt-conf.sh

Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Signed-off-by: Sagar Karandikar <sagark@eecs.berkeley.edu>
Signed-off-by: Michael Clark <mjc@sifive.com>
This commit is contained in:
Michael Clark 2018-03-03 01:32:59 +13:00
parent a7240d1e4a
commit 25fa194b7b
No known key found for this signature in database
GPG Key ID: 6BF1D7B357EF3E4F
12 changed files with 72 additions and 2 deletions

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@ -71,6 +71,8 @@ int graphic_depth = 32;
#define QEMU_ARCH QEMU_ARCH_OPENRISC
#elif defined(TARGET_PPC)
#define QEMU_ARCH QEMU_ARCH_PPC
#elif defined(TARGET_RISCV)
#define QEMU_ARCH QEMU_ARCH_RISCV
#elif defined(TARGET_S390X)
#define QEMU_ARCH QEMU_ARCH_S390X
#elif defined(TARGET_SH4)

13
configure vendored
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@ -6797,6 +6797,16 @@ case "$target_name" in
echo "TARGET_ABI32=y" >> $config_target_mak
gdb_xml_files="power64-core.xml power-fpu.xml power-altivec.xml power-spe.xml power-vsx.xml"
;;
riscv32)
TARGET_BASE_ARCH=riscv
TARGET_ABI_DIR=riscv
mttcg=yes
;;
riscv64)
TARGET_BASE_ARCH=riscv
TARGET_ABI_DIR=riscv
mttcg=yes
;;
sh4|sh4eb)
TARGET_ARCH=sh4
bflt="yes"
@ -6966,6 +6976,9 @@ for i in $ARCH $TARGET_BASE_ARCH ; do
ppc*)
disas_config "PPC"
;;
riscv)
disas_config "RISCV"
;;
s390*)
disas_config "S390"
;;

6
cpus.c
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@ -2081,6 +2081,9 @@ CpuInfoList *qmp_query_cpus(Error **errp)
#elif defined(TARGET_SPARC)
SPARCCPU *sparc_cpu = SPARC_CPU(cpu);
CPUSPARCState *env = &sparc_cpu->env;
#elif defined(TARGET_RISCV)
RISCVCPU *riscv_cpu = RISCV_CPU(cpu);
CPURISCVState *env = &riscv_cpu->env;
#elif defined(TARGET_MIPS)
MIPSCPU *mips_cpu = MIPS_CPU(cpu);
CPUMIPSState *env = &mips_cpu->env;
@ -2120,6 +2123,9 @@ CpuInfoList *qmp_query_cpus(Error **errp)
#elif defined(TARGET_S390X)
info->value->arch = CPU_INFO_ARCH_S390;
info->value->u.s390.cpu_state = env->cpu_state;
#elif defined(TARGET_RISCV)
info->value->arch = CPU_INFO_ARCH_RISCV;
info->value->u.riscv.pc = env->pc;
#else
info->value->arch = CPU_INFO_ARCH_OTHER;
#endif

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@ -0,0 +1 @@
# Default configuration for riscv-linux-user

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@ -0,0 +1,4 @@
# Default configuration for riscv-softmmu
CONFIG_SERIAL=y
CONFIG_VIRTIO=y

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@ -0,0 +1 @@
# Default configuration for riscv-linux-user

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@ -0,0 +1,4 @@
# Default configuration for riscv-softmmu
CONFIG_SERIAL=y
CONFIG_VIRTIO=y

11
hw/riscv/Makefile.objs Normal file
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@ -0,0 +1,11 @@
obj-y += riscv_htif.o
obj-y += riscv_hart.o
obj-y += sifive_e.o
obj-y += sifive_clint.o
obj-y += sifive_prci.o
obj-y += sifive_plic.o
obj-y += sifive_test.o
obj-y += sifive_u.o
obj-y += sifive_uart.o
obj-y += spike.o
obj-y += virt.o

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@ -24,6 +24,7 @@ enum {
QEMU_ARCH_TRICORE = (1 << 16),
QEMU_ARCH_NIOS2 = (1 << 17),
QEMU_ARCH_HPPA = (1 << 18),
QEMU_ARCH_RISCV = (1 << 19),
};
extern const uint32_t arch_type;

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@ -320,10 +320,12 @@
#
# @s390: since 2.12
#
# @riscv: since 2.12
#
# Since: 2.6
##
{ 'enum': 'CpuInfoArch',
'data': ['x86', 'sparc', 'ppc', 'mips', 'tricore', 's390', 'other' ] }
'data': ['x86', 'sparc', 'ppc', 'mips', 'tricore', 's390', 'riscv', 'other' ] }
##
# @CpuInfo:
@ -363,6 +365,7 @@
'mips': 'CpuInfoMIPS',
'tricore': 'CpuInfoTricore',
's390': 'CpuInfoS390',
'riscv': 'CpuInfoRISCV',
'other': 'CpuInfoOther' } }
##
@ -422,6 +425,17 @@
##
{ 'struct': 'CpuInfoTricore', 'data': { 'PC': 'int' } }
##
# @CpuInfoRISCV:
#
# Additional information about a virtual RISCV CPU
#
# @pc: the instruction pointer
#
# Since 2.12
##
{ 'struct': 'CpuInfoRISCV', 'data': { 'pc': 'int' } }
##
# @CpuInfoOther:
#
@ -533,6 +547,7 @@
'mips': 'CpuInfoOther',
'tricore': 'CpuInfoOther',
's390': 'CpuInfoS390',
'riscv': 'CpuInfoRISCV',
'other': 'CpuInfoOther' } }
##

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@ -4,7 +4,7 @@
qemu_target_list="i386 i486 alpha arm armeb sparc32plus ppc ppc64 ppc64le m68k \
mips mipsel mipsn32 mipsn32el mips64 mips64el \
sh4 sh4eb s390x aarch64 aarch64_be hppa"
sh4 sh4eb s390x aarch64 aarch64_be hppa riscv32 riscv64"
i386_magic='\x7fELF\x01\x01\x01\x00\x00\x00\x00\x00\x00\x00\x00\x00\x02\x00\x03\x00'
i386_mask='\xff\xff\xff\xff\xff\xfe\xfe\xff\xff\xff\xff\xff\xff\xff\xff\xff\xfe\xff\xff\xff'
@ -100,6 +100,14 @@ hppa_magic='\x7f\x45\x4c\x46\x01\x02\x01\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00
hppa_mask='\xff\xff\xff\xff\xff\xff\xff\x00\xff\xff\xff\xff\xff\xff\xff\xff\xff\xfe\xff\xff'
hppa_family=hppa
riscv32_magic='\x7fELF\x01\x01\x01\x00\x00\x00\x00\x00\x00\x00\x00\x00\x02\x00\xf3\x00'
riscv32_mask='\xff\xff\xff\xff\xff\xff\xff\x00\xff\xff\xff\xff\xff\xff\xff\xff\xfe\xff\xff\xff'
riscv32_family=riscv
riscv64_magic='\x7fELF\x02\x01\x01\x00\x00\x00\x00\x00\x00\x00\x00\x00\x02\x00\xf3\x00'
riscv64_mask='\xff\xff\xff\xff\xff\xff\xff\x00\xff\xff\xff\xff\xff\xff\xff\xff\xfe\xff\xff\xff'
riscv64_family=riscv
qemu_get_family() {
cpu=${HOST_ARCH:-$(uname -m)}
case "$cpu" in
@ -124,6 +132,9 @@ qemu_get_family() {
sparc*)
echo "sparc"
;;
riscv*)
echo "riscv"
;;
*)
echo "$cpu"
;;

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@ -0,0 +1 @@
obj-y += translate.o op_helper.o helper.o cpu.o fpu_helper.o gdbstub.o pmp.o