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SHIX board emulation (Samuel Tardieu)

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git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@1862 c046a42c-6fe2-441c-8c8c-71466251a162
This commit is contained in:
bellard 2006-04-27 21:32:09 +00:00
parent fdf9b3e831
commit 27c7ca7e77
11 changed files with 3066 additions and 3 deletions
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1
Changelog
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@ -6,6 +6,7 @@ version 0.8.1:
- IDE LBA48 support (Jens Axboe)
- SSE3 support
- Solaris port (Ben Taylor)
- Preliminary SH4 target (Samuel Tardieu)
version 0.8.0:

6
Makefile.target
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@ -476,10 +476,10 @@ ifeq ($(TARGET_ARCH), sh4)
op.o: op.c op_mem.c cpu.h
op_helper.o: op_helper.c exec.h cpu.h
helper.o: helper.c exec.h cpu.h
sh7750.o: sh7750.c sh7750.h sh7750_regs.h sh7750_regnames.h cpu.h
shix.o: shix.c sh7750.h sh7750_regs.h sh7750_regnames.h tc58128.h
sh7750.o: sh7750.c sh7750_regs.h sh7750_regnames.h cpu.h
shix.o: shix.c sh7750_regs.h sh7750_regnames.h
sh7750_regnames.o: sh7750_regnames.c sh7750_regnames.h sh7750_regs.h
tc58128.o: tc58128.c tc58128.h sh7750.h
tc58128.o: tc58128.c
endif
%.o: %.c

836
hw/sh7750.c Normal file
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@ -0,0 +1,836 @@
/*
* SH7750 device
*
* Copyright (c) 2005 Samuel Tardieu
*
* Permission is hereby granted, free of charge, to any person obtaining a copy
* of this software and associated documentation files (the "Software"), to deal
* in the Software without restriction, including without limitation the rights
* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
* copies of the Software, and to permit persons to whom the Software is
* furnished to do so, subject to the following conditions:
*
* The above copyright notice and this permission notice shall be included in
* all copies or substantial portions of the Software.
*
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
* THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
* OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
* THE SOFTWARE.
*/
#include <stdio.h>
#include <assert.h>
#include "vl.h"
#include "sh7750_regs.h"
#include "sh7750_regnames.h"
typedef struct {
uint8_t data[16];
uint8_t length; /* Number of characters in the FIFO */
uint8_t write_idx; /* Index of first character to write */
uint8_t read_idx; /* Index of first character to read */
} fifo;
#define NB_DEVICES 4
typedef struct SH7750State {
/* CPU */
CPUSH4State *cpu;
/* Peripheral frequency in Hz */
uint32_t periph_freq;
/* SDRAM controller */
uint16_t rfcr;
/* First serial port */
CharDriverState *serial1;
uint8_t scscr1;
uint8_t scsmr1;
uint8_t scbrr1;
uint8_t scssr1;
uint8_t scssr1_read;
uint8_t sctsr1;
uint8_t sctsr1_loaded;
uint8_t sctdr1;
uint8_t scrdr1;
/* Second serial port */
CharDriverState *serial2;
uint16_t sclsr2;
uint16_t scscr2;
uint16_t scfcr2;
uint16_t scfsr2;
uint16_t scsmr2;
uint8_t scbrr2;
fifo serial2_receive_fifo;
fifo serial2_transmit_fifo;
/* Timers */
uint8_t tstr;
/* Timer 0 */
QEMUTimer *timer0;
uint16_t tcr0;
uint32_t tcor0;
uint32_t tcnt0;
/* IO ports */
uint16_t gpioic;
uint32_t pctra;
uint32_t pctrb;
uint16_t portdira; /* Cached */
uint16_t portpullupa; /* Cached */
uint16_t portdirb; /* Cached */
uint16_t portpullupb; /* Cached */
uint16_t pdtra;
uint16_t pdtrb;
uint16_t periph_pdtra; /* Imposed by the peripherals */
uint16_t periph_portdira; /* Direction seen from the peripherals */
uint16_t periph_pdtrb; /* Imposed by the peripherals */
uint16_t periph_portdirb; /* Direction seen from the peripherals */
sh7750_io_device *devices[NB_DEVICES]; /* External peripherals */
/* Cache */
uint32_t ccr;
} SH7750State;
/**********************************************************************
Timers
**********************************************************************/
/* XXXXX At this time, timer0 works in underflow only mode, that is
the value of tcnt0 is read at alarm computation time and cannot
be read back by the guest OS */
static void start_timer0(SH7750State * s)
{
uint64_t now, next, prescaler;
if ((s->tcr0 & 6) == 6) {
fprintf(stderr, "rtc clock for timer 0 not supported\n");
assert(0);
}
if ((s->tcr0 & 7) == 5) {
fprintf(stderr, "timer 0 configuration not supported\n");
assert(0);
}
if ((s->tcr0 & 4) == 4)
prescaler = 1024;
else
prescaler = 4 << (s->tcr0 & 3);
now = qemu_get_clock(vm_clock);
/* XXXXX */
next =
now + muldiv64(prescaler * s->tcnt0, ticks_per_sec,
s->periph_freq);
if (next == now)
next = now + 1;
fprintf(stderr, "now=%016llx, next=%016llx\n", now, next);
fprintf(stderr, "timer will underflow in %f seconds\n",
(float) (next - now) / (float) ticks_per_sec);
qemu_mod_timer(s->timer0, next);
}
static void timer_start_changed(SH7750State * s)
{
if (s->tstr & SH7750_TSTR_STR0) {
start_timer0(s);
} else {
fprintf(stderr, "timer 0 is stopped\n");
qemu_del_timer(s->timer0);
}
}
static void timer0_cb(void *opaque)
{
SH7750State *s = opaque;
s->tcnt0 = (uint32_t) 0; /* XXXXX */
if (--s->tcnt0 == (uint32_t) - 1) {
fprintf(stderr, "timer 0 underflow\n");
s->tcnt0 = s->tcor0;
s->tcr0 |= SH7750_TCR_UNF;
if (s->tcr0 & SH7750_TCR_UNIE) {
fprintf(stderr,
"interrupt generation for timer 0 not supported\n");
assert(0);
}
}
start_timer0(s);
}
static void init_timers(SH7750State * s)
{
s->tcor0 = 0xffffffff;
s->tcnt0 = 0xffffffff;
s->timer0 = qemu_new_timer(vm_clock, &timer0_cb, s);
}
/**********************************************************************
First serial port
**********************************************************************/
static int serial1_can_receive(void *opaque)
{
SH7750State *s = opaque;
return s->scscr1 & SH7750_SCSCR_RE;
}
static void serial1_receive_char(SH7750State * s, uint8_t c)
{
if (s->scssr1 & SH7750_SCSSR1_RDRF) {
s->scssr1 |= SH7750_SCSSR1_ORER;
return;
}
s->scrdr1 = c;
s->scssr1 |= SH7750_SCSSR1_RDRF;
}
static void serial1_receive(void *opaque, const uint8_t * buf, int size)
{
SH7750State *s = opaque;
int i;
for (i = 0; i < size; i++) {
serial1_receive_char(s, buf[i]);
}
}
static void serial1_event(void *opaque, int event)
{
assert(0);
}
static void serial1_maybe_send(SH7750State * s)
{
uint8_t c;
if (s->scssr1 & SH7750_SCSSR1_TDRE)
return;
c = s->sctdr1;
s->scssr1 |= SH7750_SCSSR1_TDRE | SH7750_SCSSR1_TEND;
if (s->scscr1 & SH7750_SCSCR_TIE) {
fprintf(stderr, "interrupts for serial port 1 not implemented\n");
assert(0);
}
/* XXXXX Check for errors in write */
qemu_chr_write(s->serial1, &c, 1);
}
static void serial1_change_scssr1(SH7750State * s, uint8_t mem_value)
{
uint8_t new_flags;
/* If transmit disable, TDRE and TEND stays up */
if ((s->scscr1 & SH7750_SCSCR_TE) == 0) {
mem_value |= SH7750_SCSSR1_TDRE | SH7750_SCSSR1_TEND;
}
/* Only clear bits which have been read before and do not set any bit
in the flags */
new_flags = s->scssr1 & ~s->scssr1_read; /* Preserve unread flags */
new_flags &= mem_value | ~s->scssr1_read; /* Clear read flags */
s->scssr1 = (new_flags & 0xf8) | (mem_value & 1);
s->scssr1_read &= mem_value;
/* If TDRE has been cleared, TEND will also be cleared */
if ((s->scssr1 & SH7750_SCSSR1_TDRE) == 0) {
s->scssr1 &= ~SH7750_SCSSR1_TEND;
}
/* Check for transmission to start */
serial1_maybe_send(s);
}
static void serial1_update_parameters(SH7750State * s)
{
QEMUSerialSetParams ssp;
if (s->scsmr1 & SH7750_SCSMR_CHR_7)
ssp.data_bits = 7;
else
ssp.data_bits = 8;
if (s->scsmr1 & SH7750_SCSMR_PE) {
if (s->scsmr1 & SH7750_SCSMR_PM_ODD)
ssp.parity = 'O';
else
ssp.parity = 'E';
} else
ssp.parity = 'N';
if (s->scsmr1 & SH7750_SCSMR_STOP_2)
ssp.stop_bits = 2;
else
ssp.stop_bits = 1;
fprintf(stderr, "SCSMR1=%04x SCBRR1=%02x\n", s->scsmr1, s->scbrr1);
ssp.speed = s->periph_freq /
(32 * s->scbrr1 * (1 << (2 * (s->scsmr1 & 3)))) - 1;
fprintf(stderr, "data bits=%d, stop bits=%d, parity=%c, speed=%d\n",
ssp.data_bits, ssp.stop_bits, ssp.parity, ssp.speed);
qemu_chr_ioctl(s->serial1, CHR_IOCTL_SERIAL_SET_PARAMS, &ssp);
}
static void scscr1_changed(SH7750State * s)
{
if (s->scscr1 & (SH7750_SCSCR_TE | SH7750_SCSCR_RE)) {
if (!s->serial1) {
fprintf(stderr, "serial port 1 not bound to anything\n");
assert(0);
}
serial1_update_parameters(s);
}
if ((s->scscr1 & SH7750_SCSCR_RE) == 0) {
s->scssr1 |= SH7750_SCSSR1_TDRE;
}
}
static void init_serial1(SH7750State * s, int serial_nb)
{
CharDriverState *chr;
s->scssr1 = 0x84;
chr = serial_hds[serial_nb];
if (!chr) {
fprintf(stderr,
"no serial port associated to SH7750 first serial port\n");
return;
}
s->serial1 = chr;
qemu_chr_add_read_handler(chr, serial1_can_receive,
serial1_receive, s);
qemu_chr_add_event_handler(chr, serial1_event);
}
/**********************************************************************
Second serial port
**********************************************************************/
static int serial2_can_receive(void *opaque)
{
SH7750State *s = opaque;
static uint8_t max_fifo_size[] = { 15, 1, 4, 6, 8, 10, 12, 14 };
return s->serial2_receive_fifo.length <
max_fifo_size[(s->scfcr2 >> 9) & 7];
}
static void serial2_adjust_receive_flags(SH7750State * s)
{
static uint8_t max_fifo_size[] = { 1, 4, 8, 14 };
/* XXXXX Add interrupt generation */
if (s->serial2_receive_fifo.length >=
max_fifo_size[(s->scfcr2 >> 7) & 3]) {
s->scfsr2 |= SH7750_SCFSR2_RDF;
s->scfsr2 &= ~SH7750_SCFSR2_DR;
} else {
s->scfsr2 &= ~SH7750_SCFSR2_RDF;
if (s->serial2_receive_fifo.length > 0)
s->scfsr2 |= SH7750_SCFSR2_DR;
else
s->scfsr2 &= ~SH7750_SCFSR2_DR;
}
}
static void serial2_append_char(SH7750State * s, uint8_t c)
{
if (s->serial2_receive_fifo.length == 16) {
/* Overflow */
s->sclsr2 |= SH7750_SCLSR2_ORER;
return;
}
s->serial2_receive_fifo.data[s->serial2_receive_fifo.write_idx++] = c;
s->serial2_receive_fifo.length++;
serial2_adjust_receive_flags(s);
}
static void serial2_receive(void *opaque, const uint8_t * buf, int size)
{
SH7750State *s = opaque;
int i;
for (i = 0; i < size; i++)
serial2_append_char(s, buf[i]);
}
static void serial2_event(void *opaque, int event)
{
/* XXXXX */
assert(0);
}
static void serial2_update_parameters(SH7750State * s)
{
QEMUSerialSetParams ssp;
if (s->scsmr2 & SH7750_SCSMR_CHR_7)
ssp.data_bits = 7;
else
ssp.data_bits = 8;
if (s->scsmr2 & SH7750_SCSMR_PE) {
if (s->scsmr2 & SH7750_SCSMR_PM_ODD)
ssp.parity = 'O';
else
ssp.parity = 'E';
} else
ssp.parity = 'N';
if (s->scsmr2 & SH7750_SCSMR_STOP_2)
ssp.stop_bits = 2;
else
ssp.stop_bits = 1;
fprintf(stderr, "SCSMR2=%04x SCBRR2=%02x\n", s->scsmr2, s->scbrr2);
ssp.speed = s->periph_freq /
(32 * s->scbrr2 * (1 << (2 * (s->scsmr2 & 3)))) - 1;
fprintf(stderr, "data bits=%d, stop bits=%d, parity=%c, speed=%d\n",
ssp.data_bits, ssp.stop_bits, ssp.parity, ssp.speed);
qemu_chr_ioctl(s->serial2, CHR_IOCTL_SERIAL_SET_PARAMS, &ssp);
}
static void scscr2_changed(SH7750State * s)
{
if (s->scscr2 & (SH7750_SCSCR_TE | SH7750_SCSCR_RE)) {
if (!s->serial2) {
fprintf(stderr, "serial port 2 not bound to anything\n");
assert(0);
}
serial2_update_parameters(s);
}
}
static void init_serial2(SH7750State * s, int serial_nb)
{
CharDriverState *chr;
s->scfsr2 = 0x0060;
chr = serial_hds[serial_nb];
if (!chr) {
fprintf(stderr,
"no serial port associated to SH7750 second serial port\n");
return;
}
s->serial2 = chr;
qemu_chr_add_read_handler(chr, serial2_can_receive,
serial2_receive, s);
qemu_chr_add_event_handler(chr, serial2_event);
}
static void init_serial_ports(SH7750State * s)
{
init_serial1(s, 0);
init_serial2(s, 1);
}
/**********************************************************************
I/O ports
**********************************************************************/
int sh7750_register_io_device(SH7750State * s, sh7750_io_device * device)
{
int i;
for (i = 0; i < NB_DEVICES; i++) {
if (s->devices[i] == NULL) {
s->devices[i] = device;
return 0;
}
}
return -1;
}
static uint16_t portdir(uint32_t v)
{
#define EVENPORTMASK(n) ((v & (1<<((n)<<1))) >> (n))
return
EVENPORTMASK(15) | EVENPORTMASK(14) | EVENPORTMASK(13) |
EVENPORTMASK(12) | EVENPORTMASK(11) | EVENPORTMASK(10) |
EVENPORTMASK(9) | EVENPORTMASK(8) | EVENPORTMASK(7) |
EVENPORTMASK(6) | EVENPORTMASK(5) | EVENPORTMASK(4) |
EVENPORTMASK(3) | EVENPORTMASK(2) | EVENPORTMASK(1) |
EVENPORTMASK(0);
}
static uint16_t portpullup(uint32_t v)
{
#define ODDPORTMASK(n) ((v & (1<<(((n)<<1)+1))) >> (n))
return
ODDPORTMASK(15) | ODDPORTMASK(14) | ODDPORTMASK(13) |
ODDPORTMASK(12) | ODDPORTMASK(11) | ODDPORTMASK(10) |
ODDPORTMASK(9) | ODDPORTMASK(8) | ODDPORTMASK(7) | ODDPORTMASK(6) |
ODDPORTMASK(5) | ODDPORTMASK(4) | ODDPORTMASK(3) | ODDPORTMASK(2) |
ODDPORTMASK(1) | ODDPORTMASK(0);
}
static uint16_t porta_lines(SH7750State * s)
{
return (s->portdira & s->pdtra) | /* CPU */
(s->periph_portdira & s->periph_pdtra) | /* Peripherals */
(~(s->portdira | s->periph_portdira) & s->portpullupa); /* Pullups */
}
static uint16_t portb_lines(SH7750State * s)
{
return (s->portdirb & s->pdtrb) | /* CPU */
(s->periph_portdirb & s->periph_pdtrb) | /* Peripherals */
(~(s->portdirb | s->periph_portdirb) & s->portpullupb); /* Pullups */
}
static void gen_port_interrupts(SH7750State * s)
{
/* XXXXX interrupts not generated */
}
static void porta_changed(SH7750State * s, uint16_t prev)
{
uint16_t currenta, changes;
int i, r = 0;
#if 0
fprintf(stderr, "porta changed from 0x%04x to 0x%04x\n",
prev, porta_lines(s));
fprintf(stderr, "pdtra=0x%04x, pctra=0x%08x\n", s->pdtra, s->pctra);
#endif
currenta = porta_lines(s);
if (currenta == prev)
return;
changes = currenta ^ prev;
for (i = 0; i < NB_DEVICES; i++) {
if (s->devices[i] && (s->devices[i]->portamask_trigger & changes)) {
r |= s->devices[i]->port_change_cb(currenta, portb_lines(s),
&s->periph_pdtra,
&s->periph_portdira,
&s->periph_pdtrb,
&s->periph_portdirb);
}
}
if (r)
gen_port_interrupts(s);
}
static void portb_changed(SH7750State * s, uint16_t prev)
{
uint16_t currentb, changes;
int i, r = 0;
currentb = portb_lines(s);
if (currentb == prev)
return;
changes = currentb ^ prev;
for (i = 0; i < NB_DEVICES; i++) {
if (s->devices[i] && (s->devices[i]->portbmask_trigger & changes)) {
r |= s->devices[i]->port_change_cb(portb_lines(s), currentb,
&s->periph_pdtra,
&s->periph_portdira,
&s->periph_pdtrb,
&s->periph_portdirb);
}
}
if (r)
gen_port_interrupts(s);
}
/**********************************************************************
Memory
**********************************************************************/
static void error_access(const char *kind, target_phys_addr_t addr)
{
fprintf(stderr, "%s to %s (0x%08x) not supported\n",
kind, regname(addr), addr);
}
static void ignore_access(const char *kind, target_phys_addr_t addr)
{
fprintf(stderr, "%s to %s (0x%08x) ignored\n",
kind, regname(addr), addr);
}
static uint32_t sh7750_mem_readb(void *opaque, target_phys_addr_t addr)
{
SH7750State *s = opaque;
uint8_t r;
switch (addr) {
case SH7750_SCSSR1_A7:
r = s->scssr1;
s->scssr1_read |= r;
return s->scssr1;
case SH7750_SCRDR1_A7:
s->scssr1 &= ~SH7750_SCSSR1_RDRF;
return s->scrdr1;
default:
error_access("byte read", addr);
assert(0);
}
}
static uint32_t sh7750_mem_readw(void *opaque, target_phys_addr_t addr)
{
SH7750State *s = opaque;
uint16_t r;
switch (addr) {
case SH7750_RFCR_A7:
fprintf(stderr,
"Read access to refresh count register, incrementing\n");
return s->rfcr++;
case SH7750_TCR0_A7:
return s->tcr0;
case SH7750_SCLSR2_A7:
/* Read and clear overflow bit */
r = s->sclsr2;
s->sclsr2 = 0;
return r;
case SH7750_SCSFR2_A7:
return s->scfsr2;
case SH7750_PDTRA_A7:
return porta_lines(s);
case SH7750_PDTRB_A7:
return portb_lines(s);
default:
error_access("word read", addr);
assert(0);
}
}
static uint32_t sh7750_mem_readl(void *opaque, target_phys_addr_t addr)
{
SH7750State *s = opaque;
switch (addr) {
case SH7750_MMUCR_A7:
return s->cpu->mmucr;
case SH7750_PTEH_A7:
return s->cpu->pteh;
case SH7750_PTEL_A7:
return s->cpu->ptel;
case SH7750_TTB_A7:
return s->cpu->ttb;
case SH7750_TEA_A7:
return s->cpu->tea;
case SH7750_TRA_A7:
return s->cpu->tra;
case SH7750_EXPEVT_A7:
return s->cpu->expevt;
case SH7750_INTEVT_A7:
return s->cpu->intevt;
case SH7750_CCR_A7:
return s->ccr;
case 0x1f000030: /* Processor version PVR */
return 0x00050000; /* SH7750R */
case 0x1f000040: /* Processor version CVR */
return 0x00110000; /* Minimum caches */
case 0x1f000044: /* Processor version PRR */
return 0x00000100; /* SH7750R */
default:
error_access("long read", addr);
assert(0);
}
}
static void sh7750_mem_writeb(void *opaque, target_phys_addr_t addr,
uint32_t mem_value)
{
SH7750State *s = opaque;
switch (addr) {
/* PRECHARGE ? XXXXX */
case SH7750_PRECHARGE0_A7:
case SH7750_PRECHARGE1_A7:
ignore_access("byte write", addr);
return;
case SH7750_SCBRR2_A7:
s->scbrr2 = mem_value;
return;
case SH7750_TSTR_A7:
s->tstr = mem_value;
timer_start_changed(s);
return;
case SH7750_SCSCR1_A7:
s->scscr1 = mem_value;
scscr1_changed(s);
return;
case SH7750_SCSMR1_A7:
s->scsmr1 = mem_value;
return;
case SH7750_SCBRR1_A7:
s->scbrr1 = mem_value;
return;
case SH7750_SCTDR1_A7:
s->scssr1 &= ~SH7750_SCSSR1_TEND;
s->sctdr1 = mem_value;
return;
case SH7750_SCSSR1_A7:
serial1_change_scssr1(s, mem_value);
return;
default:
error_access("byte write", addr);
assert(0);
}
}
static void sh7750_mem_writew(void *opaque, target_phys_addr_t addr,
uint32_t mem_value)
{
SH7750State *s = opaque;
uint16_t temp;
switch (addr) {
/* SDRAM controller */
case SH7750_SCBRR1_A7:
case SH7750_SCBRR2_A7:
case SH7750_BCR2_A7:
case SH7750_BCR3_A7:
case SH7750_RTCOR_A7:
case SH7750_RTCNT_A7:
case SH7750_RTCSR_A7:
ignore_access("word write", addr);
return;
/* IO ports */
case SH7750_PDTRA_A7:
temp = porta_lines(s);
s->pdtra = mem_value;
porta_changed(s, temp);
return;
case SH7750_PDTRB_A7:
temp = portb_lines(s);
s->pdtrb = mem_value;
portb_changed(s, temp);
return;
case SH7750_RFCR_A7:
fprintf(stderr, "Write access to refresh count register\n");
s->rfcr = mem_value;
return;
case SH7750_SCLSR2_A7:
s->sclsr2 = mem_value;
return;
case SH7750_SCSCR2_A7:
s->scscr2 = mem_value;
scscr2_changed(s);
return;
case SH7750_SCFCR2_A7:
s->scfcr2 = mem_value;
return;
case SH7750_SCSMR2_A7:
s->scsmr2 = mem_value;
return;
case SH7750_TCR0_A7:
s->tcr0 = mem_value;
return;
case SH7750_GPIOIC_A7:
s->gpioic = mem_value;
if (mem_value != 0) {
fprintf(stderr, "I/O interrupts not implemented\n");
assert(0);
}
return;
default:
error_access("word write", addr);
assert(0);
}
}
static void sh7750_mem_writel(void *opaque, target_phys_addr_t addr,
uint32_t mem_value)
{
SH7750State *s = opaque;
uint16_t temp;
switch (addr) {
/* SDRAM controller */
case SH7750_BCR1_A7:
case SH7750_BCR4_A7:
case SH7750_WCR1_A7:
case SH7750_WCR2_A7:
case SH7750_WCR3_A7:
case SH7750_MCR_A7:
ignore_access("long write", addr);
return;
/* IO ports */
case SH7750_PCTRA_A7:
temp = porta_lines(s);
s->pctra = mem_value;
s->portdira = portdir(mem_value);
s->portpullupa = portpullup(mem_value);
porta_changed(s, temp);
return;
case SH7750_PCTRB_A7:
temp = portb_lines(s);
s->pctrb = mem_value;
s->portdirb = portdir(mem_value);
s->portpullupb = portpullup(mem_value);
portb_changed(s, temp);
return;
case SH7750_TCNT0_A7:
s->tcnt0 = mem_value & 0xf;
return;
case SH7750_MMUCR_A7:
s->cpu->mmucr = mem_value;
return;
case SH7750_PTEH_A7:
s->cpu->pteh = mem_value;
return;
case SH7750_PTEL_A7:
s->cpu->ptel = mem_value;
return;
case SH7750_TTB_A7:
s->cpu->ttb = mem_value;
return;
case SH7750_TEA_A7:
s->cpu->tea = mem_value;
return;
case SH7750_TRA_A7:
s->cpu->tra = mem_value & 0x000007ff;
return;
case SH7750_EXPEVT_A7:
s->cpu->expevt = mem_value & 0x000007ff;
return;
case SH7750_INTEVT_A7:
s->cpu->intevt = mem_value & 0x000007ff;
return;
case SH7750_CCR_A7:
s->ccr = mem_value;
return;
default:
error_access("long write", addr);
assert(0);
}
}
static CPUReadMemoryFunc *sh7750_mem_read[] = {
sh7750_mem_readb,
sh7750_mem_readw,
sh7750_mem_readl
};
static CPUWriteMemoryFunc *sh7750_mem_write[] = {
sh7750_mem_writeb,
sh7750_mem_writew,
sh7750_mem_writel
};
SH7750State *sh7750_init(CPUSH4State * cpu)
{
SH7750State *s;
int sh7750_io_memory;
s = qemu_mallocz(sizeof(SH7750State));
s->cpu = cpu;
s->periph_freq = 60000000; /* 60MHz */
sh7750_io_memory = cpu_register_io_memory(0,
sh7750_mem_read,
sh7750_mem_write, s);
cpu_register_physical_memory(0x1c000000, 0x04000000, sh7750_io_memory);
init_timers(s);
init_serial_ports(s);
return s;
}

128
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@ -0,0 +1,128 @@
#include "vl.h"
#include "sh7750_regs.h"
#define REGNAME(r) {r, #r},
typedef struct {
uint32_t regaddr;
const char *regname;
} regname_t;
static regname_t regnames[] = {
REGNAME(SH7750_PTEH_A7)
REGNAME(SH7750_PTEL_A7)
REGNAME(SH7750_PTEA_A7)
REGNAME(SH7750_TTB_A7)
REGNAME(SH7750_TEA_A7)
REGNAME(SH7750_MMUCR_A7)
REGNAME(SH7750_CCR_A7)
REGNAME(SH7750_QACR0_A7)
REGNAME(SH7750_QACR1_A7)
REGNAME(SH7750_TRA_A7)
REGNAME(SH7750_EXPEVT_A7)
REGNAME(SH7750_INTEVT_A7)
REGNAME(SH7750_STBCR_A7)
REGNAME(SH7750_STBCR2_A7)
REGNAME(SH7750_FRQCR_A7)
REGNAME(SH7750_WTCNT_A7)
REGNAME(SH7750_WTCSR_A7)
REGNAME(SH7750_R64CNT_A7)
REGNAME(SH7750_RSECCNT_A7)
REGNAME(SH7750_RMINCNT_A7)
REGNAME(SH7750_RHRCNT_A7)
REGNAME(SH7750_RWKCNT_A7)
REGNAME(SH7750_RDAYCNT_A7)
REGNAME(SH7750_RMONCNT_A7)
REGNAME(SH7750_RYRCNT_A7)
REGNAME(SH7750_RSECAR_A7)
REGNAME(SH7750_RMINAR_A7)
REGNAME(SH7750_RHRAR_A7)
REGNAME(SH7750_RWKAR_A7)
REGNAME(SH7750_RDAYAR_A7)
REGNAME(SH7750_RMONAR_A7)
REGNAME(SH7750_RCR1_A7)
REGNAME(SH7750_RCR2_A7)
REGNAME(SH7750_TOCR_A7)
REGNAME(SH7750_TSTR_A7)
REGNAME(SH7750_TCOR0_A7)
REGNAME(SH7750_TCOR1_A7)
REGNAME(SH7750_TCOR2_A7)
REGNAME(SH7750_TCNT0_A7)
REGNAME(SH7750_TCNT1_A7)
REGNAME(SH7750_TCNT2_A7)
REGNAME(SH7750_TCR0_A7)
REGNAME(SH7750_TCR1_A7)
REGNAME(SH7750_TCR2_A7)
REGNAME(SH7750_TCPR2_A7)
REGNAME(SH7750_BCR1_A7)
REGNAME(SH7750_BCR2_A7)
REGNAME(SH7750_WCR1_A7)
REGNAME(SH7750_WCR2_A7)
REGNAME(SH7750_WCR3_A7)
REGNAME(SH7750_MCR_A7)
REGNAME(SH7750_PCR_A7)
REGNAME(SH7750_RTCSR_A7)
REGNAME(SH7750_RTCNT_A7)
REGNAME(SH7750_RTCOR_A7)
REGNAME(SH7750_RFCR_A7)
REGNAME(SH7750_SAR0_A7)
REGNAME(SH7750_SAR1_A7)
REGNAME(SH7750_SAR2_A7)
REGNAME(SH7750_SAR3_A7)
REGNAME(SH7750_DAR0_A7)
REGNAME(SH7750_DAR1_A7)
REGNAME(SH7750_DAR2_A7)
REGNAME(SH7750_DAR3_A7)
REGNAME(SH7750_DMATCR0_A7)
REGNAME(SH7750_DMATCR1_A7)
REGNAME(SH7750_DMATCR2_A7)
REGNAME(SH7750_DMATCR3_A7)
REGNAME(SH7750_CHCR0_A7)
REGNAME(SH7750_CHCR1_A7)
REGNAME(SH7750_CHCR2_A7)
REGNAME(SH7750_CHCR3_A7)
REGNAME(SH7750_DMAOR_A7)
REGNAME(SH7750_SCRDR1_A7)
REGNAME(SH7750_SCRDR2_A7)
REGNAME(SH7750_SCTDR1_A7)
REGNAME(SH7750_SCTDR2_A7)
REGNAME(SH7750_SCSMR1_A7)
REGNAME(SH7750_SCSMR2_A7)
REGNAME(SH7750_SCSCR1_A7)
REGNAME(SH7750_SCSCR2_A7)
REGNAME(SH7750_SCSSR1_A7)
REGNAME(SH7750_SCSFR2_A7)
REGNAME(SH7750_SCSPTR1_A7)
REGNAME(SH7750_SCSPTR2_A7)
REGNAME(SH7750_SCBRR1_A7)
REGNAME(SH7750_SCBRR2_A7)
REGNAME(SH7750_SCFCR2_A7)
REGNAME(SH7750_SCFDR2_A7)
REGNAME(SH7750_SCLSR2_A7)
REGNAME(SH7750_SCSCMR1_A7)
REGNAME(SH7750_PCTRA_A7)
REGNAME(SH7750_PDTRA_A7)
REGNAME(SH7750_PCTRB_A7)
REGNAME(SH7750_PDTRB_A7)
REGNAME(SH7750_GPIOIC_A7)
REGNAME(SH7750_ICR_A7)
REGNAME(SH7750_IPRA_A7)
REGNAME(SH7750_IPRB_A7)
REGNAME(SH7750_IPRC_A7)
REGNAME(SH7750_BCR3_A7)
REGNAME(SH7750_BCR4_A7)
REGNAME(SH7750_PRECHARGE0_A7)
REGNAME(SH7750_PRECHARGE1_A7) {(uint32_t) - 1, 0}
};
const char *regname(uint32_t addr)
{
unsigned int i;
for (i = 0; regnames[i].regaddr != (uint32_t) - 1; i++) {
if (regnames[i].regaddr == addr)
return regnames[i].regname;
}
return "<unknown reg>";
}

6
hw/sh7750_regnames.h Normal file
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@ -0,0 +1,6 @@
#ifndef _SH7750_REGNAMES_H
#define _SH7750_REGNAMES_H
const char *regname(uint32_t addr);
#endif /* _SH7750_REGNAMES_H */

1623
hw/sh7750_regs.h Normal file
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File diff suppressed because it is too large Load Diff

111
hw/shix.c Normal file
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@ -0,0 +1,111 @@
/*
* SHIX 2.0 board description
*
* Copyright (c) 2005 Samuel Tardieu
*
* Permission is hereby granted, free of charge, to any person obtaining a copy
* of this software and associated documentation files (the "Software"), to deal
* in the Software without restriction, including without limitation the rights
* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
* copies of the Software, and to permit persons to whom the Software is
* furnished to do so, subject to the following conditions:
*
* The above copyright notice and this permission notice shall be included in
* all copies or substantial portions of the Software.
*
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
* THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
* OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
* THE SOFTWARE.
*/
/*
Shix 2.0 board by Alexis Polti, described at
http://perso.enst.fr/~polti/realisations/shix20/
More information in target-sh4/README.sh4
*/
#include "vl.h"
#define BIOS_FILENAME "shix_bios.bin"
#define BIOS_ADDRESS 0xA0000000
void DMA_run(void)
{
/* XXXXX */
}
void irq_info(void)
{
/* XXXXX */
}
void pic_set_irq(int irq, int level)
{
/* XXXXX */
}
void pic_info()
{
/* XXXXX */
}
void vga_update_display()
{
/* XXXXX */
}
void vga_invalidate_display()
{
/* XXXXX */
}
void vga_screen_dump(const char *filename)
{
/* XXXXX */
}
void shix_init(int ram_size, int vga_ram_size, int boot_device,
DisplayState * ds, const char **fd_filename, int snapshot,
const char *kernel_filename, const char *kernel_cmdline,
const char *initrd_filename)
{
int ret;
CPUState *env;
struct SH7750State *s;
printf("Initializing CPU\n");
env = cpu_init();
/* Allocate memory space */
printf("Allocating ROM\n");
cpu_register_physical_memory(0x00000000, 0x00004000, IO_MEM_ROM);
printf("Allocating SDRAM 1\n");
cpu_register_physical_memory(0x08000000, 0x01000000, 0x00004000);
printf("Allocating SDRAM 2\n");
cpu_register_physical_memory(0x0c000000, 0x01000000, 0x01004000);
/* Load BIOS in 0 (and access it through P2, 0xA0000000) */
printf("%s: load BIOS '%s'\n", __func__, BIOS_FILENAME);
ret = load_image(BIOS_FILENAME, phys_ram_base);
if (ret < 0) { /* Check bios size */
fprintf(stderr, "ret=%d\n", ret);
fprintf(stderr, "qemu: could not load SHIX bios '%s'\n",
BIOS_FILENAME);
exit(1);
}
/* Register peripherals */
s = sh7750_init(env);
/* XXXXX Check success */
tc58128_init(s, "shix_linux_nand.bin", NULL);
fprintf(stderr, "initialization terminated\n");
}
QEMUMachine shix_machine = {
"shix",
"shix card",
shix_init
};

181
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@ -0,0 +1,181 @@
#include <assert.h>
#include "vl.h"
#define CE1 0x0100
#define CE2 0x0200
#define RE 0x0400
#define WE 0x0800
#define ALE 0x1000
#define CLE 0x2000
#define RDY1 0x4000
#define RDY2 0x8000
#define RDY(n) ((n) == 0 ? RDY1 : RDY2)
typedef enum { WAIT, READ1, READ2, READ3 } state_t;
typedef struct {
uint8_t *flash_contents;
state_t state;
uint32_t address;
uint8_t address_cycle;
} tc58128_dev;
static tc58128_dev tc58128_devs[2];
#define FLASH_SIZE (16*1024*1024)
void init_dev(tc58128_dev * dev, char *filename)
{
int ret, blocks;
dev->state = WAIT;
dev->flash_contents = qemu_mallocz(FLASH_SIZE);
memset(dev->flash_contents, 0xff, FLASH_SIZE);
if (!dev->flash_contents) {
fprintf(stderr, "could not alloc memory for flash\n");
exit(1);
}
if (filename) {
/* Load flash image skipping the first block */
ret = load_image(filename, dev->flash_contents + 528 * 32);
if (ret < 0) {
fprintf(stderr, "ret=%d\n", ret);
fprintf(stderr, "qemu: could not load flash image %s\n",
filename);
exit(1);
} else {
/* Build first block with number of blocks */
blocks = (ret + 528 * 32 - 1) / (528 * 32);
dev->flash_contents[0] = blocks & 0xff;
dev->flash_contents[1] = (blocks >> 8) & 0xff;
dev->flash_contents[2] = (blocks >> 16) & 0xff;
dev->flash_contents[3] = (blocks >> 24) & 0xff;
fprintf(stderr, "loaded %d bytes for %s into flash\n", ret,
filename);
}
}
}
void handle_command(tc58128_dev * dev, uint8_t command)
{
switch (command) {
case 0xff:
fprintf(stderr, "reset flash device\n");
dev->state = WAIT;
break;
case 0x00:
fprintf(stderr, "read mode 1\n");
dev->state = READ1;
dev->address_cycle = 0;
break;
case 0x01:
fprintf(stderr, "read mode 2\n");
dev->state = READ2;
dev->address_cycle = 0;
break;
case 0x50:
fprintf(stderr, "read mode 3\n");
dev->state = READ3;
dev->address_cycle = 0;
break;
default:
fprintf(stderr, "unknown flash command 0x%02x\n", command);
assert(0);
}
}
void handle_address(tc58128_dev * dev, uint8_t data)
{
switch (dev->state) {
case READ1:
case READ2:
case READ3:
switch (dev->address_cycle) {
case 0:
dev->address = data;
if (dev->state == READ2)
dev->address |= 0x100;
else if (dev->state == READ3)
dev->address |= 0x200;
break;
case 1:
dev->address += data * 528 * 0x100;
break;
case 2:
dev->address += data * 528;
fprintf(stderr, "address pointer in flash: 0x%08x\n",
dev->address);
break;
default:
/* Invalid data */
assert(0);
}
dev->address_cycle++;
break;
default:
assert(0);
}
}
uint8_t handle_read(tc58128_dev * dev)
{
#if 0
if (dev->address % 0x100000 == 0)
fprintf(stderr, "reading flash at address 0x%08x\n", dev->address);
#endif
return dev->flash_contents[dev->address++];
}
/* We never mark the device as busy, so interrupts cannot be triggered
XXXXX */
int tc58128_cb(uint16_t porta, uint16_t portb,
uint16_t * periph_pdtra, uint16_t * periph_portadir,
uint16_t * periph_pdtrb, uint16_t * periph_portbdir)
{
int dev;
if ((porta & CE1) == 0)
dev = 0;
else if ((porta & CE2) == 0)
dev = 1;
else
return 0; /* No device selected */
if ((porta & RE) && (porta & WE)) {
/* Nothing to do, assert ready and return to input state */
*periph_portadir &= 0xff00;
*periph_portadir |= RDY(dev);
*periph_pdtra |= RDY(dev);
return 1;
}
if (porta & CLE) {
/* Command */
assert((porta & WE) == 0);
handle_command(&tc58128_devs[dev], porta & 0x00ff);
} else if (porta & ALE) {
assert((porta & WE) == 0);
handle_address(&tc58128_devs[dev], porta & 0x00ff);
} else if ((porta & RE) == 0) {
*periph_portadir |= 0x00ff;
*periph_pdtra &= 0xff00;
*periph_pdtra |= handle_read(&tc58128_devs[dev]);
} else {
assert(0);
}
return 1;
}
static sh7750_io_device tc58128 = {
RE | WE, /* Port A triggers */
0, /* Port B triggers */
tc58128_cb /* Callback */
};
int tc58128_init(struct SH7750State *s, char *zone1, char *zone2)
{
init_dev(&tc58128_devs[0], zone1);
init_dev(&tc58128_devs[1], zone2);
return sh7750_register_io_device(s, &tc58128);
}

150
target-sh4/README.sh4 Normal file
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@ -0,0 +1,150 @@
qemu target: sh4
author: Samuel Tardieu <sam@rfc1149.net>
last modified: Tue Dec 6 07:22:44 CET 2005
The sh4 target is not ready at all yet for integration in qemu. This
file describes the current state of implementation.
Most places requiring attention and/or modification can be detected by
looking for "XXXXX" or "assert (0)".
The sh4 core is located in target-sh4/*, while the 7750 peripheral
features (IO ports for example) are located in hw/sh7750.[ch]. The
main board description is in hw/shix.c, and the NAND flash in
hw/tc58128.[ch].
All the shortcomings indicated here will eventually be resolved. This
is a work in progress. Features are added in a semi-random order: if a
point is blocking to progress on booting the Linux kernel for the shix
board, it is addressed first; if feedback is necessary and no progress
can be made on blocking points until it is received, a random feature
is worked on.
Goals
-----
The primary model being worked on is the soft MMU target to be able to
emulate the Shix 2.0 board by Alexis Polti, described at
http://perso.enst.fr/~polti/realisations/shix20/
Ultimately, qemu will be coupled with a system C or a verilog
simulator to simulate the whole board functionalities.
A sh4 user-mode has also somewhat started but will be worked on
afterwards. The goal is to automate tests for GNAT (GNU Ada) compiler
that I ported recently to the sh4-linux target.
Registers
---------
16 general purpose registers are available at any time. The first 8
registers are banked and the non-directly visible ones can be accessed
by privileged instructions. In qemu, we define 24 general purpose
registers and the code generation use either [0-7]+[8-15] or
[16-23]+[8-15] depending on the MD and RB flags in the sr
configuration register.
Instructions
------------
Most sh4 instructions have been implemented. The missing ones at this
time are:
- FPU related instructions
- LDTLB to load a new MMU entry
- SLEEP to put the processor in sleep mode
Most instructions could be optimized a lot. This will be worked on
after the current model is fully functional unless debugging
convenience requires that it is done early.
Many instructions did not have a chance to be tested yet. The plan is
to implement unit and regression testing of those in the future.
MMU
---
The MMU is implemented in the sh4 core. MMU management has not been
tested at all yet. In the sh7750, it can be manipulated through memory
mapped registers and this part has not yet been implemented.
Exceptions
----------
Exceptions are implemented as described in the sh4 reference manual
but have not been tested yet. They do not use qemu EXCP_ features
yet.
IRQ
---
IRQ are not implemented yet.
Peripheral features
-------------------
+ Serial ports
Configuration and use of the first serial port (SCI) without
interrupts is supported. Input has not yet been tested.
Configuration of the second serial port (SCIF) is supported. FIFO
handling infrastructure has been started but is not completed yet.
+ GPIO ports
GPIO ports have been implemented. A registration function allows
external modules to register interest in some port changes (see
hw/tc58128.[ch] for an example) and will be called back. Interrupt
generation is not yet supported but some infrastructure is in place
for this purpose. Note that in the current model a peripheral module
cannot directly simulate a H->L->H input port transition and have an
interrupt generated on the low level.
+ TC58128 NAND flash
TC58128 NAND flash is partially implemented through GPIO ports. It
supports reading from flash.
GDB
---
GDB remote target support has been implemented and lightly tested.
Files
-----
File names are harcoded at this time. The bootloader must be stored in
shix_bios.bin in the current directory. The initial Linux image must
be stored in shix_linux_nand.bin in the current directory in NAND
format. Test files can be obtained from
http://perso.enst.fr/~polti/robot/ as well as the various datasheets I
use.
qemu disk parameter on the command line is unused. You can supply any
existing image and it will be ignored. As the goal is to simulate an
embedded target, it is not clear how this parameter will be handled in
the future.
To build an ELF kernel image from the NAND image, 16 bytes have to be
stripped off the end of every 528 bytes, keeping only 512 of them. The
following Python code snippet does it:
#! /usr/bin/python
def denand (infd, outfd):
while True:
d = infd.read (528)
if not d: return
outfd.write (d[:512])
if __name__ == '__main__':
import sys
denand (open (sys.argv[1], 'rb'),
open (sys.argv[2], 'wb'))
Style isssues
-------------
There is currently a mix between my style (space before opening
parenthesis) and qemu style. This will be resolved before final
integration is proposed.

2
vl.c
View File

@ -4863,6 +4863,8 @@ void register_machines(void)
qemu_register_machine(&integratorcp926_machine);
qemu_register_machine(&integratorcp1026_machine);
qemu_register_machine(&versatilepb_machine);
#elif defined(TARGET_SH4)
qemu_register_machine(&shix_machine);
#else
#error unsupported CPU
#endif

25
vl.h
View File

@ -842,6 +842,9 @@ extern QEMUMachine heathrow_machine;
/* mips_r4k.c */
extern QEMUMachine mips_machine;
/* shix.c */
extern QEMUMachine shix_machine;
#ifdef TARGET_PPC
ppc_tb_t *cpu_ppc_tb_init (CPUState *env, uint32_t freq);
#endif
@ -1016,6 +1019,28 @@ void *pl190_init(uint32_t base, void *parent, int irq, int fiq);
void sp804_init(uint32_t base, void *pic, int irq);
void icp_pit_init(uint32_t base, void *pic, int irq);
/* sh7750.c */
struct SH7750State;
struct SH7750State *sh7750_init(CPUSH4State * cpu);
typedef struct {
/* The callback will be triggered if any of the designated lines change */
uint16_t portamask_trigger;
uint16_t portbmask_trigger;
/* Return 0 if no action was taken */
int (*port_change_cb) (uint16_t porta, uint16_t portb,
uint16_t * periph_pdtra,
uint16_t * periph_portdira,
uint16_t * periph_pdtrb,
uint16_t * periph_portdirb);
} sh7750_io_device;
int sh7750_register_io_device(struct SH7750State *s,
sh7750_io_device * device);
/* tc58128.c */
int tc58128_init(struct SH7750State *s, char *zone1, char *zone2);
#endif /* defined(QEMU_TOOL) */
/* monitor.c */