ppc/pnv: Introduce a POWER10 PnvChip and a powernv10 machine
This is an empty shell with the XSCOM bus and cores. The chip controllers will come later. Signed-off-by: Cédric Le Goater <clg@kaod.org> Message-Id: <20191205184454.10722-3-clg@kaod.org> Signed-off-by: David Gibson <david@gibson.dropbear.id.au>
This commit is contained in:
Cédric Le Goater
David Gibson
parent
7d37b274ff
commit
2b548a4255
158
hw/ppc/pnv.c
158
hw/ppc/pnv.c
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@ -317,6 +317,23 @@ static void pnv_chip_power9_dt_populate(PnvChip *chip, void *fdt)
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pnv_dt_lpc(chip, fdt, 0);
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}
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static void pnv_chip_power10_dt_populate(PnvChip *chip, void *fdt)
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{
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int i;
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pnv_dt_xscom(chip, fdt, 0);
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for (i = 0; i < chip->nr_cores; i++) {
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PnvCore *pnv_core = chip->cores[i];
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pnv_dt_core(chip, pnv_core, fdt);
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}
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if (chip->ram_size) {
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pnv_dt_memory(fdt, chip->chip_id, chip->ram_start, chip->ram_size);
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}
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}
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static void pnv_dt_rtc(ISADevice *d, void *fdt, int lpc_off)
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{
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uint32_t io_base = d->ioport_id;
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@ -467,6 +484,7 @@ static void *pnv_dt_create(MachineState *machine)
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{
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const char plat_compat8[] = "qemu,powernv8\0qemu,powernv\0ibm,powernv";
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const char plat_compat9[] = "qemu,powernv9\0ibm,powernv";
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const char plat_compat10[] = "qemu,powernv10\0ibm,powernv";
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PnvMachineState *pnv = PNV_MACHINE(machine);
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void *fdt;
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char *buf;
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@ -484,7 +502,10 @@ static void *pnv_dt_create(MachineState *machine)
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_FDT((fdt_setprop_cell(fdt, 0, "#size-cells", 0x2)));
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_FDT((fdt_setprop_string(fdt, 0, "model",
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"IBM PowerNV (emulated by qemu)")));
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if (pnv_is_power9(pnv)) {
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if (pnv_is_power10(pnv)) {
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_FDT((fdt_setprop(fdt, 0, "compatible", plat_compat10,
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sizeof(plat_compat10))));
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} else if (pnv_is_power9(pnv)) {
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_FDT((fdt_setprop(fdt, 0, "compatible", plat_compat9,
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sizeof(plat_compat9))));
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} else {
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@ -528,8 +549,8 @@ static void *pnv_dt_create(MachineState *machine)
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pnv_dt_bmc_sensors(pnv->bmc, fdt);
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}
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/* Create an extra node for power management on Power9 */
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if (pnv_is_power9(pnv)) {
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/* Create an extra node for power management on Power9 and Power10 */
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if (pnv_is_power9(pnv) || pnv_is_power10(pnv)) {
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pnv_dt_power_mgt(fdt);
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}
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@ -578,6 +599,12 @@ static ISABus *pnv_chip_power9_isa_create(PnvChip *chip, Error **errp)
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return pnv_lpc_isa_create(&chip9->lpc, false, errp);
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}
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static ISABus *pnv_chip_power10_isa_create(PnvChip *chip, Error **errp)
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{
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error_setg(errp, "No ISA bus!");
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return NULL;
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}
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static ISABus *pnv_isa_create(PnvChip *chip, Error **errp)
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{
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return PNV_CHIP_GET_CLASS(chip)->isa_create(chip, errp);
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@ -618,6 +645,13 @@ static void pnv_ipmi_bt_init(ISABus *bus, IPMIBmc *bmc, uint32_t irq)
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object_property_set_bool(obj, true, "realized", &error_fatal);
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}
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static void pnv_chip_power10_pic_print_info(PnvChip *chip, Monitor *mon)
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{
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/*
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* No interrupt controller yet
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*/;
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}
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static void pnv_init(MachineState *machine)
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{
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PnvMachineState *pnv = PNV_MACHINE(machine);
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@ -822,6 +856,11 @@ static uint32_t pnv_chip_core_pir_p9(PnvChip *chip, uint32_t core_id)
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return (chip->chip_id << 8) | (core_id << 2);
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}
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static uint32_t pnv_chip_core_pir_p10(PnvChip *chip, uint32_t core_id)
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{
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return (chip->chip_id << 8) | (core_id << 2);
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}
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static void pnv_chip_power9_intc_create(PnvChip *chip, PowerPCCPU *cpu,
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Error **errp)
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{
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@ -859,6 +898,27 @@ static void pnv_chip_power9_intc_destroy(PnvChip *chip, PowerPCCPU *cpu)
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pnv_cpu->intc = NULL;
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}
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static void pnv_chip_power10_intc_create(PnvChip *chip, PowerPCCPU *cpu,
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Error **errp)
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{
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PnvCPUState *pnv_cpu = pnv_cpu_state(cpu);
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/* Will be defined when the interrupt controller is */
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pnv_cpu->intc = NULL;
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}
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static void pnv_chip_power10_intc_reset(PnvChip *chip, PowerPCCPU *cpu)
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{
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;
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}
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static void pnv_chip_power10_intc_destroy(PnvChip *chip, PowerPCCPU *cpu)
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{
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PnvCPUState *pnv_cpu = pnv_cpu_state(cpu);
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pnv_cpu->intc = NULL;
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}
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/*
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* Allowed core identifiers on a POWER8 Processor Chip :
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*
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@ -886,6 +946,9 @@ static void pnv_chip_power9_intc_destroy(PnvChip *chip, PowerPCCPU *cpu)
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*/
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#define POWER9_CORE_MASK (0xffffffffffffffull)
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#define POWER10_CORE_MASK (0xffffffffffffffull)
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static void pnv_chip_power8_instance_init(Object *obj)
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{
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Pnv8Chip *chip8 = PNV8_CHIP(obj);
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@ -1246,6 +1309,56 @@ static void pnv_chip_power9_class_init(ObjectClass *klass, void *data)
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&k->parent_realize);
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}
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static void pnv_chip_power10_instance_init(Object *obj)
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{
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/*
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* No controllers yet
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*/
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;
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}
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static void pnv_chip_power10_realize(DeviceState *dev, Error **errp)
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{
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PnvChipClass *pcc = PNV_CHIP_GET_CLASS(dev);
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PnvChip *chip = PNV_CHIP(dev);
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Error *local_err = NULL;
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/* XSCOM bridge is first */
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pnv_xscom_realize(chip, PNV10_XSCOM_SIZE, &local_err);
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if (local_err) {
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error_propagate(errp, local_err);
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return;
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}
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sysbus_mmio_map(SYS_BUS_DEVICE(chip), 0, PNV10_XSCOM_BASE(chip));
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pcc->parent_realize(dev, &local_err);
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if (local_err) {
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error_propagate(errp, local_err);
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return;
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}
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}
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static void pnv_chip_power10_class_init(ObjectClass *klass, void *data)
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{
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DeviceClass *dc = DEVICE_CLASS(klass);
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PnvChipClass *k = PNV_CHIP_CLASS(klass);
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k->chip_type = PNV_CHIP_POWER10;
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k->chip_cfam_id = 0x120da04900008000ull; /* P10 DD1.0 (with NX) */
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k->cores_mask = POWER10_CORE_MASK;
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k->core_pir = pnv_chip_core_pir_p10;
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k->intc_create = pnv_chip_power10_intc_create;
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k->intc_reset = pnv_chip_power10_intc_reset;
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k->intc_destroy = pnv_chip_power10_intc_destroy;
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k->isa_create = pnv_chip_power10_isa_create;
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k->dt_populate = pnv_chip_power10_dt_populate;
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k->pic_print_info = pnv_chip_power10_pic_print_info;
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dc->desc = "PowerNV Chip POWER10";
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device_class_set_parent_realize(dc, pnv_chip_power10_realize,
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&k->parent_realize);
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}
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static void pnv_chip_core_sanitize(PnvChip *chip, Error **errp)
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{
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PnvChipClass *pcc = PNV_CHIP_GET_CLASS(chip);
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@ -1327,10 +1440,12 @@ static void pnv_chip_core_realize(PnvChip *chip, Error **errp)
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&error_fatal);
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/* Each core has an XSCOM MMIO region */
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if (!pnv_chip_is_power9(chip)) {
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xscom_core_base = PNV_XSCOM_EX_BASE(core_hwid);
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} else {
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if (pnv_chip_is_power10(chip)) {
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xscom_core_base = PNV10_XSCOM_EC_BASE(core_hwid);
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} else if (pnv_chip_is_power9(chip)) {
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xscom_core_base = PNV9_XSCOM_EC_BASE(core_hwid);
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} else {
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xscom_core_base = PNV_XSCOM_EX_BASE(core_hwid);
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}
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pnv_xscom_add_subregion(chip, xscom_core_base,
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@ -1558,6 +1673,14 @@ static void pnv_machine_power9_class_init(ObjectClass *oc, void *data)
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mc->alias = "powernv";
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}
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static void pnv_machine_power10_class_init(ObjectClass *oc, void *data)
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{
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MachineClass *mc = MACHINE_CLASS(oc);
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mc->desc = "IBM PowerNV (Non-Virtualized) POWER10";
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mc->default_cpu_type = POWERPC_CPU_TYPE_NAME("power10_v1.0");
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}
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static void pnv_machine_class_init(ObjectClass *oc, void *data)
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{
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MachineClass *mc = MACHINE_CLASS(oc);
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@ -1595,7 +1718,19 @@ static void pnv_machine_class_init(ObjectClass *oc, void *data)
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.parent = TYPE_PNV9_CHIP, \
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}
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#define DEFINE_PNV10_CHIP_TYPE(type, class_initfn) \
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{ \
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.name = type, \
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.class_init = class_initfn, \
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.parent = TYPE_PNV10_CHIP, \
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}
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static const TypeInfo types[] = {
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{
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.name = MACHINE_TYPE_NAME("powernv10"),
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.parent = TYPE_PNV_MACHINE,
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.class_init = pnv_machine_power10_class_init,
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},
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{
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.name = MACHINE_TYPE_NAME("powernv9"),
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.parent = TYPE_PNV_MACHINE,
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@ -1635,6 +1770,17 @@ static const TypeInfo types[] = {
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.abstract = true,
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},
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/*
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* P10 chip and variants
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*/
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{
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.name = TYPE_PNV10_CHIP,
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.parent = TYPE_PNV_CHIP,
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.instance_init = pnv_chip_power10_instance_init,
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.instance_size = sizeof(Pnv10Chip),
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},
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DEFINE_PNV10_CHIP_TYPE(TYPE_PNV_CHIP_POWER10, pnv_chip_power10_class_init),
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/*
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* P9 chip and variants
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*/
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@ -247,6 +247,7 @@ static void pnv_core_realize(DeviceState *dev, Error **errp)
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}
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snprintf(name, sizeof(name), "xscom-core.%d", cc->core_id);
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/* TODO: check PNV_XSCOM_EX_SIZE for p10 */
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pnv_xscom_region_init(&pc->xscom_regs, OBJECT(dev), pcc->xscom_ops,
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pc, name, PNV_XSCOM_EX_SIZE);
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@ -308,6 +309,14 @@ static void pnv_core_power9_class_init(ObjectClass *oc, void *data)
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pcc->xscom_ops = &pnv_core_power9_xscom_ops;
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}
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static void pnv_core_power10_class_init(ObjectClass *oc, void *data)
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{
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PnvCoreClass *pcc = PNV_CORE_CLASS(oc);
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/* TODO: Use the P9 XSCOMs for now on P10 */
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pcc->xscom_ops = &pnv_core_power9_xscom_ops;
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}
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static void pnv_core_class_init(ObjectClass *oc, void *data)
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{
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DeviceClass *dc = DEVICE_CLASS(oc);
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@ -337,6 +346,7 @@ static const TypeInfo pnv_core_infos[] = {
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DEFINE_PNV_CORE_TYPE(power8, "power8_v2.0"),
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DEFINE_PNV_CORE_TYPE(power8, "power8nvl_v1.0"),
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DEFINE_PNV_CORE_TYPE(power9, "power9_v2.0"),
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DEFINE_PNV_CORE_TYPE(power10, "power10_v1.0"),
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};
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DEFINE_TYPES(pnv_core_infos)
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@ -69,10 +69,16 @@ static uint32_t pnv_xscom_pcba(PnvChip *chip, uint64_t addr)
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{
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addr &= (PNV_XSCOM_SIZE - 1);
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if (pnv_chip_is_power9(chip)) {
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return addr >> 3;
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} else {
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switch (PNV_CHIP_GET_CLASS(chip)->chip_type) {
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case PNV_CHIP_POWER8E:
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case PNV_CHIP_POWER8:
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case PNV_CHIP_POWER8NVL:
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return ((addr >> 4) & ~0xfull) | ((addr >> 3) & 0xf);
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case PNV_CHIP_POWER9:
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case PNV_CHIP_POWER10:
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return addr >> 3;
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default:
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g_assert_not_reached();
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}
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}
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@ -307,6 +313,7 @@ static int xscom_dt_child(Object *child, void *opaque)
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static const char compat_p8[] = "ibm,power8-xscom\0ibm,xscom";
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static const char compat_p9[] = "ibm,power9-xscom\0ibm,xscom";
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static const char compat_p10[] = "ibm,power10-xscom\0ibm,xscom";
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int pnv_dt_xscom(PnvChip *chip, void *fdt, int root_offset)
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{
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@ -315,7 +322,10 @@ int pnv_dt_xscom(PnvChip *chip, void *fdt, int root_offset)
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ForeachPopulateArgs args;
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char *name;
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if (pnv_chip_is_power9(chip)) {
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if (pnv_chip_is_power10(chip)) {
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reg[0] = cpu_to_be64(PNV10_XSCOM_BASE(chip));
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reg[1] = cpu_to_be64(PNV10_XSCOM_SIZE);
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} else if (pnv_chip_is_power9(chip)) {
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reg[0] = cpu_to_be64(PNV9_XSCOM_BASE(chip));
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reg[1] = cpu_to_be64(PNV9_XSCOM_SIZE);
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} else {
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@ -332,7 +342,10 @@ int pnv_dt_xscom(PnvChip *chip, void *fdt, int root_offset)
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_FDT((fdt_setprop_cell(fdt, xscom_offset, "#size-cells", 1)));
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_FDT((fdt_setprop(fdt, xscom_offset, "reg", reg, sizeof(reg))));
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if (pnv_chip_is_power9(chip)) {
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if (pnv_chip_is_power10(chip)) {
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_FDT((fdt_setprop(fdt, xscom_offset, "compatible", compat_p10,
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sizeof(compat_p10))));
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} else if (pnv_chip_is_power9(chip)) {
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_FDT((fdt_setprop(fdt, xscom_offset, "compatible", compat_p9,
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sizeof(compat_p9))));
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} else {
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@ -43,6 +43,7 @@ typedef enum PnvChipType {
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PNV_CHIP_POWER8, /* AKA Venice */
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PNV_CHIP_POWER8NVL, /* AKA Naples */
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PNV_CHIP_POWER9, /* AKA Nimbus */
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PNV_CHIP_POWER10, /* AKA TBD */
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} PnvChipType;
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typedef struct PnvChip {
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@ -105,6 +106,14 @@ typedef struct Pnv9Chip {
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#define PNV9_PIR2FUSEDCORE(pir) (((pir) >> 3) & 0xf)
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#define PNV9_PIR2CHIP(pir) (((pir) >> 8) & 0x7f)
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#define TYPE_PNV10_CHIP "pnv10-chip"
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#define PNV10_CHIP(obj) OBJECT_CHECK(Pnv10Chip, (obj), TYPE_PNV10_CHIP)
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typedef struct Pnv10Chip {
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/*< private >*/
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PnvChip parent_obj;
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} Pnv10Chip;
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typedef struct PnvChipClass {
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/*< private >*/
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SysBusDeviceClass parent_class;
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@ -144,6 +153,10 @@ typedef struct PnvChipClass {
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#define PNV_CHIP_POWER9(obj) \
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OBJECT_CHECK(PnvChip, (obj), TYPE_PNV_CHIP_POWER9)
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#define TYPE_PNV_CHIP_POWER10 PNV_CHIP_TYPE_NAME("power10_v1.0")
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#define PNV_CHIP_POWER10(obj) \
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OBJECT_CHECK(PnvChip, (obj), TYPE_PNV_CHIP_POWER10)
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/*
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* This generates a HW chip id depending on an index, as found on a
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* two socket system with dual chip modules :
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@ -203,6 +216,16 @@ PnvChip *pnv_get_chip(uint32_t chip_id);
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#define PNV_FDT_ADDR 0x01000000
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#define PNV_TIMEBASE_FREQ 512000000ULL
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static inline bool pnv_chip_is_power10(const PnvChip *chip)
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{
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return PNV_CHIP_GET_CLASS(chip)->chip_type == PNV_CHIP_POWER10;
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}
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static inline bool pnv_is_power10(PnvMachineState *pnv)
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{
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return pnv_chip_is_power10(pnv->chips[0]);
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}
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/*
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||||
* BMC helpers
|
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*/
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@ -293,4 +316,14 @@ IPMIBmc *pnv_bmc_create(void);
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#define PNV9_HOMER_SIZE 0x0000000000300000ull
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#define PNV9_HOMER_BASE(chip) \
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(0x203ffd800000ull + ((uint64_t)PNV_CHIP_INDEX(chip)) * PNV9_HOMER_SIZE)
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||||
/*
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* POWER10 MMIO base addresses - 16TB stride per chip
|
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*/
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#define PNV10_CHIP_BASE(chip, base) \
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((base) + ((uint64_t) (chip)->chip_id << 44))
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#define PNV10_XSCOM_SIZE 0x0000000400000000ull
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#define PNV10_XSCOM_BASE(chip) PNV10_CHIP_BASE(chip, 0x00603fc00000000ull)
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||||
#endif /* PPC_PNV_H */
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||||
|
|
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|||
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|
@ -70,6 +70,9 @@ typedef struct PnvXScomInterfaceClass {
|
|||
#define PNV_XSCOM_OCC_BASE 0x0066000
|
||||
#define PNV_XSCOM_OCC_SIZE 0x6000
|
||||
|
||||
/*
|
||||
* Layout of the XSCOM PCB addresses (POWER 9)
|
||||
*/
|
||||
#define PNV9_XSCOM_EC_BASE(core) \
|
||||
((uint64_t)(((core) & 0x1F) + 0x20) << 24)
|
||||
#define PNV9_XSCOM_EC_SIZE 0x100000
|
||||
|
|
@ -87,6 +90,22 @@ typedef struct PnvXScomInterfaceClass {
|
|||
#define PNV9_XSCOM_XIVE_BASE 0x5013000
|
||||
#define PNV9_XSCOM_XIVE_SIZE 0x300
|
||||
|
||||
/*
|
||||
* Layout of the XSCOM PCB addresses (POWER 10)
|
||||
*/
|
||||
#define PNV10_XSCOM_EQ_CHIPLET(core) (0x20 + ((core) >> 2))
|
||||
#define PNV10_XSCOM_EQ(chiplet) ((chiplet) << 24)
|
||||
#define PNV10_XSCOM_EC(proc) \
|
||||
((0x2 << 16) | ((1 << (3 - (proc))) << 12))
|
||||
|
||||
#define PNV10_XSCOM_EQ_BASE(core) \
|
||||
((uint64_t) PNV10_XSCOM_EQ(PNV10_XSCOM_EQ_CHIPLET(core)))
|
||||
#define PNV10_XSCOM_EQ_SIZE 0x100000
|
||||
|
||||
#define PNV10_XSCOM_EC_BASE(core) \
|
||||
((uint64_t) PNV10_XSCOM_EQ_BASE(core) | PNV10_XSCOM_EC(core & 0x3))
|
||||
#define PNV10_XSCOM_EC_SIZE 0x100000
|
||||
|
||||
extern void pnv_xscom_realize(PnvChip *chip, uint64_t size, Error **errp);
|
||||
extern int pnv_dt_xscom(PnvChip *chip, void *fdt, int offset);
|
||||
|
||||
|
|
|
|||
Loading…
Reference in New Issue