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hw/timer/imx_epit: update interrupt state on CR write access

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The interrupt state can change due to:
- reset clears both SR.OCIF and CR.OCIE
- write to CR.EN or CR.OCIE

Signed-off-by: Axel Heider <axel.heider@hensoldt.net>
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
This commit is contained in:
Axel Heider 2022-10-25 20:32:30 +02:00 committed by Peter Maydell
parent 1ead962edf
commit 2ca267fd36
1 changed files with 12 additions and 4 deletions
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16
hw/timer/imx_epit.c
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@ -206,12 +206,20 @@ static void imx_epit_write(void *opaque, hwaddr offset, uint64_t value,
if (s->cr & CR_SWR) {
/* handle the reset */
imx_epit_reset(DEVICE(s));
/*
* TODO: could we 'break' here? following operations appear
* to duplicate the work imx_epit_reset() already did.
*/
}
/*
* The interrupt state can change due to:
* - reset clears both SR.OCIF and CR.OCIE
* - write to CR.EN or CR.OCIE
*/
imx_epit_update_int(s);
/*
* TODO: could we 'break' here for reset? following operations appear
* to duplicate the work imx_epit_reset() already did.
*/
ptimer_transaction_begin(s->timer_cmp);
ptimer_transaction_begin(s->timer_reload);