s390x/tcg: Rework MMU selection for instruction fetches
Instructions are always fetched from primary address space, except when in home address mode. Perform the selection directly in cpu_mmu_index(). get_mem_index() is only used to perform data access, instructions are fetched via cpu_lduw_code(), which translates to cpu_mmu_index(env, true). We don't care about restricting the access permissions of the TLB entries anymore, as we no longer enter PRIMARY entries into the SECONDARY MMU. Cleanup related code a bit. Reviewed-by: Thomas Huth <thuth@redhat.com> Signed-off-by: David Hildenbrand <david@redhat.com> Reviewed-by: Cornelia Huck <cohuck@redhat.com> Message-Id: <20190816084708.602-4-david@redhat.com> Signed-off-by: Cornelia Huck <cohuck@redhat.com>
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@ -332,6 +332,13 @@ static inline int cpu_mmu_index(CPUS390XState *env, bool ifetch)
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return MMU_REAL_IDX;
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return MMU_REAL_IDX;
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}
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}
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if (ifetch) {
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if ((env->psw.mask & PSW_MASK_ASC) == PSW_ASC_HOME) {
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return MMU_HOME_IDX;
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}
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return MMU_PRIMARY_IDX;
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}
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switch (env->psw.mask & PSW_MASK_ASC) {
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switch (env->psw.mask & PSW_MASK_ASC) {
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case PSW_ASC_PRIMARY:
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case PSW_ASC_PRIMARY:
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return MMU_PRIMARY_IDX;
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return MMU_PRIMARY_IDX;
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@ -350,8 +350,9 @@ int mmu_translate(CPUS390XState *env, target_ulong vaddr, int rw, uint64_t asc,
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{
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{
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static S390SKeysState *ss;
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static S390SKeysState *ss;
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static S390SKeysClass *skeyclass;
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static S390SKeysClass *skeyclass;
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int r = -1;
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uint64_t asce;
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uint8_t key;
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uint8_t key;
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int r;
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if (unlikely(!ss)) {
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if (unlikely(!ss)) {
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ss = s390_get_skeys_device();
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ss = s390_get_skeys_device();
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@ -381,36 +382,21 @@ int mmu_translate(CPUS390XState *env, target_ulong vaddr, int rw, uint64_t asc,
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if (!(env->psw.mask & PSW_MASK_DAT)) {
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if (!(env->psw.mask & PSW_MASK_DAT)) {
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*raddr = vaddr;
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*raddr = vaddr;
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r = 0;
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goto nodat;
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goto out;
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}
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}
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switch (asc) {
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switch (asc) {
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case PSW_ASC_PRIMARY:
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case PSW_ASC_PRIMARY:
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PTE_DPRINTF("%s: asc=primary\n", __func__);
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PTE_DPRINTF("%s: asc=primary\n", __func__);
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r = mmu_translate_asce(env, vaddr, asc, env->cregs[1], raddr, flags,
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asce = env->cregs[1];
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rw, exc);
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break;
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break;
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case PSW_ASC_HOME:
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case PSW_ASC_HOME:
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PTE_DPRINTF("%s: asc=home\n", __func__);
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PTE_DPRINTF("%s: asc=home\n", __func__);
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r = mmu_translate_asce(env, vaddr, asc, env->cregs[13], raddr, flags,
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asce = env->cregs[13];
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rw, exc);
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break;
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break;
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case PSW_ASC_SECONDARY:
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case PSW_ASC_SECONDARY:
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PTE_DPRINTF("%s: asc=secondary\n", __func__);
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PTE_DPRINTF("%s: asc=secondary\n", __func__);
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/*
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asce = env->cregs[7];
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* Instruction: Primary
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* Data: Secondary
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*/
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if (rw == MMU_INST_FETCH) {
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r = mmu_translate_asce(env, vaddr, PSW_ASC_PRIMARY, env->cregs[1],
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raddr, flags, rw, exc);
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*flags &= ~(PAGE_READ | PAGE_WRITE);
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} else {
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r = mmu_translate_asce(env, vaddr, PSW_ASC_SECONDARY, env->cregs[7],
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raddr, flags, rw, exc);
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*flags &= ~(PAGE_EXEC);
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}
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break;
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break;
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case PSW_ASC_ACCREG:
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case PSW_ASC_ACCREG:
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default:
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default:
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@ -418,11 +404,17 @@ int mmu_translate(CPUS390XState *env, target_ulong vaddr, int rw, uint64_t asc,
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break;
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break;
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}
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}
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out:
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/* perform the DAT translation */
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r = mmu_translate_asce(env, vaddr, asc, asce, raddr, flags, rw, exc);
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if (r) {
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return r;
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}
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nodat:
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/* Convert real address -> absolute address */
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/* Convert real address -> absolute address */
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*raddr = mmu_real2abs(env, *raddr);
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*raddr = mmu_real2abs(env, *raddr);
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if (r == 0 && *raddr < ram_size) {
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if (*raddr < ram_size) {
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r = skeyclass->get_skeys(ss, *raddr / TARGET_PAGE_SIZE, 1, &key);
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r = skeyclass->get_skeys(ss, *raddr / TARGET_PAGE_SIZE, 1, &key);
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if (r) {
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if (r) {
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trace_get_skeys_nonzero(r);
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trace_get_skeys_nonzero(r);
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@ -444,7 +436,7 @@ int mmu_translate(CPUS390XState *env, target_ulong vaddr, int rw, uint64_t asc,
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}
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}
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}
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}
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return r;
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return 0;
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}
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}
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/**
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/**
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